arch/powerpc/cpu/mpc8xxx/cpu.c

   1 /*
   2  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
   5  * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
   6  * cpu specific common code for 85xx/86xx processors.
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <config.h>
  27 #include <common.h>
  28 #include <command.h>
  29 #include <tsec.h>
  30 #include <fm_eth.h>
  31 #include <netdev.h>
  32 #include <asm/cache.h>
  33 #include <asm/io.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 static struct cpu_type cpu_type_list[] = {
  38 #if defined(CONFIG_MPC85xx)
  39         CPU_TYPE_ENTRY(8533, 8533, 1),
  40         CPU_TYPE_ENTRY(8535, 8535, 1),
  41         CPU_TYPE_ENTRY(8536, 8536, 1),
  42         CPU_TYPE_ENTRY(8540, 8540, 1),
  43         CPU_TYPE_ENTRY(8541, 8541, 1),
  44         CPU_TYPE_ENTRY(8543, 8543, 1),
  45         CPU_TYPE_ENTRY(8544, 8544, 1),
  46         CPU_TYPE_ENTRY(8545, 8545, 1),
  47         CPU_TYPE_ENTRY(8547, 8547, 1),
  48         CPU_TYPE_ENTRY(8548, 8548, 1),
  49         CPU_TYPE_ENTRY(8555, 8555, 1),
  50         CPU_TYPE_ENTRY(8560, 8560, 1),
  51         CPU_TYPE_ENTRY(8567, 8567, 1),
  52         CPU_TYPE_ENTRY(8568, 8568, 1),
  53         CPU_TYPE_ENTRY(8569, 8569, 1),
  54         CPU_TYPE_ENTRY(8572, 8572, 2),
  55         CPU_TYPE_ENTRY(P1010, P1010, 1),
  56         CPU_TYPE_ENTRY(P1011, P1011, 1),
  57         CPU_TYPE_ENTRY(P1012, P1012, 1),
  58         CPU_TYPE_ENTRY(P1013, P1013, 1),
  59         CPU_TYPE_ENTRY(P1014, P1014, 1),
  60         CPU_TYPE_ENTRY(P1017, P1017, 1),
  61         CPU_TYPE_ENTRY(P1020, P1020, 2),
  62         CPU_TYPE_ENTRY(P1021, P1021, 2),
  63         CPU_TYPE_ENTRY(P1022, P1022, 2),
  64         CPU_TYPE_ENTRY(P1023, P1023, 2),
  65         CPU_TYPE_ENTRY(P1024, P1024, 2),
  66         CPU_TYPE_ENTRY(P1025, P1025, 2),
  67         CPU_TYPE_ENTRY(P2010, P2010, 1),
  68         CPU_TYPE_ENTRY(P2020, P2020, 2),
  69         CPU_TYPE_ENTRY(P2040, P2040, 4),
  70         CPU_TYPE_ENTRY(P2041, P2041, 4),
  71         CPU_TYPE_ENTRY(P3041, P3041, 4),
  72         CPU_TYPE_ENTRY(P4040, P4040, 4),
  73         CPU_TYPE_ENTRY(P4080, P4080, 8),
  74         CPU_TYPE_ENTRY(P5010, P5010, 1),
  75         CPU_TYPE_ENTRY(P5020, P5020, 2),
  76         CPU_TYPE_ENTRY(P5021, P5021, 2),
  77         CPU_TYPE_ENTRY(P5040, P5040, 4),
  78         CPU_TYPE_ENTRY(T4240, T4240, 0),
  79         CPU_TYPE_ENTRY(T4120, T4120, 0),
  80         CPU_TYPE_ENTRY(B4860, B4860, 0),
  81         CPU_TYPE_ENTRY(G4860, G4860, 0),
  82         CPU_TYPE_ENTRY(G4060, G4060, 0),
  83         CPU_TYPE_ENTRY(B4440, B4440, 0),
  84         CPU_TYPE_ENTRY(G4440, G4440, 0),
  85         CPU_TYPE_ENTRY(B4420, B4420, 0),
  86         CPU_TYPE_ENTRY(B4220, B4220, 0),
  87         CPU_TYPE_ENTRY(BSC9130, 9130, 1),
  88         CPU_TYPE_ENTRY(BSC9131, 9131, 1),
  89         CPU_TYPE_ENTRY(BSC9132, 9132, 2),
  90         CPU_TYPE_ENTRY(BSC9232, 9232, 2),
  91 #elif defined(CONFIG_MPC86xx)
  92         CPU_TYPE_ENTRY(8610, 8610, 1),
  93         CPU_TYPE_ENTRY(8641, 8641, 2),
  94         CPU_TYPE_ENTRY(8641D, 8641D, 2),
  95 #endif
  96 };
  97
  98 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  99 u32 compute_ppc_cpumask(void)
 100 {
 101         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 102         int i = 0, count = 0;
 103         u32 cluster, mask = 0;
 104
 105         do {
 106                 int j;
 107                 cluster = in_be32(&gur->tp_cluster[i++].lower);
 108                 for (j = 0; j < 4; j++) {
 109                         u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
 110                         u32 type = in_be32(&gur->tp_ityp[idx]);
 111
 112                         if (type & TP_ITYP_AV) {
 113                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
 114                                         mask |= 1 << count;
 115                         }
 116                         count++;
 117                 }
 118         } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
 119
 120         return mask;
 121 }
 122 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 123 /*
 124  * Before chassis genenration 2, the cpumask should be hard-coded.
 125  * In case of cpu type unknown or cpumask unset, use 1 as fail save.
 126  */
 127 #define compute_ppc_cpumask()   1
 128 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 129
 130 static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
 131
 132 struct cpu_type *identify_cpu(u32 ver)
 133 {
 134         int i;
 135         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) {
 136                 if (cpu_type_list[i].soc_ver == ver)
 137                         return &cpu_type_list[i];
 138         }
 139         return &cpu_type_unknown;
 140 }
 141
 142 #define MPC8xxx_PICFRR_NCPU_MASK  0x00001f00
 143 #define MPC8xxx_PICFRR_NCPU_SHIFT 8
 144
 145 /*
 146  * Return a 32-bit mask indicating which cores are present on this SOC.
 147  */
 148 u32 cpu_mask(void)
 149 {
 150         ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
 151         struct cpu_type *cpu = gd->arch.cpu;
 152
 153         /* better to query feature reporting register than just assume 1 */
 154         if (cpu == &cpu_type_unknown)
 155         return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
 156                         MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
 157
 158         if (cpu->num_cores == 0)
 159                 return compute_ppc_cpumask();
 160
 161         return cpu->mask;
 162 }
 163
 164 /*
 165  * Return the number of cores on this SOC.
 166  */
 167 int cpu_numcores(void)
 168 {
 169         struct cpu_type *cpu = gd->arch.cpu;
 170
 171         /*
 172          * Report # of cores in terms of the cpu_mask if we haven't
 173          * figured out how many there are yet
 174          */
 175         if (cpu->num_cores == 0)
 176                 return hweight32(cpu_mask());
 177
 178         return cpu->num_cores;
 179 }
 180
 181 /*
 182  * Check if the given core ID is valid
 183  *
 184  * Returns zero if it isn't, 1 if it is.
 185  */
 186 int is_core_valid(unsigned int core)
 187 {
 188         return !!((1 << core) & cpu_mask());
 189 }
 190
 191 int probecpu (void)
 192 {
 193         uint svr;
 194         uint ver;
 195
 196         svr = get_svr();
 197         ver = SVR_SOC_VER(svr);
 198
 199         gd->arch.cpu = identify_cpu(ver);
 200
 201         return 0;
 202 }
 203
 204 /* Once in memory, compute mask & # cores once and save them off */
 205 int fixup_cpu(void)
 206 {
 207         struct cpu_type *cpu = gd->arch.cpu;
 208
 209         if (cpu->num_cores == 0) {
 210                 cpu->mask = cpu_mask();
 211                 cpu->num_cores = cpu_numcores();
 212         }
 213
 214         return 0;
 215 }
 216
 217 /*
 218  * Initializes on-chip ethernet controllers.
 219  * to override, implement board_eth_init()
 220  */
 221 int cpu_eth_init(bd_t *bis)
 222 {
 223 #if defined(CONFIG_ETHER_ON_FCC)
 224         fec_initialize(bis);
 225 #endif
 226
 227 #if defined(CONFIG_UEC_ETH)
 228         uec_standard_init(bis);
 229 #endif
 230
 231 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
 232         tsec_standard_init(bis);
 233 #endif
 234
 235 #ifdef CONFIG_FMAN_ENET
 236         fm_standard_init(bis);
 237 #endif
 238         return 0;
 239 }