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[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / denali_spd_ddr2.c
1 /*
2 * arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core
4 * DDR2 controller, specifically the 440EPx/GRx.
5 *
6 * (C) Copyright 2007-2008
7 * Larry Johnson, lrj@acm.org.
8 *
9 * Based primarily on arch/powerpc/cpu/ppc4xx/4xx_spd_ddr2.c, which is...
10 *
11 * (C) Copyright 2007
12 * Stefan Roese, DENX Software Engineering, sr@denx.de.
13 *
14 * COPYRIGHT AMCC CORPORATION 2004
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 *
34 */
35
36 /* define DEBUG for debugging output (obviously ;-)) */
37 #if 0
38 #define DEBUG
39 #endif
40
41 #include <common.h>
42 #include <command.h>
43 #include <asm/ppc4xx.h>
44 #include <i2c.h>
45 #include <asm/io.h>
46 #include <asm/processor.h>
47 #include <asm/mmu.h>
48 #include <asm/cache.h>
49
50 #if defined(CONFIG_SPD_EEPROM) && \
51 (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
52
53 /*-----------------------------------------------------------------------------+
54 * Defines
55 *-----------------------------------------------------------------------------*/
56 #define MAXDIMMS 2
57 #define MAXRANKS 2
58
59 #define ONE_BILLION 1000000000
60
61 #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
62
63 #define DLL_DQS_DELAY 0x19
64 #define DLL_DQS_BYPASS 0x0B
65 #define DQS_OUT_SHIFT 0x7F
66
67 /*
68 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
69 * region. Right now the cache should still be disabled in U-Boot because of the
70 * EMAC driver, that need it's buffer descriptor to be located in non cached
71 * memory.
72 *
73 * If at some time this restriction doesn't apply anymore, just define
74 * CONFIG_4xx_DCACHE in the board config file and this code should setup
75 * everything correctly.
76 */
77 #if defined(CONFIG_4xx_DCACHE)
78 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
79 #else
80 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
81 #endif
82
83 /*-----------------------------------------------------------------------------+
84 * Prototypes
85 *-----------------------------------------------------------------------------*/
86 extern int denali_wait_for_dlllock(void);
87 extern void denali_core_search_data_eye(void);
88 extern void dcbz_area(u32 start_address, u32 num_bytes);
89
90 /*
91 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
92 */
93 void __spd_ddr_init_hang(void)
94 {
95 hang();
96 }
97 void spd_ddr_init_hang(void)
98 __attribute__ ((weak, alias("__spd_ddr_init_hang")));
99
100 #if defined(DEBUG)
101 static void print_mcsr(void)
102 {
103 printf("MCSR = 0x%08X\n", mfspr(SPRN_MCSR));
104 }
105
106 static void denali_sdram_register_dump(void)
107 {
108 unsigned int sdram_data;
109
110 printf("\n Register Dump:\n");
111 mfsdram(DDR0_00, sdram_data);
112 printf(" DDR0_00 = 0x%08X", sdram_data);
113 mfsdram(DDR0_01, sdram_data);
114 printf(" DDR0_01 = 0x%08X\n", sdram_data);
115 mfsdram(DDR0_02, sdram_data);
116 printf(" DDR0_02 = 0x%08X", sdram_data);
117 mfsdram(DDR0_03, sdram_data);
118 printf(" DDR0_03 = 0x%08X\n", sdram_data);
119 mfsdram(DDR0_04, sdram_data);
120 printf(" DDR0_04 = 0x%08X", sdram_data);
121 mfsdram(DDR0_05, sdram_data);
122 printf(" DDR0_05 = 0x%08X\n", sdram_data);
123 mfsdram(DDR0_06, sdram_data);
124 printf(" DDR0_06 = 0x%08X", sdram_data);
125 mfsdram(DDR0_07, sdram_data);
126 printf(" DDR0_07 = 0x%08X\n", sdram_data);
127 mfsdram(DDR0_08, sdram_data);
128 printf(" DDR0_08 = 0x%08X", sdram_data);
129 mfsdram(DDR0_09, sdram_data);
130 printf(" DDR0_09 = 0x%08X\n", sdram_data);
131 mfsdram(DDR0_10, sdram_data);
132 printf(" DDR0_10 = 0x%08X", sdram_data);
133 mfsdram(DDR0_11, sdram_data);
134 printf(" DDR0_11 = 0x%08X\n", sdram_data);
135 mfsdram(DDR0_12, sdram_data);
136 printf(" DDR0_12 = 0x%08X", sdram_data);
137 mfsdram(DDR0_14, sdram_data);
138 printf(" DDR0_14 = 0x%08X\n", sdram_data);
139 mfsdram(DDR0_17, sdram_data);
140 printf(" DDR0_17 = 0x%08X", sdram_data);
141 mfsdram(DDR0_18, sdram_data);
142 printf(" DDR0_18 = 0x%08X\n", sdram_data);
143 mfsdram(DDR0_19, sdram_data);
144 printf(" DDR0_19 = 0x%08X", sdram_data);
145 mfsdram(DDR0_20, sdram_data);
146 printf(" DDR0_20 = 0x%08X\n", sdram_data);
147 mfsdram(DDR0_21, sdram_data);
148 printf(" DDR0_21 = 0x%08X", sdram_data);
149 mfsdram(DDR0_22, sdram_data);
150 printf(" DDR0_22 = 0x%08X\n", sdram_data);
151 mfsdram(DDR0_23, sdram_data);
152 printf(" DDR0_23 = 0x%08X", sdram_data);
153 mfsdram(DDR0_24, sdram_data);
154 printf(" DDR0_24 = 0x%08X\n", sdram_data);
155 mfsdram(DDR0_25, sdram_data);
156 printf(" DDR0_25 = 0x%08X", sdram_data);
157 mfsdram(DDR0_26, sdram_data);
158 printf(" DDR0_26 = 0x%08X\n", sdram_data);
159 mfsdram(DDR0_27, sdram_data);
160 printf(" DDR0_27 = 0x%08X", sdram_data);
161 mfsdram(DDR0_28, sdram_data);
162 printf(" DDR0_28 = 0x%08X\n", sdram_data);
163 mfsdram(DDR0_31, sdram_data);
164 printf(" DDR0_31 = 0x%08X", sdram_data);
165 mfsdram(DDR0_32, sdram_data);
166 printf(" DDR0_32 = 0x%08X\n", sdram_data);
167 mfsdram(DDR0_33, sdram_data);
168 printf(" DDR0_33 = 0x%08X", sdram_data);
169 mfsdram(DDR0_34, sdram_data);
170 printf(" DDR0_34 = 0x%08X\n", sdram_data);
171 mfsdram(DDR0_35, sdram_data);
172 printf(" DDR0_35 = 0x%08X", sdram_data);
173 mfsdram(DDR0_36, sdram_data);
174 printf(" DDR0_36 = 0x%08X\n", sdram_data);
175 mfsdram(DDR0_37, sdram_data);
176 printf(" DDR0_37 = 0x%08X", sdram_data);
177 mfsdram(DDR0_38, sdram_data);
178 printf(" DDR0_38 = 0x%08X\n", sdram_data);
179 mfsdram(DDR0_39, sdram_data);
180 printf(" DDR0_39 = 0x%08X", sdram_data);
181 mfsdram(DDR0_40, sdram_data);
182 printf(" DDR0_40 = 0x%08X\n", sdram_data);
183 mfsdram(DDR0_41, sdram_data);
184 printf(" DDR0_41 = 0x%08X", sdram_data);
185 mfsdram(DDR0_42, sdram_data);
186 printf(" DDR0_42 = 0x%08X\n", sdram_data);
187 mfsdram(DDR0_43, sdram_data);
188 printf(" DDR0_43 = 0x%08X", sdram_data);
189 mfsdram(DDR0_44, sdram_data);
190 printf(" DDR0_44 = 0x%08X\n", sdram_data);
191 }
192 #else
193 static inline void denali_sdram_register_dump(void)
194 {
195 }
196
197 inline static void print_mcsr(void)
198 {
199 }
200 #endif /* defined(DEBUG) */
201
202 static int is_ecc_enabled(void)
203 {
204 u32 val;
205
206 mfsdram(DDR0_22, val);
207 return 0x3 == DDR0_22_CTRL_RAW_DECODE(val);
208 }
209
210 static unsigned char spd_read(u8 chip, unsigned int addr)
211 {
212 u8 data[2];
213
214 if (0 != i2c_probe(chip) || 0 != i2c_read(chip, addr, 1, data, 1)) {
215 debug("spd_read(0x%02X, 0x%02X) failed\n", chip, addr);
216 return 0;
217 }
218 debug("spd_read(0x%02X, 0x%02X) returned 0x%02X\n",
219 chip, addr, data[0]);
220 return data[0];
221 }
222
223 static unsigned long get_tcyc(unsigned char reg)
224 {
225 /*
226 * Byte 9, et al: Cycle time for CAS Latency=X, is split into two
227 * nibbles: the higher order nibble (bits 4-7) designates the cycle time
228 * to a granularity of 1ns; the value presented by the lower order
229 * nibble (bits 0-3) has a granularity of .1ns and is added to the value
230 * designated by the higher nibble. In addition, four lines of the lower
231 * order nibble are assigned to support +.25, +.33, +.66, and +.75.
232 */
233
234 unsigned char subfield_b = reg & 0x0F;
235
236 switch (subfield_b & 0x0F) {
237 case 0x0:
238 case 0x1:
239 case 0x2:
240 case 0x3:
241 case 0x4:
242 case 0x5:
243 case 0x6:
244 case 0x7:
245 case 0x8:
246 case 0x9:
247 return 1000 * (reg >> 4) + 100 * subfield_b;
248 case 0xA:
249 return 1000 * (reg >> 4) + 250;
250 case 0xB:
251 return 1000 * (reg >> 4) + 333;
252 case 0xC:
253 return 1000 * (reg >> 4) + 667;
254 case 0xD:
255 return 1000 * (reg >> 4) + 750;
256 }
257 return 0;
258 }
259
260 /*------------------------------------------------------------------
261 * Find the installed DIMMs, make sure that the are DDR2, and fill
262 * in the dimm_ranks array. Then dimm_ranks[dimm_num] > 0 iff the
263 * DIMM and dimm_num is present.
264 * Note: Because there are only two chip-select lines, it is assumed
265 * that a board with a single socket can support two ranks on that
266 * socket, while a board with two sockets can support only one rank
267 * on each socket.
268 *-----------------------------------------------------------------*/
269 static void get_spd_info(unsigned long dimm_ranks[],
270 unsigned long *ranks,
271 unsigned char const iic0_dimm_addr[],
272 unsigned long num_dimm_banks)
273 {
274 unsigned long dimm_num;
275 unsigned long dimm_found = false;
276 unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1;
277 unsigned char num_of_bytes;
278 unsigned char total_size;
279
280 *ranks = 0;
281 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
282 num_of_bytes = 0;
283 total_size = 0;
284
285 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
286 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
287 if ((num_of_bytes != 0) && (total_size != 0)) {
288 unsigned char const dimm_type =
289 spd_read(iic0_dimm_addr[dimm_num], 2);
290
291 unsigned long ranks_on_dimm =
292 (spd_read(iic0_dimm_addr[dimm_num], 5) & 0x07) + 1;
293
294 if (8 != dimm_type) {
295 switch (dimm_type) {
296 case 1:
297 printf("ERROR: Standard Fast Page Mode "
298 "DRAM DIMM");
299 break;
300 case 2:
301 printf("ERROR: EDO DIMM");
302 break;
303 case 3:
304 printf("ERROR: Pipelined Nibble DIMM");
305 break;
306 case 4:
307 printf("ERROR: SDRAM DIMM");
308 break;
309 case 5:
310 printf("ERROR: Multiplexed ROM DIMM");
311 break;
312 case 6:
313 printf("ERROR: SGRAM DIMM");
314 break;
315 case 7:
316 printf("ERROR: DDR1 DIMM");
317 break;
318 default:
319 printf("ERROR: Unknown DIMM (type %d)",
320 (unsigned int)dimm_type);
321 break;
322 }
323 printf(" detected in slot %lu.\n", dimm_num);
324 printf("Only DDR2 SDRAM DIMMs are supported."
325 "\n");
326 printf("Replace the module with a DDR2 DIMM."
327 "\n\n");
328 spd_ddr_init_hang();
329 }
330 dimm_found = true;
331 debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM"
332 "\n", dimm_num, ranks_on_dimm);
333 if (ranks_on_dimm > max_ranks_per_dimm) {
334 printf("WARNING: DRAM DIMM in slot %lu has %lu "
335 "ranks.\n", dimm_num, ranks_on_dimm);
336 if (1 == max_ranks_per_dimm) {
337 printf("Only one rank will be used.\n");
338 } else {
339 printf
340 ("Only two ranks will be used.\n");
341 }
342 ranks_on_dimm = max_ranks_per_dimm;
343 }
344 dimm_ranks[dimm_num] = ranks_on_dimm;
345 *ranks += ranks_on_dimm;
346 } else {
347 dimm_ranks[dimm_num] = 0;
348 debug("DIMM slot %lu: Not populated\n", dimm_num);
349 }
350 }
351 if (dimm_found == false) {
352 printf("ERROR: No memory installed.\n");
353 printf("Install at least one DDR2 DIMM.\n\n");
354 spd_ddr_init_hang();
355 }
356 debug("Total number of ranks = %ld\n", *ranks);
357 }
358
359 /*------------------------------------------------------------------
360 * For the memory DIMMs installed, this routine verifies that
361 * frequency previously calculated is supported.
362 *-----------------------------------------------------------------*/
363 static void check_frequency(unsigned long *dimm_ranks,
364 unsigned char const iic0_dimm_addr[],
365 unsigned long num_dimm_banks,
366 unsigned long sdram_freq)
367 {
368 unsigned long dimm_num;
369 unsigned long cycle_time;
370 unsigned long calc_cycle_time;
371
372 /*
373 * calc_cycle_time is calculated from DDR frequency set by board/chip
374 * and is expressed in picoseconds to match the way DIMM cycle time is
375 * calculated below.
376 */
377 calc_cycle_time = MULDIV64(ONE_BILLION, 1000, sdram_freq);
378
379 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
380 if (dimm_ranks[dimm_num]) {
381 cycle_time =
382 get_tcyc(spd_read(iic0_dimm_addr[dimm_num], 9));
383 debug("cycle_time=%ld ps\n", cycle_time);
384
385 if (cycle_time > (calc_cycle_time + 10)) {
386 /*
387 * the provided sdram cycle_time is too small
388 * for the available DIMM cycle_time. The
389 * additionnal 10ps is here to accept a small
390 * incertainty.
391 */
392 printf
393 ("ERROR: DRAM DIMM detected with cycle_time %d ps in "
394 "slot %d \n while calculated cycle time is %d ps.\n",
395 (unsigned int)cycle_time,
396 (unsigned int)dimm_num,
397 (unsigned int)calc_cycle_time);
398 printf
399 ("Replace the DIMM, or change DDR frequency via "
400 "strapping bits.\n\n");
401 spd_ddr_init_hang();
402 }
403 }
404 }
405 }
406
407 /*------------------------------------------------------------------
408 * This routine gets size information for the installed memory
409 * DIMMs.
410 *-----------------------------------------------------------------*/
411 static void get_dimm_size(unsigned long dimm_ranks[],
412 unsigned char const iic0_dimm_addr[],
413 unsigned long num_dimm_banks,
414 unsigned long *const rows,
415 unsigned long *const banks,
416 unsigned long *const cols, unsigned long *const width)
417 {
418 unsigned long dimm_num;
419
420 *rows = 0;
421 *banks = 0;
422 *cols = 0;
423 *width = 0;
424 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
425 if (dimm_ranks[dimm_num]) {
426 unsigned long t;
427
428 /* Rows */
429 t = spd_read(iic0_dimm_addr[dimm_num], 3);
430 if (0 == *rows) {
431 *rows = t;
432 } else if (t != *rows) {
433 printf("ERROR: DRAM DIMM modules do not all "
434 "have the same number of rows.\n\n");
435 spd_ddr_init_hang();
436 }
437 /* Banks */
438 t = spd_read(iic0_dimm_addr[dimm_num], 17);
439 if (0 == *banks) {
440 *banks = t;
441 } else if (t != *banks) {
442 printf("ERROR: DRAM DIMM modules do not all "
443 "have the same number of banks.\n\n");
444 spd_ddr_init_hang();
445 }
446 /* Columns */
447 t = spd_read(iic0_dimm_addr[dimm_num], 4);
448 if (0 == *cols) {
449 *cols = t;
450 } else if (t != *cols) {
451 printf("ERROR: DRAM DIMM modules do not all "
452 "have the same number of columns.\n\n");
453 spd_ddr_init_hang();
454 }
455 /* Data width */
456 t = spd_read(iic0_dimm_addr[dimm_num], 6);
457 if (0 == *width) {
458 *width = t;
459 } else if (t != *width) {
460 printf("ERROR: DRAM DIMM modules do not all "
461 "have the same data width.\n\n");
462 spd_ddr_init_hang();
463 }
464 }
465 }
466 debug("Number of rows = %ld\n", *rows);
467 debug("Number of columns = %ld\n", *cols);
468 debug("Number of banks = %ld\n", *banks);
469 debug("Data width = %ld\n", *width);
470 if (*rows > 14) {
471 printf("ERROR: DRAM DIMM modules have %lu address rows.\n",
472 *rows);
473 printf("Only modules with 14 or fewer rows are supported.\n\n");
474 spd_ddr_init_hang();
475 }
476 if (4 != *banks && 8 != *banks) {
477 printf("ERROR: DRAM DIMM modules have %lu banks.\n", *banks);
478 printf("Only modules with 4 or 8 banks are supported.\n\n");
479 spd_ddr_init_hang();
480 }
481 if (*cols > 12) {
482 printf("ERROR: DRAM DIMM modules have %lu address columns.\n",
483 *cols);
484 printf("Only modules with 12 or fewer columns are "
485 "supported.\n\n");
486 spd_ddr_init_hang();
487 }
488 if (32 != *width && 40 != *width && 64 != *width && 72 != *width) {
489 printf("ERROR: DRAM DIMM modules have a width of %lu bit.\n",
490 *width);
491 printf("Only modules with widths of 32, 40, 64, and 72 bits "
492 "are supported.\n\n");
493 spd_ddr_init_hang();
494 }
495 }
496
497 /*------------------------------------------------------------------
498 * Only 1.8V modules are supported. This routine verifies this.
499 *-----------------------------------------------------------------*/
500 static void check_voltage_type(unsigned long dimm_ranks[],
501 unsigned char const iic0_dimm_addr[],
502 unsigned long num_dimm_banks)
503 {
504 unsigned long dimm_num;
505 unsigned long voltage_type;
506
507 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
508 if (dimm_ranks[dimm_num]) {
509 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
510 if (0x05 != voltage_type) { /* 1.8V for DDR2 */
511 printf("ERROR: Slot %lu provides 1.8V for DDR2 "
512 "DIMMs.\n", dimm_num);
513 switch (voltage_type) {
514 case 0x00:
515 printf("This DIMM is 5.0 Volt/TTL.\n");
516 break;
517 case 0x01:
518 printf("This DIMM is LVTTL.\n");
519 break;
520 case 0x02:
521 printf("This DIMM is 1.5 Volt.\n");
522 break;
523 case 0x03:
524 printf("This DIMM is 3.3 Volt/TTL.\n");
525 break;
526 case 0x04:
527 printf("This DIMM is 2.5 Volt.\n");
528 break;
529 default:
530 printf("This DIMM is an unknown "
531 "voltage.\n");
532 break;
533 }
534 printf("Replace it with a 1.8V DDR2 DIMM.\n\n");
535 spd_ddr_init_hang();
536 }
537 }
538 }
539 }
540
541 static void program_ddr0_03(unsigned long dimm_ranks[],
542 unsigned char const iic0_dimm_addr[],
543 unsigned long num_dimm_banks,
544 unsigned long sdram_freq,
545 unsigned long rows, unsigned long *cas_latency)
546 {
547 unsigned long dimm_num;
548 unsigned long cas_index;
549 unsigned long cycle_2_0_clk;
550 unsigned long cycle_3_0_clk;
551 unsigned long cycle_4_0_clk;
552 unsigned long cycle_5_0_clk;
553 unsigned long max_2_0_tcyc_ps = 100;
554 unsigned long max_3_0_tcyc_ps = 100;
555 unsigned long max_4_0_tcyc_ps = 100;
556 unsigned long max_5_0_tcyc_ps = 100;
557 unsigned char cas_available = 0x3C; /* value for DDR2 */
558 u32 ddr0_03 = DDR0_03_BSTLEN_ENCODE(0x2) | DDR0_03_INITAREF_ENCODE(0x2);
559 unsigned int const tcyc_addr[3] = { 9, 23, 25 };
560
561 /*------------------------------------------------------------------
562 * Get the board configuration info.
563 *-----------------------------------------------------------------*/
564 debug("sdram_freq = %ld\n", sdram_freq);
565
566 /*------------------------------------------------------------------
567 * Handle the timing. We need to find the worst case timing of all
568 * the dimm modules installed.
569 *-----------------------------------------------------------------*/
570 /* loop through all the DIMM slots on the board */
571 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
572 /* If a dimm is installed in a particular slot ... */
573 if (dimm_ranks[dimm_num]) {
574 unsigned char const cas_bit =
575 spd_read(iic0_dimm_addr[dimm_num], 18);
576 unsigned char cas_mask;
577
578 cas_available &= cas_bit;
579 for (cas_mask = 0x80; cas_mask; cas_mask >>= 1) {
580 if (cas_bit & cas_mask)
581 break;
582 }
583 debug("cas_bit (SPD byte 18) = %02X, cas_mask = %02X\n",
584 cas_bit, cas_mask);
585
586 for (cas_index = 0; cas_index < 3;
587 cas_mask >>= 1, cas_index++) {
588 unsigned long cycle_time_ps;
589
590 if (!(cas_available & cas_mask)) {
591 continue;
592 }
593 cycle_time_ps =
594 get_tcyc(spd_read(iic0_dimm_addr[dimm_num],
595 tcyc_addr[cas_index]));
596
597 debug("cas_index = %ld: cycle_time_ps = %ld\n",
598 cas_index, cycle_time_ps);
599 /*
600 * DDR2 devices use the following bitmask for CAS latency:
601 * Bit 7 6 5 4 3 2 1 0
602 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
603 */
604 switch (cas_mask) {
605 case 0x20:
606 max_5_0_tcyc_ps =
607 max(max_5_0_tcyc_ps, cycle_time_ps);
608 break;
609 case 0x10:
610 max_4_0_tcyc_ps =
611 max(max_4_0_tcyc_ps, cycle_time_ps);
612 break;
613 case 0x08:
614 max_3_0_tcyc_ps =
615 max(max_3_0_tcyc_ps, cycle_time_ps);
616 break;
617 case 0x04:
618 max_2_0_tcyc_ps =
619 max(max_2_0_tcyc_ps, cycle_time_ps);
620 break;
621 }
622 }
623 }
624 }
625 debug("cas_available (bit map) = 0x%02X\n", cas_available);
626
627 /*------------------------------------------------------------------
628 * Set the SDRAM mode, SDRAM_MMODE
629 *-----------------------------------------------------------------*/
630
631 /* add 10 here because of rounding problems */
632 cycle_2_0_clk = MULDIV64(ONE_BILLION, 1000, max_2_0_tcyc_ps) + 10;
633 cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10;
634 cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10;
635 cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10;
636 debug("cycle_2_0_clk = %ld\n", cycle_2_0_clk);
637 debug("cycle_3_0_clk = %ld\n", cycle_3_0_clk);
638 debug("cycle_4_0_clk = %ld\n", cycle_4_0_clk);
639 debug("cycle_5_0_clk = %ld\n", cycle_5_0_clk);
640
641 if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) {
642 *cas_latency = 2;
643 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x2) |
644 DDR0_03_CASLAT_LIN_ENCODE(0x4);
645 } else if ((cas_available & 0x08) && (sdram_freq <= cycle_3_0_clk)) {
646 *cas_latency = 3;
647 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x3) |
648 DDR0_03_CASLAT_LIN_ENCODE(0x6);
649 } else if ((cas_available & 0x10) && (sdram_freq <= cycle_4_0_clk)) {
650 *cas_latency = 4;
651 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x4) |
652 DDR0_03_CASLAT_LIN_ENCODE(0x8);
653 } else if ((cas_available & 0x20) && (sdram_freq <= cycle_5_0_clk)) {
654 *cas_latency = 5;
655 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x5) |
656 DDR0_03_CASLAT_LIN_ENCODE(0xA);
657 } else {
658 printf("ERROR: Cannot find a supported CAS latency with the "
659 "installed DIMMs.\n");
660 printf("Only DDR2 DIMMs with CAS latencies of 2.0, 3.0, 4.0, "
661 "and 5.0 are supported.\n");
662 printf("Make sure the PLB speed is within the supported range "
663 "of the DIMMs.\n");
664 printf("sdram_freq=%ld cycle2=%ld cycle3=%ld cycle4=%ld "
665 "cycle5=%ld\n\n", sdram_freq, cycle_2_0_clk,
666 cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
667 spd_ddr_init_hang();
668 }
669 debug("CAS latency = %ld\n", *cas_latency);
670 mtsdram(DDR0_03, ddr0_03);
671 }
672
673 static void program_ddr0_04(unsigned long dimm_ranks[],
674 unsigned char const iic0_dimm_addr[],
675 unsigned long num_dimm_banks,
676 unsigned long sdram_freq)
677 {
678 unsigned long dimm_num;
679 unsigned long t_rc_ps = 0;
680 unsigned long t_rrd_ps = 0;
681 unsigned long t_rtp_ps = 0;
682 unsigned long t_rc_clk;
683 unsigned long t_rrd_clk;
684 unsigned long t_rtp_clk;
685
686 /*------------------------------------------------------------------
687 * Handle the timing. We need to find the worst case timing of all
688 * the dimm modules installed.
689 *-----------------------------------------------------------------*/
690 /* loop through all the DIMM slots on the board */
691 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
692 /* If a dimm is installed in a particular slot ... */
693 if (dimm_ranks[dimm_num]) {
694 unsigned long ps;
695
696 /* tRC */
697 ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 41);
698 switch (spd_read(iic0_dimm_addr[dimm_num], 40) >> 4) {
699 case 0x1:
700 ps += 250;
701 break;
702 case 0x2:
703 ps += 333;
704 break;
705 case 0x3:
706 ps += 500;
707 break;
708 case 0x4:
709 ps += 667;
710 break;
711 case 0x5:
712 ps += 750;
713 break;
714 }
715 t_rc_ps = max(t_rc_ps, ps);
716 /* tRRD */
717 ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 28);
718 t_rrd_ps = max(t_rrd_ps, ps);
719 /* tRTP */
720 ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 38);
721 t_rtp_ps = max(t_rtp_ps, ps);
722 }
723 }
724 debug("t_rc_ps = %ld\n", t_rc_ps);
725 t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000;
726 debug("t_rrd_ps = %ld\n", t_rrd_ps);
727 t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000;
728 debug("t_rtp_ps = %ld\n", t_rtp_ps);
729 t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000;
730 mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) |
731 DDR0_04_TRRD_ENCODE(t_rrd_clk) |
732 DDR0_04_TRTP_ENCODE(t_rtp_clk));
733 }
734
735 static void program_ddr0_05(unsigned long dimm_ranks[],
736 unsigned char const iic0_dimm_addr[],
737 unsigned long num_dimm_banks,
738 unsigned long sdram_freq)
739 {
740 unsigned long dimm_num;
741 unsigned long t_rp_ps = 0;
742 unsigned long t_ras_ps = 0;
743 unsigned long t_rp_clk;
744 unsigned long t_ras_clk;
745 u32 ddr0_05 = DDR0_05_TMRD_ENCODE(0x2) | DDR0_05_TEMRS_ENCODE(0x2);
746
747 /*------------------------------------------------------------------
748 * Handle the timing. We need to find the worst case timing of all
749 * the dimm modules installed.
750 *-----------------------------------------------------------------*/
751 /* loop through all the DIMM slots on the board */
752 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
753 /* If a dimm is installed in a particular slot ... */
754 if (dimm_ranks[dimm_num]) {
755 unsigned long ps;
756
757 /* tRP */
758 ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 27);
759 t_rp_ps = max(t_rp_ps, ps);
760 /* tRAS */
761 ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 30);
762 t_ras_ps = max(t_ras_ps, ps);
763 }
764 }
765 debug("t_rp_ps = %ld\n", t_rp_ps);
766 t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000;
767 debug("t_ras_ps = %ld\n", t_ras_ps);
768 t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000;
769 mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) |
770 DDR0_05_TRAS_MIN_ENCODE(t_ras_clk));
771 }
772
773 static void program_ddr0_06(unsigned long dimm_ranks[],
774 unsigned char const iic0_dimm_addr[],
775 unsigned long num_dimm_banks,
776 unsigned long sdram_freq)
777 {
778 unsigned long dimm_num;
779 unsigned char spd_40;
780 unsigned long t_wtr_ps = 0;
781 unsigned long t_rfc_ps = 0;
782 unsigned long t_wtr_clk;
783 unsigned long t_rfc_clk;
784 u32 ddr0_06 =
785 DDR0_06_WRITEINTERP_ENCODE(0x1) | DDR0_06_TDLL_ENCODE(200);
786
787 /*------------------------------------------------------------------
788 * Handle the timing. We need to find the worst case timing of all
789 * the dimm modules installed.
790 *-----------------------------------------------------------------*/
791 /* loop through all the DIMM slots on the board */
792 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
793 /* If a dimm is installed in a particular slot ... */
794 if (dimm_ranks[dimm_num]) {
795 unsigned long ps;
796
797 /* tWTR */
798 ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 37);
799 t_wtr_ps = max(t_wtr_ps, ps);
800 /* tRFC */
801 ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 42);
802 spd_40 = spd_read(iic0_dimm_addr[dimm_num], 40);
803 ps += 256000 * (spd_40 & 0x01);
804 switch ((spd_40 & 0x0E) >> 1) {
805 case 0x1:
806 ps += 250;
807 break;
808 case 0x2:
809 ps += 333;
810 break;
811 case 0x3:
812 ps += 500;
813 break;
814 case 0x4:
815 ps += 667;
816 break;
817 case 0x5:
818 ps += 750;
819 break;
820 }
821 t_rfc_ps = max(t_rfc_ps, ps);
822 }
823 }
824 debug("t_wtr_ps = %ld\n", t_wtr_ps);
825 t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000;
826 debug("t_rfc_ps = %ld\n", t_rfc_ps);
827 t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000;
828 mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) |
829 DDR0_06_TRFC_ENCODE(t_rfc_clk));
830 }
831
832 static void program_ddr0_10(unsigned long dimm_ranks[], unsigned long ranks)
833 {
834 unsigned long csmap;
835
836 if (2 == ranks) {
837 /* Both chip selects in use */
838 csmap = 0x03;
839 } else {
840 /* One chip select in use */
841 csmap = (1 == dimm_ranks[0]) ? 0x1 : 0x2;
842 }
843 mtsdram(DDR0_10, DDR0_10_WRITE_MODEREG_ENCODE(0x0) |
844 DDR0_10_CS_MAP_ENCODE(csmap) |
845 DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(0));
846 }
847
848 static void program_ddr0_11(unsigned long sdram_freq)
849 {
850 unsigned long const t_xsnr_ps = 200000; /* 200 ns */
851 unsigned long t_xsnr_clk;
852
853 debug("t_xsnr_ps = %ld\n", t_xsnr_ps);
854 t_xsnr_clk =
855 (MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000;
856 mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) |
857 DDR0_11_TXSNR_ENCODE(t_xsnr_clk) | DDR0_11_TXSR_ENCODE(200));
858 }
859
860 static void program_ddr0_22(unsigned long dimm_ranks[],
861 unsigned char const iic0_dimm_addr[],
862 unsigned long num_dimm_banks, unsigned long width)
863 {
864 #if defined(CONFIG_DDR_ECC)
865 unsigned long dimm_num;
866 unsigned long ecc_available = width >= 64;
867 u32 ddr0_22 = DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
868 DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
869 DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS);
870
871 /* loop through all the DIMM slots on the board */
872 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
873 /* If a dimm is installed in a particular slot ... */
874 if (dimm_ranks[dimm_num]) {
875 /* Check for ECC */
876 if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) &
877 0x02)) {
878 ecc_available = false;
879 }
880 }
881 }
882 if (ecc_available) {
883 debug("ECC found on all DIMMs present\n");
884 mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x3));
885 } else {
886 debug("ECC not found on some or all DIMMs present\n");
887 mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x0));
888 }
889 #else
890 mtsdram(DDR0_22, DDR0_22_CTRL_RAW_ENCODE(0x0) |
891 DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
892 DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
893 DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS));
894 #endif /* defined(CONFIG_DDR_ECC) */
895 }
896
897 static void program_ddr0_24(unsigned long ranks)
898 {
899 u32 ddr0_24 = DDR0_24_RTT_PAD_TERMINATION_ENCODE(0x1) | /* 75 ohm */
900 DDR0_24_ODT_RD_MAP_CS1_ENCODE(0x0);
901
902 if (2 == ranks) {
903 /* Both chip selects in use */
904 ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x1) |
905 DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x2);
906 } else {
907 /* One chip select in use */
908 /* One of the two fields added to ddr0_24 is a "don't care" */
909 ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x2) |
910 DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x1);
911 }
912 mtsdram(DDR0_24, ddr0_24);
913 }
914
915 static void program_ddr0_26(unsigned long sdram_freq)
916 {
917 unsigned long const t_ref_ps = 7800000; /* 7.8 us. refresh */
918 /* TODO: check definition of tRAS_MAX */
919 unsigned long const t_ras_max_ps = 9 * t_ref_ps;
920 unsigned long t_ras_max_clk;
921 unsigned long t_ref_clk;
922
923 /* Round down t_ras_max_clk and t_ref_clk */
924 debug("t_ras_max_ps = %ld\n", t_ras_max_ps);
925 t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000;
926 debug("t_ref_ps = %ld\n", t_ref_ps);
927 t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000;
928 mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) |
929 DDR0_26_TREF_ENCODE(t_ref_clk));
930 }
931
932 static void program_ddr0_27(unsigned long sdram_freq)
933 {
934 unsigned long const t_init_ps = 200000000; /* 200 us. init */
935 unsigned long t_init_clk;
936
937 debug("t_init_ps = %ld\n", t_init_ps);
938 t_init_clk =
939 (MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000;
940 mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) |
941 DDR0_27_TINIT_ENCODE(t_init_clk));
942 }
943
944 static void program_ddr0_43(unsigned long dimm_ranks[],
945 unsigned char const iic0_dimm_addr[],
946 unsigned long num_dimm_banks,
947 unsigned long sdram_freq,
948 unsigned long cols, unsigned long banks)
949 {
950 unsigned long dimm_num;
951 unsigned long t_wr_ps = 0;
952 unsigned long t_wr_clk;
953 u32 ddr0_43 = DDR0_43_APREBIT_ENCODE(10) |
954 DDR0_43_COLUMN_SIZE_ENCODE(12 - cols) |
955 DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0);
956
957 /*------------------------------------------------------------------
958 * Handle the timing. We need to find the worst case timing of all
959 * the dimm modules installed.
960 *-----------------------------------------------------------------*/
961 /* loop through all the DIMM slots on the board */
962 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
963 /* If a dimm is installed in a particular slot ... */
964 if (dimm_ranks[dimm_num]) {
965 unsigned long ps;
966
967 ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 36);
968 t_wr_ps = max(t_wr_ps, ps);
969 }
970 }
971 debug("t_wr_ps = %ld\n", t_wr_ps);
972 t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000;
973 mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk));
974 }
975
976 static void program_ddr0_44(unsigned long dimm_ranks[],
977 unsigned char const iic0_dimm_addr[],
978 unsigned long num_dimm_banks,
979 unsigned long sdram_freq)
980 {
981 unsigned long dimm_num;
982 unsigned long t_rcd_ps = 0;
983 unsigned long t_rcd_clk;
984
985 /*------------------------------------------------------------------
986 * Handle the timing. We need to find the worst case timing of all
987 * the dimm modules installed.
988 *-----------------------------------------------------------------*/
989 /* loop through all the DIMM slots on the board */
990 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
991 /* If a dimm is installed in a particular slot ... */
992 if (dimm_ranks[dimm_num]) {
993 unsigned long ps;
994
995 ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 29);
996 t_rcd_ps = max(t_rcd_ps, ps);
997 }
998 }
999 debug("t_rcd_ps = %ld\n", t_rcd_ps);
1000 t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000;
1001 mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk));
1002 }
1003
1004 /*-----------------------------------------------------------------------------+
1005 * initdram. Initializes the 440EPx/GPx DDR SDRAM controller.
1006 * Note: This routine runs from flash with a stack set up in the chip's
1007 * sram space. It is important that the routine does not require .sbss, .bss or
1008 * .data sections. It also cannot call routines that require these sections.
1009 *-----------------------------------------------------------------------------*/
1010 /*-----------------------------------------------------------------------------
1011 * Function: initdram
1012 * Description: Configures SDRAM memory banks for DDR operation.
1013 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
1014 * via the IIC bus and then configures the DDR SDRAM memory
1015 * banks appropriately. If Auto Memory Configuration is
1016 * not used, it is assumed that no DIMM is plugged
1017 *-----------------------------------------------------------------------------*/
1018 phys_size_t initdram(int board_type)
1019 {
1020 unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
1021 unsigned long dimm_ranks[MAXDIMMS];
1022 unsigned long ranks;
1023 unsigned long rows;
1024 unsigned long banks;
1025 unsigned long cols;
1026 unsigned long width;
1027 unsigned long const sdram_freq = get_bus_freq(0);
1028 unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr); /* on board dimm banks */
1029 unsigned long cas_latency = 0; /* to quiet initialization warning */
1030 unsigned long dram_size;
1031
1032 debug("\nEntering initdram()\n");
1033
1034 /*------------------------------------------------------------------
1035 * Stop the DDR-SDRAM controller.
1036 *-----------------------------------------------------------------*/
1037 mtsdram(DDR0_02, DDR0_02_START_ENCODE(0));
1038
1039 /*
1040 * Make sure I2C controller is initialized
1041 * before continuing.
1042 */
1043 /* switch to correct I2C bus */
1044 I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
1045 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
1046
1047 /*------------------------------------------------------------------
1048 * Clear out the serial presence detect buffers.
1049 * Perform IIC reads from the dimm. Fill in the spds.
1050 * Check to see if the dimm slots are populated
1051 *-----------------------------------------------------------------*/
1052 get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks);
1053
1054 /*------------------------------------------------------------------
1055 * Check the frequency supported for the dimms plugged.
1056 *-----------------------------------------------------------------*/
1057 check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1058
1059 /*------------------------------------------------------------------
1060 * Check and get size information.
1061 *-----------------------------------------------------------------*/
1062 get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks,
1063 &cols, &width);
1064
1065 /*------------------------------------------------------------------
1066 * Check the voltage type for the dimms plugged.
1067 *-----------------------------------------------------------------*/
1068 check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks);
1069
1070 /*------------------------------------------------------------------
1071 * Program registers for SDRAM controller.
1072 *-----------------------------------------------------------------*/
1073 mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) |
1074 DDR0_00_DLL_START_POINT_DECODE(0x0A));
1075
1076 mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) |
1077 DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) |
1078 DDR0_01_INT_MASK_ENCODE(0xFF));
1079
1080 program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
1081 rows, &cas_latency);
1082
1083 program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1084
1085 program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1086
1087 program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1088
1089 /*
1090 * TODO: tFAW not found in SPD. Value of 13 taken from Sequoia
1091 * board SDRAM, but may be overly conservative.
1092 */
1093 mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
1094 DDR0_07_TFAW_ENCODE(13) |
1095 DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
1096 DDR0_07_AREFRESH_ENCODE(0));
1097
1098 mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) |
1099 DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) |
1100 DDR0_08_DDRII_ENCODE(1));
1101
1102 mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) |
1103 DDR0_09_RTT_0_ENCODE(0x1) |
1104 DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) |
1105 DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20));
1106
1107 program_ddr0_10(dimm_ranks, ranks);
1108
1109 program_ddr0_11(sdram_freq);
1110
1111 mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3));
1112
1113 mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) |
1114 DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) |
1115 DDR0_14_REG_DIMM_ENABLE_ENCODE(0));
1116
1117 mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY));
1118
1119 mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) |
1120 DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) |
1121 DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) |
1122 DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY));
1123
1124 mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) |
1125 DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) |
1126 DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) |
1127 DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY));
1128
1129 mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) |
1130 DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) |
1131 DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) |
1132 DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS));
1133
1134 mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) |
1135 DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) |
1136 DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) |
1137 DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS));
1138
1139 program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width);
1140
1141 mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) |
1142 DDR0_23_FWC_ENCODE(0));
1143
1144 program_ddr0_24(ranks);
1145
1146 program_ddr0_26(sdram_freq);
1147
1148 program_ddr0_27(sdram_freq);
1149
1150 mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) |
1151 DDR0_28_EMRS2_DATA_ENCODE(0x0000));
1152
1153 mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000));
1154
1155 mtsdram(DDR0_42, DDR0_42_ADDR_PINS_ENCODE(14 - rows) |
1156 DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency));
1157
1158 program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
1159 cols, banks);
1160
1161 program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1162
1163 denali_sdram_register_dump();
1164
1165 dram_size = (width >= 64) ? 8 : 4;
1166 dram_size *= 1 << cols;
1167 dram_size *= banks;
1168 dram_size *= 1 << rows;
1169 dram_size *= ranks;
1170 debug("dram_size = %lu\n", dram_size);
1171
1172 /* Start the SDRAM controler */
1173 mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
1174 denali_wait_for_dlllock();
1175
1176 #if defined(CONFIG_DDR_DATA_EYE)
1177 /*
1178 * Map the first 1 MiB of memory in the TLB, and perform the data eye
1179 * search.
1180 */
1181 program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
1182 denali_core_search_data_eye();
1183 denali_sdram_register_dump();
1184 remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE);
1185 #endif
1186
1187 #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
1188 program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0);
1189 sync();
1190 /* Zero the memory */
1191 debug("Zeroing SDRAM...");
1192 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
1193 dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE);
1194 #else
1195 #error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file
1196 #endif
1197 /* Write modified dcache lines back to memory */
1198 clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE);
1199 debug("Completed\n");
1200 sync();
1201 remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size);
1202
1203 #if defined(CONFIG_DDR_ECC)
1204 /*
1205 * If ECC is enabled, clear and enable interrupts
1206 */
1207 if (is_ecc_enabled()) {
1208 u32 val;
1209
1210 sync();
1211 /* Clear error status */
1212 mfsdram(DDR0_00, val);
1213 mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
1214 /* Set 'int_mask' parameter to functionnal value */
1215 mfsdram(DDR0_01, val);
1216 mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) |
1217 DDR0_01_INT_MASK_ALL_OFF);
1218 #if defined(CONFIG_DDR_DATA_EYE)
1219 /*
1220 * Running denali_core_search_data_eye() when ECC is enabled
1221 * causes non-ECC machine checks. This clears them.
1222 */
1223 print_mcsr();
1224 mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
1225 print_mcsr();
1226 #endif
1227 sync();
1228 }
1229 #endif /* defined(CONFIG_DDR_ECC) */
1230 #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
1231
1232 program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
1233 return dram_size;
1234 }
1235
1236 void board_add_ram_info(int use_default)
1237 {
1238 u32 val;
1239
1240 printf(" (ECC");
1241 if (!is_ecc_enabled()) {
1242 printf(" not");
1243 }
1244 printf(" enabled, %ld MHz", (2 * get_bus_freq(0)) / 1000000);
1245
1246 mfsdram(DDR0_03, val);
1247 printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1);
1248 }
1249 #endif /* CONFIG_SPD_EEPROM */
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