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powerpc: T1042: Remove macro CONFIG_PPC_T1042
[people/ms/u-boot.git] / arch / powerpc / include / asm / immap_85xx.h
1 /*
2 * MPC85xx Internal Memory Map
3 *
4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
5 *
6 * Copyright(c) 2002,2003 Motorola Inc.
7 * Xianghua Xiao (x.xiao@motorola.com)
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 #ifndef __IMMAP_85xx__
13 #define __IMMAP_85xx__
14
15 #include <asm/types.h>
16 #include <asm/fsl_dma.h>
17 #include <asm/fsl_i2c.h>
18 #include <fsl_ifc.h>
19 #include <fsl_sec.h>
20 #include <fsl_sfp.h>
21 #include <asm/fsl_lbc.h>
22 #include <fsl_fman.h>
23 #include <fsl_immap.h>
24
25 typedef struct ccsr_local {
26 u32 ccsrbarh; /* CCSR Base Addr High */
27 u32 ccsrbarl; /* CCSR Base Addr Low */
28 u32 ccsrar; /* CCSR Attr */
29 #define CCSRAR_C 0x80000000 /* Commit */
30 u8 res1[4];
31 u32 altcbarh; /* Alternate Configuration Base Addr High */
32 u32 altcbarl; /* Alternate Configuration Base Addr Low */
33 u32 altcar; /* Alternate Configuration Attr */
34 u8 res2[4];
35 u32 bstrh; /* Boot space translation high */
36 u32 bstrl; /* Boot space translation Low */
37 u32 bstrar; /* Boot space translation attributes */
38 u8 res3[0xbd4];
39 struct {
40 u32 lawbarh; /* LAWn base addr high */
41 u32 lawbarl; /* LAWn base addr low */
42 u32 lawar; /* LAWn attributes */
43 u8 res4[4];
44 } law[32];
45 u8 res35[0x204];
46 } ccsr_local_t;
47
48 /* Local-Access Registers & ECM Registers */
49 typedef struct ccsr_local_ecm {
50 u32 ccsrbar; /* CCSR Base Addr */
51 u8 res1[4];
52 u32 altcbar; /* Alternate Configuration Base Addr */
53 u8 res2[4];
54 u32 altcar; /* Alternate Configuration Attr */
55 u8 res3[12];
56 u32 bptr; /* Boot Page Translation */
57 u8 res4[3044];
58 u32 lawbar0; /* Local Access Window 0 Base Addr */
59 u8 res5[4];
60 u32 lawar0; /* Local Access Window 0 Attrs */
61 u8 res6[20];
62 u32 lawbar1; /* Local Access Window 1 Base Addr */
63 u8 res7[4];
64 u32 lawar1; /* Local Access Window 1 Attrs */
65 u8 res8[20];
66 u32 lawbar2; /* Local Access Window 2 Base Addr */
67 u8 res9[4];
68 u32 lawar2; /* Local Access Window 2 Attrs */
69 u8 res10[20];
70 u32 lawbar3; /* Local Access Window 3 Base Addr */
71 u8 res11[4];
72 u32 lawar3; /* Local Access Window 3 Attrs */
73 u8 res12[20];
74 u32 lawbar4; /* Local Access Window 4 Base Addr */
75 u8 res13[4];
76 u32 lawar4; /* Local Access Window 4 Attrs */
77 u8 res14[20];
78 u32 lawbar5; /* Local Access Window 5 Base Addr */
79 u8 res15[4];
80 u32 lawar5; /* Local Access Window 5 Attrs */
81 u8 res16[20];
82 u32 lawbar6; /* Local Access Window 6 Base Addr */
83 u8 res17[4];
84 u32 lawar6; /* Local Access Window 6 Attrs */
85 u8 res18[20];
86 u32 lawbar7; /* Local Access Window 7 Base Addr */
87 u8 res19[4];
88 u32 lawar7; /* Local Access Window 7 Attrs */
89 u8 res19_8a[20];
90 u32 lawbar8; /* Local Access Window 8 Base Addr */
91 u8 res19_8b[4];
92 u32 lawar8; /* Local Access Window 8 Attrs */
93 u8 res19_9a[20];
94 u32 lawbar9; /* Local Access Window 9 Base Addr */
95 u8 res19_9b[4];
96 u32 lawar9; /* Local Access Window 9 Attrs */
97 u8 res19_10a[20];
98 u32 lawbar10; /* Local Access Window 10 Base Addr */
99 u8 res19_10b[4];
100 u32 lawar10; /* Local Access Window 10 Attrs */
101 u8 res19_11a[20];
102 u32 lawbar11; /* Local Access Window 11 Base Addr */
103 u8 res19_11b[4];
104 u32 lawar11; /* Local Access Window 11 Attrs */
105 u8 res20[652];
106 u32 eebacr; /* ECM CCB Addr Configuration */
107 u8 res21[12];
108 u32 eebpcr; /* ECM CCB Port Configuration */
109 u8 res22[3564];
110 u32 eedr; /* ECM Error Detect */
111 u8 res23[4];
112 u32 eeer; /* ECM Error Enable */
113 u32 eeatr; /* ECM Error Attrs Capture */
114 u32 eeadr; /* ECM Error Addr Capture */
115 u8 res24[492];
116 } ccsr_local_ecm_t;
117
118 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
119 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
120
121 /* I2C Registers */
122 typedef struct ccsr_i2c {
123 struct fsl_i2c_base i2c[1];
124 u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
125 } ccsr_i2c_t;
126
127 #if defined(CONFIG_ARCH_MPC8540) || \
128 defined(CONFIG_ARCH_MPC8541) || \
129 defined(CONFIG_ARCH_MPC8548) || \
130 defined(CONFIG_ARCH_MPC8555)
131 /* DUART Registers */
132 typedef struct ccsr_duart {
133 u8 res1[1280];
134 /* URBR1, UTHR1, UDLB1 with the same addr */
135 u8 urbr1_uthr1_udlb1;
136 /* UIER1, UDMB1 with the same addr01 */
137 u8 uier1_udmb1;
138 /* UIIR1, UFCR1, UAFR1 with the same addr */
139 u8 uiir1_ufcr1_uafr1;
140 u8 ulcr1; /* UART1 Line Control */
141 u8 umcr1; /* UART1 Modem Control */
142 u8 ulsr1; /* UART1 Line Status */
143 u8 umsr1; /* UART1 Modem Status */
144 u8 uscr1; /* UART1 Scratch */
145 u8 res2[8];
146 u8 udsr1; /* UART1 DMA Status */
147 u8 res3[239];
148 /* URBR2, UTHR2, UDLB2 with the same addr */
149 u8 urbr2_uthr2_udlb2;
150 /* UIER2, UDMB2 with the same addr */
151 u8 uier2_udmb2;
152 /* UIIR2, UFCR2, UAFR2 with the same addr */
153 u8 uiir2_ufcr2_uafr2;
154 u8 ulcr2; /* UART2 Line Control */
155 u8 umcr2; /* UART2 Modem Control */
156 u8 ulsr2; /* UART2 Line Status */
157 u8 umsr2; /* UART2 Modem Status */
158 u8 uscr2; /* UART2 Scratch */
159 u8 res4[8];
160 u8 udsr2; /* UART2 DMA Status */
161 u8 res5[2543];
162 } ccsr_duart_t;
163 #else /* MPC8560 uses UART on its CPM */
164 typedef struct ccsr_duart {
165 u8 res[4096];
166 } ccsr_duart_t;
167 #endif
168
169 /* eSPI Registers */
170 typedef struct ccsr_espi {
171 u32 mode; /* eSPI mode */
172 u32 event; /* eSPI event */
173 u32 mask; /* eSPI mask */
174 u32 com; /* eSPI command */
175 u32 tx; /* eSPI transmit FIFO access */
176 u32 rx; /* eSPI receive FIFO access */
177 u8 res1[8]; /* reserved */
178 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
179 u8 res2[4048]; /* fill up to 0x1000 */
180 } ccsr_espi_t;
181
182 /* PCI Registers */
183 typedef struct ccsr_pcix {
184 u32 cfg_addr; /* PCIX Configuration Addr */
185 u32 cfg_data; /* PCIX Configuration Data */
186 u32 int_ack; /* PCIX IRQ Acknowledge */
187 u8 res000c[52];
188 u32 liodn_base; /* PCIX LIODN base register */
189 u8 res0044[2996];
190 u32 ipver1; /* PCIX IP block revision register 1 */
191 u32 ipver2; /* PCIX IP block revision register 2 */
192 u32 potar0; /* PCIX Outbound Transaction Addr 0 */
193 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
194 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
195 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */
196 u32 powar0; /* PCIX Outbound Window Attrs 0 */
197 u8 res2[12];
198 u32 potar1; /* PCIX Outbound Transaction Addr 1 */
199 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */
200 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */
201 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */
202 u32 powar1; /* PCIX Outbound Window Attrs 1 */
203 u8 res3[12];
204 u32 potar2; /* PCIX Outbound Transaction Addr 2 */
205 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */
206 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */
207 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */
208 u32 powar2; /* PCIX Outbound Window Attrs 2 */
209 u8 res4[12];
210 u32 potar3; /* PCIX Outbound Transaction Addr 3 */
211 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */
212 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */
213 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */
214 u32 powar3; /* PCIX Outbound Window Attrs 3 */
215 u8 res5[12];
216 u32 potar4; /* PCIX Outbound Transaction Addr 4 */
217 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */
218 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */
219 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */
220 u32 powar4; /* PCIX Outbound Window Attrs 4 */
221 u8 res6[268];
222 u32 pitar3; /* PCIX Inbound Translation Addr 3 */
223 u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */
224 u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */
225 u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */
226 u32 piwar3; /* PCIX Inbound Window Attrs 3 */
227 u8 res7[12];
228 u32 pitar2; /* PCIX Inbound Translation Addr 2 */
229 u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */
230 u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */
231 u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */
232 u32 piwar2; /* PCIX Inbound Window Attrs 2 */
233 u8 res8[12];
234 u32 pitar1; /* PCIX Inbound Translation Addr 1 */
235 u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */
236 u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */
237 u8 res9[4];
238 u32 piwar1; /* PCIX Inbound Window Attrs 1 */
239 u8 res10[12];
240 u32 pedr; /* PCIX Error Detect */
241 u32 pecdr; /* PCIX Error Capture Disable */
242 u32 peer; /* PCIX Error Enable */
243 u32 peattrcr; /* PCIX Error Attrs Capture */
244 u32 peaddrcr; /* PCIX Error Addr Capture */
245 u32 peextaddrcr; /* PCIX Error Extended Addr Capture */
246 u32 pedlcr; /* PCIX Error Data Low Capture */
247 u32 pedhcr; /* PCIX Error Error Data High Capture */
248 u32 gas_timr; /* PCIX Gasket Timer */
249 u8 res11[476];
250 } ccsr_pcix_t;
251
252 #define PCIX_COMMAND 0x62
253 #define POWAR_EN 0x80000000
254 #define POWAR_IO_READ 0x00080000
255 #define POWAR_MEM_READ 0x00040000
256 #define POWAR_IO_WRITE 0x00008000
257 #define POWAR_MEM_WRITE 0x00004000
258 #define POWAR_MEM_512M 0x0000001c
259 #define POWAR_IO_1M 0x00000013
260
261 #define PIWAR_EN 0x80000000
262 #define PIWAR_PF 0x20000000
263 #define PIWAR_LOCAL 0x00f00000
264 #define PIWAR_READ_SNOOP 0x00050000
265 #define PIWAR_WRITE_SNOOP 0x00005000
266 #define PIWAR_MEM_2G 0x0000001e
267
268 #ifndef CONFIG_MPC85XX_GPIO
269 typedef struct ccsr_gpio {
270 u32 gpdir;
271 u32 gpodr;
272 u32 gpdat;
273 u32 gpier;
274 u32 gpimr;
275 u32 gpicr;
276 } ccsr_gpio_t;
277 #endif
278
279 /* L2 Cache Registers */
280 typedef struct ccsr_l2cache {
281 u32 l2ctl; /* L2 configuration 0 */
282 u8 res1[12];
283 u32 l2cewar0; /* L2 cache external write addr 0 */
284 u8 res2[4];
285 u32 l2cewcr0; /* L2 cache external write control 0 */
286 u8 res3[4];
287 u32 l2cewar1; /* L2 cache external write addr 1 */
288 u8 res4[4];
289 u32 l2cewcr1; /* L2 cache external write control 1 */
290 u8 res5[4];
291 u32 l2cewar2; /* L2 cache external write addr 2 */
292 u8 res6[4];
293 u32 l2cewcr2; /* L2 cache external write control 2 */
294 u8 res7[4];
295 u32 l2cewar3; /* L2 cache external write addr 3 */
296 u8 res8[4];
297 u32 l2cewcr3; /* L2 cache external write control 3 */
298 u8 res9[180];
299 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
300 u8 res10[4];
301 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */
302 u8 res11[3316];
303 u32 l2errinjhi; /* L2 error injection mask high */
304 u32 l2errinjlo; /* L2 error injection mask low */
305 u32 l2errinjctl; /* L2 error injection tag/ECC control */
306 u8 res12[20];
307 u32 l2captdatahi; /* L2 error data high capture */
308 u32 l2captdatalo; /* L2 error data low capture */
309 u32 l2captecc; /* L2 error ECC capture */
310 u8 res13[20];
311 u32 l2errdet; /* L2 error detect */
312 u32 l2errdis; /* L2 error disable */
313 u32 l2errinten; /* L2 error interrupt enable */
314 u32 l2errattr; /* L2 error attributes capture */
315 u32 l2erraddr; /* L2 error addr capture */
316 u8 res14[4];
317 u32 l2errctl; /* L2 error control */
318 u8 res15[420];
319 } ccsr_l2cache_t;
320
321 #define MPC85xx_L2CTL_L2E 0x80000000
322 #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
323 #define MPC85xx_L2ERRDIS_MBECC 0x00000008
324 #define MPC85xx_L2ERRDIS_SBECC 0x00000004
325
326 /* DMA Registers */
327 typedef struct ccsr_dma {
328 u8 res1[256];
329 struct fsl_dma dma[4];
330 u32 dgsr; /* DMA General Status */
331 u8 res2[11516];
332 } ccsr_dma_t;
333
334 /* tsec */
335 typedef struct ccsr_tsec {
336 u8 res1[16];
337 u32 ievent; /* IRQ Event */
338 u32 imask; /* IRQ Mask */
339 u32 edis; /* Error Disabled */
340 u8 res2[4];
341 u32 ecntrl; /* Ethernet Control */
342 u32 minflr; /* Minimum Frame Len */
343 u32 ptv; /* Pause Time Value */
344 u32 dmactrl; /* DMA Control */
345 u32 tbipa; /* TBI PHY Addr */
346 u8 res3[88];
347 u32 fifo_tx_thr; /* FIFO transmit threshold */
348 u8 res4[8];
349 u32 fifo_tx_starve; /* FIFO transmit starve */
350 u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */
351 u8 res5[96];
352 u32 tctrl; /* TX Control */
353 u32 tstat; /* TX Status */
354 u8 res6[4];
355 u32 tbdlen; /* TX Buffer Desc Data Len */
356 u8 res7[16];
357 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */
358 u32 ctbptr; /* Current TX Buffer Desc Ptr */
359 u8 res8[88];
360 u32 tbptrh; /* TX Buffer Desc Ptr High */
361 u32 tbptr; /* TX Buffer Desc Ptr Low */
362 u8 res9[120];
363 u32 tbaseh; /* TX Desc Base Addr High */
364 u32 tbase; /* TX Desc Base Addr */
365 u8 res10[168];
366 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
367 u32 ostbdp; /* OOS TX Data Buffer Ptr */
368 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */
369 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */
370 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */
371 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */
372 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */
373 u8 res11[52];
374 u32 rctrl; /* RX Control */
375 u32 rstat; /* RX Status */
376 u8 res12[4];
377 u32 rbdlen; /* RxBD Data Len */
378 u8 res13[16];
379 u32 crbptrh; /* Current RX Buffer Desc Ptr High */
380 u32 crbptr; /* Current RX Buffer Desc Ptr */
381 u8 res14[24];
382 u32 mrblr; /* Maximum RX Buffer Len */
383 u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */
384 u8 res15[56];
385 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */
386 u32 rbptr; /* RX Buffer Desc Ptr */
387 u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */
388 u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */
389 u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */
390 u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */
391 u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */
392 u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */
393 u8 res16[96];
394 u32 rbaseh; /* RX Desc Base Addr High 0 */
395 u32 rbase; /* RX Desc Base Addr */
396 u32 rbaseh1; /* RX Desc Base Addr High 1 */
397 u32 rbasel1; /* RX Desc Base Addr Low 1 */
398 u32 rbaseh2; /* RX Desc Base Addr High 2 */
399 u32 rbasel2; /* RX Desc Base Addr Low 2 */
400 u32 rbaseh3; /* RX Desc Base Addr High 3 */
401 u32 rbasel3; /* RX Desc Base Addr Low 3 */
402 u8 res17[224];
403 u32 maccfg1; /* MAC Configuration 1 */
404 u32 maccfg2; /* MAC Configuration 2 */
405 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
406 u32 hafdup; /* Half Duplex */
407 u32 maxfrm; /* Maximum Frame Len */
408 u8 res18[12];
409 u32 miimcfg; /* MII Management Configuration */
410 u32 miimcom; /* MII Management Cmd */
411 u32 miimadd; /* MII Management Addr */
412 u32 miimcon; /* MII Management Control */
413 u32 miimstat; /* MII Management Status */
414 u32 miimind; /* MII Management Indicator */
415 u8 res19[4];
416 u32 ifstat; /* Interface Status */
417 u32 macstnaddr1; /* Station Addr Part 1 */
418 u32 macstnaddr2; /* Station Addr Part 2 */
419 u8 res20[312];
420 u32 tr64; /* TX & RX 64-byte Frame Counter */
421 u32 tr127; /* TX & RX 65-127 byte Frame Counter */
422 u32 tr255; /* TX & RX 128-255 byte Frame Counter */
423 u32 tr511; /* TX & RX 256-511 byte Frame Counter */
424 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
425 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
426 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
427 u32 rbyt; /* RX Byte Counter */
428 u32 rpkt; /* RX Packet Counter */
429 u32 rfcs; /* RX FCS Error Counter */
430 u32 rmca; /* RX Multicast Packet Counter */
431 u32 rbca; /* RX Broadcast Packet Counter */
432 u32 rxcf; /* RX Control Frame Packet Counter */
433 u32 rxpf; /* RX Pause Frame Packet Counter */
434 u32 rxuo; /* RX Unknown OP Code Counter */
435 u32 raln; /* RX Alignment Error Counter */
436 u32 rflr; /* RX Frame Len Error Counter */
437 u32 rcde; /* RX Code Error Counter */
438 u32 rcse; /* RX Carrier Sense Error Counter */
439 u32 rund; /* RX Undersize Packet Counter */
440 u32 rovr; /* RX Oversize Packet Counter */
441 u32 rfrg; /* RX Fragments Counter */
442 u32 rjbr; /* RX Jabber Counter */
443 u32 rdrp; /* RX Drop Counter */
444 u32 tbyt; /* TX Byte Counter Counter */
445 u32 tpkt; /* TX Packet Counter */
446 u32 tmca; /* TX Multicast Packet Counter */
447 u32 tbca; /* TX Broadcast Packet Counter */
448 u32 txpf; /* TX Pause Control Frame Counter */
449 u32 tdfr; /* TX Deferral Packet Counter */
450 u32 tedf; /* TX Excessive Deferral Packet Counter */
451 u32 tscl; /* TX Single Collision Packet Counter */
452 u32 tmcl; /* TX Multiple Collision Packet Counter */
453 u32 tlcl; /* TX Late Collision Packet Counter */
454 u32 txcl; /* TX Excessive Collision Packet Counter */
455 u32 tncl; /* TX Total Collision Counter */
456 u8 res21[4];
457 u32 tdrp; /* TX Drop Frame Counter */
458 u32 tjbr; /* TX Jabber Frame Counter */
459 u32 tfcs; /* TX FCS Error Counter */
460 u32 txcf; /* TX Control Frame Counter */
461 u32 tovr; /* TX Oversize Frame Counter */
462 u32 tund; /* TX Undersize Frame Counter */
463 u32 tfrg; /* TX Fragments Frame Counter */
464 u32 car1; /* Carry One */
465 u32 car2; /* Carry Two */
466 u32 cam1; /* Carry Mask One */
467 u32 cam2; /* Carry Mask Two */
468 u8 res22[192];
469 u32 iaddr0; /* Indivdual addr 0 */
470 u32 iaddr1; /* Indivdual addr 1 */
471 u32 iaddr2; /* Indivdual addr 2 */
472 u32 iaddr3; /* Indivdual addr 3 */
473 u32 iaddr4; /* Indivdual addr 4 */
474 u32 iaddr5; /* Indivdual addr 5 */
475 u32 iaddr6; /* Indivdual addr 6 */
476 u32 iaddr7; /* Indivdual addr 7 */
477 u8 res23[96];
478 u32 gaddr0; /* Global addr 0 */
479 u32 gaddr1; /* Global addr 1 */
480 u32 gaddr2; /* Global addr 2 */
481 u32 gaddr3; /* Global addr 3 */
482 u32 gaddr4; /* Global addr 4 */
483 u32 gaddr5; /* Global addr 5 */
484 u32 gaddr6; /* Global addr 6 */
485 u32 gaddr7; /* Global addr 7 */
486 u8 res24[96];
487 u32 pmd0; /* Pattern Match Data */
488 u8 res25[4];
489 u32 pmask0; /* Pattern Mask */
490 u8 res26[4];
491 u32 pcntrl0; /* Pattern Match Control */
492 u8 res27[4];
493 u32 pattrb0; /* Pattern Match Attrs */
494 u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */
495 u32 pmd1; /* Pattern Match Data */
496 u8 res28[4];
497 u32 pmask1; /* Pattern Mask */
498 u8 res29[4];
499 u32 pcntrl1; /* Pattern Match Control */
500 u8 res30[4];
501 u32 pattrb1; /* Pattern Match Attrs */
502 u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */
503 u32 pmd2; /* Pattern Match Data */
504 u8 res31[4];
505 u32 pmask2; /* Pattern Mask */
506 u8 res32[4];
507 u32 pcntrl2; /* Pattern Match Control */
508 u8 res33[4];
509 u32 pattrb2; /* Pattern Match Attrs */
510 u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */
511 u32 pmd3; /* Pattern Match Data */
512 u8 res34[4];
513 u32 pmask3; /* Pattern Mask */
514 u8 res35[4];
515 u32 pcntrl3; /* Pattern Match Control */
516 u8 res36[4];
517 u32 pattrb3; /* Pattern Match Attrs */
518 u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */
519 u32 pmd4; /* Pattern Match Data */
520 u8 res37[4];
521 u32 pmask4; /* Pattern Mask */
522 u8 res38[4];
523 u32 pcntrl4; /* Pattern Match Control */
524 u8 res39[4];
525 u32 pattrb4; /* Pattern Match Attrs */
526 u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */
527 u32 pmd5; /* Pattern Match Data */
528 u8 res40[4];
529 u32 pmask5; /* Pattern Mask */
530 u8 res41[4];
531 u32 pcntrl5; /* Pattern Match Control */
532 u8 res42[4];
533 u32 pattrb5; /* Pattern Match Attrs */
534 u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */
535 u32 pmd6; /* Pattern Match Data */
536 u8 res43[4];
537 u32 pmask6; /* Pattern Mask */
538 u8 res44[4];
539 u32 pcntrl6; /* Pattern Match Control */
540 u8 res45[4];
541 u32 pattrb6; /* Pattern Match Attrs */
542 u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */
543 u32 pmd7; /* Pattern Match Data */
544 u8 res46[4];
545 u32 pmask7; /* Pattern Mask */
546 u8 res47[4];
547 u32 pcntrl7; /* Pattern Match Control */
548 u8 res48[4];
549 u32 pattrb7; /* Pattern Match Attrs */
550 u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */
551 u32 pmd8; /* Pattern Match Data */
552 u8 res49[4];
553 u32 pmask8; /* Pattern Mask */
554 u8 res50[4];
555 u32 pcntrl8; /* Pattern Match Control */
556 u8 res51[4];
557 u32 pattrb8; /* Pattern Match Attrs */
558 u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */
559 u32 pmd9; /* Pattern Match Data */
560 u8 res52[4];
561 u32 pmask9; /* Pattern Mask */
562 u8 res53[4];
563 u32 pcntrl9; /* Pattern Match Control */
564 u8 res54[4];
565 u32 pattrb9; /* Pattern Match Attrs */
566 u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */
567 u32 pmd10; /* Pattern Match Data */
568 u8 res55[4];
569 u32 pmask10; /* Pattern Mask */
570 u8 res56[4];
571 u32 pcntrl10; /* Pattern Match Control */
572 u8 res57[4];
573 u32 pattrb10; /* Pattern Match Attrs */
574 u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */
575 u32 pmd11; /* Pattern Match Data */
576 u8 res58[4];
577 u32 pmask11; /* Pattern Mask */
578 u8 res59[4];
579 u32 pcntrl11; /* Pattern Match Control */
580 u8 res60[4];
581 u32 pattrb11; /* Pattern Match Attrs */
582 u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */
583 u32 pmd12; /* Pattern Match Data */
584 u8 res61[4];
585 u32 pmask12; /* Pattern Mask */
586 u8 res62[4];
587 u32 pcntrl12; /* Pattern Match Control */
588 u8 res63[4];
589 u32 pattrb12; /* Pattern Match Attrs */
590 u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */
591 u32 pmd13; /* Pattern Match Data */
592 u8 res64[4];
593 u32 pmask13; /* Pattern Mask */
594 u8 res65[4];
595 u32 pcntrl13; /* Pattern Match Control */
596 u8 res66[4];
597 u32 pattrb13; /* Pattern Match Attrs */
598 u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */
599 u32 pmd14; /* Pattern Match Data */
600 u8 res67[4];
601 u32 pmask14; /* Pattern Mask */
602 u8 res68[4];
603 u32 pcntrl14; /* Pattern Match Control */
604 u8 res69[4];
605 u32 pattrb14; /* Pattern Match Attrs */
606 u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */
607 u32 pmd15; /* Pattern Match Data */
608 u8 res70[4];
609 u32 pmask15; /* Pattern Mask */
610 u8 res71[4];
611 u32 pcntrl15; /* Pattern Match Control */
612 u8 res72[4];
613 u32 pattrb15; /* Pattern Match Attrs */
614 u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */
615 u8 res73[248];
616 u32 attr; /* Attrs */
617 u32 attreli; /* Attrs Extract Len & Idx */
618 u8 res74[1024];
619 } ccsr_tsec_t;
620
621 /* PIC Registers */
622 typedef struct ccsr_pic {
623 u8 res1[64];
624 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */
625 u8 res2[12];
626 u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */
627 u8 res3[12];
628 u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */
629 u8 res4[12];
630 u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */
631 u8 res5[12];
632 u32 ctpr; /* Current Task Priority */
633 u8 res6[12];
634 u32 whoami; /* Who Am I */
635 u8 res7[12];
636 u32 iack; /* IRQ Acknowledge */
637 u8 res8[12];
638 u32 eoi; /* End Of IRQ */
639 u8 res9[3916];
640 u32 frr; /* Feature Reporting */
641 u8 res10[28];
642 u32 gcr; /* Global Configuration */
643 #define MPC85xx_PICGCR_RST 0x80000000
644 #define MPC85xx_PICGCR_M 0x20000000
645 u8 res11[92];
646 u32 vir; /* Vendor Identification */
647 u8 res12[12];
648 u32 pir; /* Processor Initialization */
649 u8 res13[12];
650 u32 ipivpr0; /* IPI Vector/Priority 0 */
651 u8 res14[12];
652 u32 ipivpr1; /* IPI Vector/Priority 1 */
653 u8 res15[12];
654 u32 ipivpr2; /* IPI Vector/Priority 2 */
655 u8 res16[12];
656 u32 ipivpr3; /* IPI Vector/Priority 3 */
657 u8 res17[12];
658 u32 svr; /* Spurious Vector */
659 u8 res18[12];
660 u32 tfrr; /* Timer Frequency Reporting */
661 u8 res19[12];
662 u32 gtccr0; /* Global Timer Current Count 0 */
663 u8 res20[12];
664 u32 gtbcr0; /* Global Timer Base Count 0 */
665 u8 res21[12];
666 u32 gtvpr0; /* Global Timer Vector/Priority 0 */
667 u8 res22[12];
668 u32 gtdr0; /* Global Timer Destination 0 */
669 u8 res23[12];
670 u32 gtccr1; /* Global Timer Current Count 1 */
671 u8 res24[12];
672 u32 gtbcr1; /* Global Timer Base Count 1 */
673 u8 res25[12];
674 u32 gtvpr1; /* Global Timer Vector/Priority 1 */
675 u8 res26[12];
676 u32 gtdr1; /* Global Timer Destination 1 */
677 u8 res27[12];
678 u32 gtccr2; /* Global Timer Current Count 2 */
679 u8 res28[12];
680 u32 gtbcr2; /* Global Timer Base Count 2 */
681 u8 res29[12];
682 u32 gtvpr2; /* Global Timer Vector/Priority 2 */
683 u8 res30[12];
684 u32 gtdr2; /* Global Timer Destination 2 */
685 u8 res31[12];
686 u32 gtccr3; /* Global Timer Current Count 3 */
687 u8 res32[12];
688 u32 gtbcr3; /* Global Timer Base Count 3 */
689 u8 res33[12];
690 u32 gtvpr3; /* Global Timer Vector/Priority 3 */
691 u8 res34[12];
692 u32 gtdr3; /* Global Timer Destination 3 */
693 u8 res35[268];
694 u32 tcr; /* Timer Control */
695 u8 res36[12];
696 u32 irqsr0; /* IRQ_OUT Summary 0 */
697 u8 res37[12];
698 u32 irqsr1; /* IRQ_OUT Summary 1 */
699 u8 res38[12];
700 u32 cisr0; /* Critical IRQ Summary 0 */
701 u8 res39[12];
702 u32 cisr1; /* Critical IRQ Summary 1 */
703 u8 res40[188];
704 u32 msgr0; /* Message 0 */
705 u8 res41[12];
706 u32 msgr1; /* Message 1 */
707 u8 res42[12];
708 u32 msgr2; /* Message 2 */
709 u8 res43[12];
710 u32 msgr3; /* Message 3 */
711 u8 res44[204];
712 u32 mer; /* Message Enable */
713 u8 res45[12];
714 u32 msr; /* Message Status */
715 u8 res46[60140];
716 u32 eivpr0; /* External IRQ Vector/Priority 0 */
717 u8 res47[12];
718 u32 eidr0; /* External IRQ Destination 0 */
719 u8 res48[12];
720 u32 eivpr1; /* External IRQ Vector/Priority 1 */
721 u8 res49[12];
722 u32 eidr1; /* External IRQ Destination 1 */
723 u8 res50[12];
724 u32 eivpr2; /* External IRQ Vector/Priority 2 */
725 u8 res51[12];
726 u32 eidr2; /* External IRQ Destination 2 */
727 u8 res52[12];
728 u32 eivpr3; /* External IRQ Vector/Priority 3 */
729 u8 res53[12];
730 u32 eidr3; /* External IRQ Destination 3 */
731 u8 res54[12];
732 u32 eivpr4; /* External IRQ Vector/Priority 4 */
733 u8 res55[12];
734 u32 eidr4; /* External IRQ Destination 4 */
735 u8 res56[12];
736 u32 eivpr5; /* External IRQ Vector/Priority 5 */
737 u8 res57[12];
738 u32 eidr5; /* External IRQ Destination 5 */
739 u8 res58[12];
740 u32 eivpr6; /* External IRQ Vector/Priority 6 */
741 u8 res59[12];
742 u32 eidr6; /* External IRQ Destination 6 */
743 u8 res60[12];
744 u32 eivpr7; /* External IRQ Vector/Priority 7 */
745 u8 res61[12];
746 u32 eidr7; /* External IRQ Destination 7 */
747 u8 res62[12];
748 u32 eivpr8; /* External IRQ Vector/Priority 8 */
749 u8 res63[12];
750 u32 eidr8; /* External IRQ Destination 8 */
751 u8 res64[12];
752 u32 eivpr9; /* External IRQ Vector/Priority 9 */
753 u8 res65[12];
754 u32 eidr9; /* External IRQ Destination 9 */
755 u8 res66[12];
756 u32 eivpr10; /* External IRQ Vector/Priority 10 */
757 u8 res67[12];
758 u32 eidr10; /* External IRQ Destination 10 */
759 u8 res68[12];
760 u32 eivpr11; /* External IRQ Vector/Priority 11 */
761 u8 res69[12];
762 u32 eidr11; /* External IRQ Destination 11 */
763 u8 res70[140];
764 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */
765 u8 res71[12];
766 u32 iidr0; /* Internal IRQ Destination 0 */
767 u8 res72[12];
768 u32 iivpr1; /* Internal IRQ Vector/Priority 1 */
769 u8 res73[12];
770 u32 iidr1; /* Internal IRQ Destination 1 */
771 u8 res74[12];
772 u32 iivpr2; /* Internal IRQ Vector/Priority 2 */
773 u8 res75[12];
774 u32 iidr2; /* Internal IRQ Destination 2 */
775 u8 res76[12];
776 u32 iivpr3; /* Internal IRQ Vector/Priority 3 */
777 u8 res77[12];
778 u32 iidr3; /* Internal IRQ Destination 3 */
779 u8 res78[12];
780 u32 iivpr4; /* Internal IRQ Vector/Priority 4 */
781 u8 res79[12];
782 u32 iidr4; /* Internal IRQ Destination 4 */
783 u8 res80[12];
784 u32 iivpr5; /* Internal IRQ Vector/Priority 5 */
785 u8 res81[12];
786 u32 iidr5; /* Internal IRQ Destination 5 */
787 u8 res82[12];
788 u32 iivpr6; /* Internal IRQ Vector/Priority 6 */
789 u8 res83[12];
790 u32 iidr6; /* Internal IRQ Destination 6 */
791 u8 res84[12];
792 u32 iivpr7; /* Internal IRQ Vector/Priority 7 */
793 u8 res85[12];
794 u32 iidr7; /* Internal IRQ Destination 7 */
795 u8 res86[12];
796 u32 iivpr8; /* Internal IRQ Vector/Priority 8 */
797 u8 res87[12];
798 u32 iidr8; /* Internal IRQ Destination 8 */
799 u8 res88[12];
800 u32 iivpr9; /* Internal IRQ Vector/Priority 9 */
801 u8 res89[12];
802 u32 iidr9; /* Internal IRQ Destination 9 */
803 u8 res90[12];
804 u32 iivpr10; /* Internal IRQ Vector/Priority 10 */
805 u8 res91[12];
806 u32 iidr10; /* Internal IRQ Destination 10 */
807 u8 res92[12];
808 u32 iivpr11; /* Internal IRQ Vector/Priority 11 */
809 u8 res93[12];
810 u32 iidr11; /* Internal IRQ Destination 11 */
811 u8 res94[12];
812 u32 iivpr12; /* Internal IRQ Vector/Priority 12 */
813 u8 res95[12];
814 u32 iidr12; /* Internal IRQ Destination 12 */
815 u8 res96[12];
816 u32 iivpr13; /* Internal IRQ Vector/Priority 13 */
817 u8 res97[12];
818 u32 iidr13; /* Internal IRQ Destination 13 */
819 u8 res98[12];
820 u32 iivpr14; /* Internal IRQ Vector/Priority 14 */
821 u8 res99[12];
822 u32 iidr14; /* Internal IRQ Destination 14 */
823 u8 res100[12];
824 u32 iivpr15; /* Internal IRQ Vector/Priority 15 */
825 u8 res101[12];
826 u32 iidr15; /* Internal IRQ Destination 15 */
827 u8 res102[12];
828 u32 iivpr16; /* Internal IRQ Vector/Priority 16 */
829 u8 res103[12];
830 u32 iidr16; /* Internal IRQ Destination 16 */
831 u8 res104[12];
832 u32 iivpr17; /* Internal IRQ Vector/Priority 17 */
833 u8 res105[12];
834 u32 iidr17; /* Internal IRQ Destination 17 */
835 u8 res106[12];
836 u32 iivpr18; /* Internal IRQ Vector/Priority 18 */
837 u8 res107[12];
838 u32 iidr18; /* Internal IRQ Destination 18 */
839 u8 res108[12];
840 u32 iivpr19; /* Internal IRQ Vector/Priority 19 */
841 u8 res109[12];
842 u32 iidr19; /* Internal IRQ Destination 19 */
843 u8 res110[12];
844 u32 iivpr20; /* Internal IRQ Vector/Priority 20 */
845 u8 res111[12];
846 u32 iidr20; /* Internal IRQ Destination 20 */
847 u8 res112[12];
848 u32 iivpr21; /* Internal IRQ Vector/Priority 21 */
849 u8 res113[12];
850 u32 iidr21; /* Internal IRQ Destination 21 */
851 u8 res114[12];
852 u32 iivpr22; /* Internal IRQ Vector/Priority 22 */
853 u8 res115[12];
854 u32 iidr22; /* Internal IRQ Destination 22 */
855 u8 res116[12];
856 u32 iivpr23; /* Internal IRQ Vector/Priority 23 */
857 u8 res117[12];
858 u32 iidr23; /* Internal IRQ Destination 23 */
859 u8 res118[12];
860 u32 iivpr24; /* Internal IRQ Vector/Priority 24 */
861 u8 res119[12];
862 u32 iidr24; /* Internal IRQ Destination 24 */
863 u8 res120[12];
864 u32 iivpr25; /* Internal IRQ Vector/Priority 25 */
865 u8 res121[12];
866 u32 iidr25; /* Internal IRQ Destination 25 */
867 u8 res122[12];
868 u32 iivpr26; /* Internal IRQ Vector/Priority 26 */
869 u8 res123[12];
870 u32 iidr26; /* Internal IRQ Destination 26 */
871 u8 res124[12];
872 u32 iivpr27; /* Internal IRQ Vector/Priority 27 */
873 u8 res125[12];
874 u32 iidr27; /* Internal IRQ Destination 27 */
875 u8 res126[12];
876 u32 iivpr28; /* Internal IRQ Vector/Priority 28 */
877 u8 res127[12];
878 u32 iidr28; /* Internal IRQ Destination 28 */
879 u8 res128[12];
880 u32 iivpr29; /* Internal IRQ Vector/Priority 29 */
881 u8 res129[12];
882 u32 iidr29; /* Internal IRQ Destination 29 */
883 u8 res130[12];
884 u32 iivpr30; /* Internal IRQ Vector/Priority 30 */
885 u8 res131[12];
886 u32 iidr30; /* Internal IRQ Destination 30 */
887 u8 res132[12];
888 u32 iivpr31; /* Internal IRQ Vector/Priority 31 */
889 u8 res133[12];
890 u32 iidr31; /* Internal IRQ Destination 31 */
891 u8 res134[4108];
892 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */
893 u8 res135[12];
894 u32 midr0; /* Messaging IRQ Destination 0 */
895 u8 res136[12];
896 u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */
897 u8 res137[12];
898 u32 midr1; /* Messaging IRQ Destination 1 */
899 u8 res138[12];
900 u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */
901 u8 res139[12];
902 u32 midr2; /* Messaging IRQ Destination 2 */
903 u8 res140[12];
904 u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */
905 u8 res141[12];
906 u32 midr3; /* Messaging IRQ Destination 3 */
907 u8 res142[59852];
908 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */
909 u8 res143[12];
910 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */
911 u8 res144[12];
912 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */
913 u8 res145[12];
914 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */
915 u8 res146[12];
916 u32 ctpr0; /* Current Task Priority for Processor 0 */
917 u8 res147[12];
918 u32 whoami0; /* Who Am I for Processor 0 */
919 u8 res148[12];
920 u32 iack0; /* IRQ Acknowledge for Processor 0 */
921 u8 res149[12];
922 u32 eoi0; /* End Of IRQ for Processor 0 */
923 u8 res150[130892];
924 } ccsr_pic_t;
925
926 /* CPM Block */
927 #ifndef CONFIG_CPM2
928 typedef struct ccsr_cpm {
929 u8 res[262144];
930 } ccsr_cpm_t;
931 #else
932 /*
933 * DPARM
934 * General SIU
935 */
936 typedef struct ccsr_cpm_siu {
937 u8 res1[80];
938 u32 smaer;
939 u32 smser;
940 u32 smevr;
941 u8 res2[4];
942 u32 lmaer;
943 u32 lmser;
944 u32 lmevr;
945 u8 res3[2964];
946 } ccsr_cpm_siu_t;
947
948 /* IRQ Controller */
949 typedef struct ccsr_cpm_intctl {
950 u16 sicr;
951 u8 res1[2];
952 u32 sivec;
953 u32 sipnrh;
954 u32 sipnrl;
955 u32 siprr;
956 u32 scprrh;
957 u32 scprrl;
958 u32 simrh;
959 u32 simrl;
960 u32 siexr;
961 u8 res2[88];
962 u32 sccr;
963 u8 res3[124];
964 } ccsr_cpm_intctl_t;
965
966 /* input/output port */
967 typedef struct ccsr_cpm_iop {
968 u32 pdira;
969 u32 ppara;
970 u32 psora;
971 u32 podra;
972 u32 pdata;
973 u8 res1[12];
974 u32 pdirb;
975 u32 pparb;
976 u32 psorb;
977 u32 podrb;
978 u32 pdatb;
979 u8 res2[12];
980 u32 pdirc;
981 u32 pparc;
982 u32 psorc;
983 u32 podrc;
984 u32 pdatc;
985 u8 res3[12];
986 u32 pdird;
987 u32 ppard;
988 u32 psord;
989 u32 podrd;
990 u32 pdatd;
991 u8 res4[12];
992 } ccsr_cpm_iop_t;
993
994 /* CPM timers */
995 typedef struct ccsr_cpm_timer {
996 u8 tgcr1;
997 u8 res1[3];
998 u8 tgcr2;
999 u8 res2[11];
1000 u16 tmr1;
1001 u16 tmr2;
1002 u16 trr1;
1003 u16 trr2;
1004 u16 tcr1;
1005 u16 tcr2;
1006 u16 tcn1;
1007 u16 tcn2;
1008 u16 tmr3;
1009 u16 tmr4;
1010 u16 trr3;
1011 u16 trr4;
1012 u16 tcr3;
1013 u16 tcr4;
1014 u16 tcn3;
1015 u16 tcn4;
1016 u16 ter1;
1017 u16 ter2;
1018 u16 ter3;
1019 u16 ter4;
1020 u8 res3[608];
1021 } ccsr_cpm_timer_t;
1022
1023 /* SDMA */
1024 typedef struct ccsr_cpm_sdma {
1025 u8 sdsr;
1026 u8 res1[3];
1027 u8 sdmr;
1028 u8 res2[739];
1029 } ccsr_cpm_sdma_t;
1030
1031 /* FCC1 */
1032 typedef struct ccsr_cpm_fcc1 {
1033 u32 gfmr;
1034 u32 fpsmr;
1035 u16 ftodr;
1036 u8 res1[2];
1037 u16 fdsr;
1038 u8 res2[2];
1039 u16 fcce;
1040 u8 res3[2];
1041 u16 fccm;
1042 u8 res4[2];
1043 u8 fccs;
1044 u8 res5[3];
1045 u8 ftirr_phy[4];
1046 } ccsr_cpm_fcc1_t;
1047
1048 /* FCC2 */
1049 typedef struct ccsr_cpm_fcc2 {
1050 u32 gfmr;
1051 u32 fpsmr;
1052 u16 ftodr;
1053 u8 res1[2];
1054 u16 fdsr;
1055 u8 res2[2];
1056 u16 fcce;
1057 u8 res3[2];
1058 u16 fccm;
1059 u8 res4[2];
1060 u8 fccs;
1061 u8 res5[3];
1062 u8 ftirr_phy[4];
1063 } ccsr_cpm_fcc2_t;
1064
1065 /* FCC3 */
1066 typedef struct ccsr_cpm_fcc3 {
1067 u32 gfmr;
1068 u32 fpsmr;
1069 u16 ftodr;
1070 u8 res1[2];
1071 u16 fdsr;
1072 u8 res2[2];
1073 u16 fcce;
1074 u8 res3[2];
1075 u16 fccm;
1076 u8 res4[2];
1077 u8 fccs;
1078 u8 res5[3];
1079 u8 res[36];
1080 } ccsr_cpm_fcc3_t;
1081
1082 /* FCC1 extended */
1083 typedef struct ccsr_cpm_fcc1_ext {
1084 u32 firper;
1085 u32 firer;
1086 u32 firsr_h;
1087 u32 firsr_l;
1088 u8 gfemr;
1089 u8 res[15];
1090
1091 } ccsr_cpm_fcc1_ext_t;
1092
1093 /* FCC2 extended */
1094 typedef struct ccsr_cpm_fcc2_ext {
1095 u32 firper;
1096 u32 firer;
1097 u32 firsr_h;
1098 u32 firsr_l;
1099 u8 gfemr;
1100 u8 res[31];
1101 } ccsr_cpm_fcc2_ext_t;
1102
1103 /* FCC3 extended */
1104 typedef struct ccsr_cpm_fcc3_ext {
1105 u8 gfemr;
1106 u8 res[47];
1107 } ccsr_cpm_fcc3_ext_t;
1108
1109 /* TC layers */
1110 typedef struct ccsr_cpm_tmp1 {
1111 u8 res[496];
1112 } ccsr_cpm_tmp1_t;
1113
1114 /* BRGs:5,6,7,8 */
1115 typedef struct ccsr_cpm_brg2 {
1116 u32 brgc5;
1117 u32 brgc6;
1118 u32 brgc7;
1119 u32 brgc8;
1120 u8 res[608];
1121 } ccsr_cpm_brg2_t;
1122
1123 /* I2C */
1124 typedef struct ccsr_cpm_i2c {
1125 u8 i2mod;
1126 u8 res1[3];
1127 u8 i2add;
1128 u8 res2[3];
1129 u8 i2brg;
1130 u8 res3[3];
1131 u8 i2com;
1132 u8 res4[3];
1133 u8 i2cer;
1134 u8 res5[3];
1135 u8 i2cmr;
1136 u8 res6[331];
1137 } ccsr_cpm_i2c_t;
1138
1139 /* CPM core */
1140 typedef struct ccsr_cpm_cp {
1141 u32 cpcr;
1142 u32 rccr;
1143 u8 res1[14];
1144 u16 rter;
1145 u8 res2[2];
1146 u16 rtmr;
1147 u16 rtscr;
1148 u8 res3[2];
1149 u32 rtsr;
1150 u8 res4[12];
1151 } ccsr_cpm_cp_t;
1152
1153 /* BRGs:1,2,3,4 */
1154 typedef struct ccsr_cpm_brg1 {
1155 u32 brgc1;
1156 u32 brgc2;
1157 u32 brgc3;
1158 u32 brgc4;
1159 } ccsr_cpm_brg1_t;
1160
1161 /* SCC1-SCC4 */
1162 typedef struct ccsr_cpm_scc {
1163 u32 gsmrl;
1164 u32 gsmrh;
1165 u16 psmr;
1166 u8 res1[2];
1167 u16 todr;
1168 u16 dsr;
1169 u16 scce;
1170 u8 res2[2];
1171 u16 sccm;
1172 u8 res3;
1173 u8 sccs;
1174 u8 res4[8];
1175 } ccsr_cpm_scc_t;
1176
1177 typedef struct ccsr_cpm_tmp2 {
1178 u8 res[32];
1179 } ccsr_cpm_tmp2_t;
1180
1181 /* SPI */
1182 typedef struct ccsr_cpm_spi {
1183 u16 spmode;
1184 u8 res1[4];
1185 u8 spie;
1186 u8 res2[3];
1187 u8 spim;
1188 u8 res3[2];
1189 u8 spcom;
1190 u8 res4[82];
1191 } ccsr_cpm_spi_t;
1192
1193 /* CPM MUX */
1194 typedef struct ccsr_cpm_mux {
1195 u8 cmxsi1cr;
1196 u8 res1;
1197 u8 cmxsi2cr;
1198 u8 res2;
1199 u32 cmxfcr;
1200 u32 cmxscr;
1201 u8 res3[2];
1202 u16 cmxuar;
1203 u8 res4[16];
1204 } ccsr_cpm_mux_t;
1205
1206 /* SI,MCC,etc */
1207 typedef struct ccsr_cpm_tmp3 {
1208 u8 res[58592];
1209 } ccsr_cpm_tmp3_t;
1210
1211 typedef struct ccsr_cpm_iram {
1212 u32 iram[8192];
1213 u8 res[98304];
1214 } ccsr_cpm_iram_t;
1215
1216 typedef struct ccsr_cpm {
1217 /* Some references are into the unique & known dpram spaces,
1218 * others are from the generic base.
1219 */
1220 #define im_dprambase im_dpram1
1221 u8 im_dpram1[16*1024];
1222 u8 res1[16*1024];
1223 u8 im_dpram2[16*1024];
1224 u8 res2[16*1024];
1225 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1226 ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */
1227 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1228 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1229 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
1230 ccsr_cpm_fcc1_t im_cpm_fcc1;
1231 ccsr_cpm_fcc2_t im_cpm_fcc2;
1232 ccsr_cpm_fcc3_t im_cpm_fcc3;
1233 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1234 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1235 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1236 ccsr_cpm_tmp1_t im_cpm_tmp1;
1237 ccsr_cpm_brg2_t im_cpm_brg2;
1238 ccsr_cpm_i2c_t im_cpm_i2c;
1239 ccsr_cpm_cp_t im_cpm_cp;
1240 ccsr_cpm_brg1_t im_cpm_brg1;
1241 ccsr_cpm_scc_t im_cpm_scc[4];
1242 ccsr_cpm_tmp2_t im_cpm_tmp2;
1243 ccsr_cpm_spi_t im_cpm_spi;
1244 ccsr_cpm_mux_t im_cpm_mux;
1245 ccsr_cpm_tmp3_t im_cpm_tmp3;
1246 ccsr_cpm_iram_t im_cpm_iram;
1247 } ccsr_cpm_t;
1248 #endif
1249
1250 #ifdef CONFIG_SYS_SRIO
1251 /* Architectural regsiters */
1252 struct rio_arch {
1253 u32 didcar; /* Device Identity CAR */
1254 u32 dicar; /* Device Information CAR */
1255 u32 aidcar; /* Assembly Identity CAR */
1256 u32 aicar; /* Assembly Information CAR */
1257 u32 pefcar; /* Processing Element Features CAR */
1258 u8 res0[4];
1259 u32 socar; /* Source Operations CAR */
1260 u32 docar; /* Destination Operations CAR */
1261 u8 res1[32];
1262 u32 mcsr; /* Mailbox CSR */
1263 u32 pwdcsr; /* Port-Write and Doorbell CSR */
1264 u8 res2[4];
1265 u32 pellccsr; /* Processing Element Logic Layer CCSR */
1266 u8 res3[12];
1267 u32 lcsbacsr; /* Local Configuration Space BACSR */
1268 u32 bdidcsr; /* Base Device ID CSR */
1269 u8 res4[4];
1270 u32 hbdidlcsr; /* Host Base Device ID Lock CSR */
1271 u32 ctcsr; /* Component Tag CSR */
1272 };
1273
1274 /* Extended Features Space: 1x/4x LP-Serial Port registers */
1275 struct rio_lp_serial_port {
1276 u32 plmreqcsr; /* Port Link Maintenance Request CSR */
1277 u32 plmrespcsr; /* Port Link Maintenance Response CS */
1278 u32 plascsr; /* Port Local Ackid Status CSR */
1279 u8 res0[12];
1280 u32 pescsr; /* Port Error and Status CSR */
1281 u32 pccsr; /* Port Control CSR */
1282 };
1283
1284 /* Extended Features Space: 1x/4x LP-Serial registers */
1285 struct rio_lp_serial {
1286 u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */
1287 u8 res0[28];
1288 u32 pltoccsr; /* Port Link Time-out CCSR */
1289 u32 prtoccsr; /* Port Response Time-out CCSR */
1290 u8 res1[20];
1291 u32 pgccsr; /* Port General CSR */
1292 struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1293 };
1294
1295 /* Logical error reporting registers */
1296 struct rio_logical_err {
1297 u32 erbh; /* Error Reporting Block Header Register */
1298 u8 res0[4];
1299 u32 ltledcsr; /* Logical/Transport layer error DCSR */
1300 u32 ltleecsr; /* Logical/Transport layer error ECSR */
1301 u8 res1[4];
1302 u32 ltlaccsr; /* Logical/Transport layer ACCSR */
1303 u32 ltldidccsr; /* Logical/Transport layer DID CCSR */
1304 u32 ltlcccsr; /* Logical/Transport layer control CCSR */
1305 };
1306
1307 /* Physical error reporting port registers */
1308 struct rio_phys_err_port {
1309 u32 edcsr; /* Port error detect CSR */
1310 u32 erecsr; /* Port error rate enable CSR */
1311 u32 ecacsr; /* Port error capture attributes CSR */
1312 u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */
1313 u32 peccsr[3]; /* Port error capture CSR */
1314 u8 res0[12];
1315 u32 ercsr; /* Port error rate CSR */
1316 u32 ertcsr; /* Port error rate threshold CSR */
1317 u8 res1[16];
1318 };
1319
1320 /* Physical error reporting registers */
1321 struct rio_phys_err {
1322 struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1323 };
1324
1325 /* Implementation Space: General Port-Common */
1326 struct rio_impl_common {
1327 u8 res0[4];
1328 u32 llcr; /* Logical Layer Configuration Register */
1329 u8 res1[8];
1330 u32 epwisr; /* Error / Port-Write Interrupt SR */
1331 u8 res2[12];
1332 u32 lretcr; /* Logical Retry Error Threshold CR */
1333 u8 res3[92];
1334 u32 pretcr; /* Physical Retry Erorr Threshold CR */
1335 u8 res4[124];
1336 };
1337
1338 /* Implementation Space: Port Specific */
1339 struct rio_impl_port_spec {
1340 u32 adidcsr; /* Port Alt. Device ID CSR */
1341 u8 res0[28];
1342 u32 ptaacr; /* Port Pass-Through/Accept-All CR */
1343 u32 lopttlcr;
1344 u8 res1[8];
1345 u32 iecsr; /* Port Implementation Error CSR */
1346 u8 res2[12];
1347 u32 pcr; /* Port Phsyical Configuration Register */
1348 u8 res3[20];
1349 u32 slcsr; /* Port Serial Link CSR */
1350 u8 res4[4];
1351 u32 sleicr; /* Port Serial Link Error Injection */
1352 u32 a0txcr; /* Port Arbitration 0 Tx CR */
1353 u32 a1txcr; /* Port Arbitration 1 Tx CR */
1354 u32 a2txcr; /* Port Arbitration 2 Tx CR */
1355 u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */
1356 u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */
1357 };
1358
1359 /* Implementation Space: register */
1360 struct rio_implement {
1361 struct rio_impl_common com;
1362 struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1363 };
1364
1365 /* Revision Control Register */
1366 struct rio_rev_ctrl {
1367 u32 ipbrr[2]; /* IP Block Revision Register */
1368 };
1369
1370 struct rio_atmu_row {
1371 u32 rowtar; /* RapidIO Outbound Window TAR */
1372 u32 rowtear; /* RapidIO Outbound Window TEAR */
1373 u32 rowbar;
1374 u8 res0[4];
1375 u32 rowar; /* RapidIO Outbound Attributes Register */
1376 u32 rowsr[3]; /* Port RapidIO outbound window segment register */
1377 };
1378
1379 struct rio_atmu_riw {
1380 u32 riwtar; /* RapidIO Inbound Window Translation AR */
1381 u8 res0[4];
1382 u32 riwbar; /* RapidIO Inbound Window Base AR */
1383 u8 res1[4];
1384 u32 riwar; /* RapidIO Inbound Attributes Register */
1385 u8 res2[12];
1386 };
1387
1388 /* ATMU window registers */
1389 struct rio_atmu_win {
1390 struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
1391 u8 res0[64];
1392 struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
1393 };
1394
1395 struct rio_atmu {
1396 struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1397 };
1398
1399 #ifdef CONFIG_SYS_FSL_RMU
1400 struct rio_msg {
1401 u32 omr; /* Outbound Mode Register */
1402 u32 osr; /* Outbound Status Register */
1403 u32 eodqdpar; /* Extended Outbound DQ DPAR */
1404 u32 odqdpar; /* Outbound Descriptor Queue DPAR */
1405 u32 eosar; /* Extended Outbound Unit Source AR */
1406 u32 osar; /* Outbound Unit Source AR */
1407 u32 odpr; /* Outbound Destination Port Register */
1408 u32 odatr; /* Outbound Destination Attributes Register */
1409 u32 odcr; /* Outbound Doubleword Count Register */
1410 u32 eodqepar; /* Extended Outbound DQ EPAR */
1411 u32 odqepar; /* Outbound Descriptor Queue EPAR */
1412 u32 oretr; /* Outbound Retry Error Threshold Register */
1413 u32 omgr; /* Outbound Multicast Group Register */
1414 u32 omlr; /* Outbound Multicast List Register */
1415 u8 res0[40];
1416 u32 imr; /* Outbound Mode Register */
1417 u32 isr; /* Inbound Status Register */
1418 u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */
1419 u32 idqdpar; /* Inbound Descriptor Queue DPAR */
1420 u32 eifqepar; /* Extended Inbound Frame Queue EPAR */
1421 u32 ifqepar; /* Inbound Frame Queue EPAR */
1422 u32 imirir; /* Inbound Maximum Interrutp RIR */
1423 u8 res1[4];
1424 u32 eihqepar; /* Extended inbound message header queue EPAR */
1425 u32 ihqepar; /* Inbound message header queue EPAR */
1426 u8 res2[120];
1427 };
1428
1429 struct rio_dbell {
1430 u32 odmr; /* Outbound Doorbell Mode Register */
1431 u32 odsr; /* Outbound Doorbell Status Register */
1432 u8 res0[16];
1433 u32 oddpr; /* Outbound Doorbell Destination Port */
1434 u32 oddatr; /* Outbound Doorbell Destination AR */
1435 u8 res1[12];
1436 u32 oddretr; /* Outbound Doorbell Retry Threshold CR */
1437 u8 res2[48];
1438 u32 idmr; /* Inbound Doorbell Mode Register */
1439 u32 idsr; /* Inbound Doorbell Status Register */
1440 u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */
1441 u32 iqdpar; /* Inbound Doorbell Queue DPAR */
1442 u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */
1443 u32 idqepar; /* Inbound Doorbell Queue EPAR */
1444 u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */
1445 };
1446
1447 struct rio_pw {
1448 u32 pwmr; /* Port-Write Mode Register */
1449 u32 pwsr; /* Port-Write Status Register */
1450 u32 epwqbar; /* Extended Port-Write Queue BAR */
1451 u32 pwqbar; /* Port-Write Queue Base Address Register */
1452 };
1453 #endif
1454
1455 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
1456 struct rio_liodn {
1457 u32 plbr;
1458 u8 res0[28];
1459 u32 plaor;
1460 u8 res1[12];
1461 u32 pludr;
1462 u32 plldr;
1463 u8 res2[456];
1464 };
1465 #endif
1466
1467 /* RapidIO Registers */
1468 struct ccsr_rio {
1469 struct rio_arch arch;
1470 u8 res0[144];
1471 struct rio_lp_serial lp_serial;
1472 u8 res1[1152];
1473 struct rio_logical_err logical_err;
1474 u8 res2[32];
1475 struct rio_phys_err phys_err;
1476 u8 res3[63808];
1477 struct rio_implement impl;
1478 u8 res4[2552];
1479 struct rio_rev_ctrl rev;
1480 struct rio_atmu atmu;
1481 #ifdef CONFIG_SYS_FSL_RMU
1482 u8 res5[8192];
1483 struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
1484 u8 res6[512];
1485 struct rio_dbell dbell;
1486 u8 res7[100];
1487 struct rio_pw pw;
1488 #endif
1489 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
1490 u8 res5[8192];
1491 struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1492 #endif
1493 };
1494 #endif
1495
1496 /* Quick Engine Block Pin Muxing Registers */
1497 typedef struct par_io {
1498 u32 cpodr;
1499 u32 cpdat;
1500 u32 cpdir1;
1501 u32 cpdir2;
1502 u32 cppar1;
1503 u32 cppar2;
1504 u8 res[8];
1505 } par_io_t;
1506
1507 #ifdef CONFIG_SYS_FSL_CPC
1508 /*
1509 * Define a single offset that is the start of all the CPC register
1510 * blocks - if there is more than one CPC, we expect these to be
1511 * contiguous 4k regions
1512 */
1513
1514 typedef struct cpc_corenet {
1515 u32 cpccsr0; /* Config/status reg */
1516 u32 res1;
1517 u32 cpccfg0; /* Configuration register */
1518 u32 res2;
1519 u32 cpcewcr0; /* External Write reg 0 */
1520 u32 cpcewabr0; /* External write base reg 0 */
1521 u32 res3[2];
1522 u32 cpcewcr1; /* External Write reg 1 */
1523 u32 cpcewabr1; /* External write base reg 1 */
1524 u32 res4[54];
1525 u32 cpcsrcr1; /* SRAM control reg 1 */
1526 u32 cpcsrcr0; /* SRAM control reg 0 */
1527 u32 res5[62];
1528 struct {
1529 u32 id; /* partition ID */
1530 u32 res;
1531 u32 alloc; /* partition allocation */
1532 u32 way; /* partition way */
1533 } partition_regs[16];
1534 u32 res6[704];
1535 u32 cpcerrinjhi; /* Error injection high */
1536 u32 cpcerrinjlo; /* Error injection lo */
1537 u32 cpcerrinjctl; /* Error injection control */
1538 u32 res7[5];
1539 u32 cpccaptdatahi; /* capture data high */
1540 u32 cpccaptdatalo; /* capture data low */
1541 u32 cpcaptecc; /* capture ECC */
1542 u32 res8[5];
1543 u32 cpcerrdet; /* error detect */
1544 u32 cpcerrdis; /* error disable */
1545 u32 cpcerrinten; /* errir interrupt enable */
1546 u32 cpcerrattr; /* error attribute */
1547 u32 cpcerreaddr; /* error extended address */
1548 u32 cpcerraddr; /* error address */
1549 u32 cpcerrctl; /* error control */
1550 u32 res9[41]; /* pad out to 4k */
1551 u32 cpchdbcr0; /* hardware debug control register 0 */
1552 u32 res10[63]; /* pad out to 4k */
1553 } cpc_corenet_t;
1554
1555 #define CPC_CSR0_CE 0x80000000 /* Cache Enable */
1556 #define CPC_CSR0_PE 0x40000000 /* Enable ECC */
1557 #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
1558 #define CPC_CSR0_WT 0x00080000 /* Write-through mode */
1559 #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
1560 #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
1561 #define CPC_CFG0_SZ_MASK 0x00003fff
1562 #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
1563 #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1564 #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1565 #define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1566 #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
1567 & CPC_SRCR1_SRBARU_MASK)
1568 #define CPC_SRCR0_SRBARL_MASK 0xffff8000
1569 #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
1570 #define CPC_SRCR0_INTLVEN 0x00000100
1571 #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1572 #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1573 #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1574 #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1575 #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1576 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1577 #define CPC_SRCR0_SRAMEN 0x00000001
1578 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
1579 #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
1580 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
1581 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
1582 #define CPC_HDBCR0_SPLRU_LEVEL_EN 0x001e0000
1583 #endif /* CONFIG_SYS_FSL_CPC */
1584
1585 /* Global Utilities Block */
1586 #ifdef CONFIG_FSL_CORENET
1587 typedef struct ccsr_gur {
1588 u32 porsr1; /* POR status 1 */
1589 u32 porsr2; /* POR status 2 */
1590 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
1591 #define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15
1592 #define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1
1593 #define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1
1594 #define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0
1595 #endif
1596 u8 res_008[0x20-0x8];
1597 u32 gpporcr1; /* General-purpose POR configuration */
1598 u32 gpporcr2; /* General-purpose POR configuration 2 */
1599 u32 dcfg_fusesr; /* Fuse status register */
1600 #define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
1601 #define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
1602 #define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
1603 #define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
1604 u8 res_02c[0x70-0x2c];
1605 u32 devdisr; /* Device disable control */
1606 u32 devdisr2; /* Device disable control 2 */
1607 u32 devdisr3; /* Device disable control 3 */
1608 u32 devdisr4; /* Device disable control 4 */
1609 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1610 u32 devdisr5; /* Device disable control 5 */
1611 #define FSL_CORENET_DEVDISR_PBL 0x80000000
1612 #define FSL_CORENET_DEVDISR_PMAN 0x40000000
1613 #define FSL_CORENET_DEVDISR_ESDHC 0x20000000
1614 #define FSL_CORENET_DEVDISR_DMA1 0x00800000
1615 #define FSL_CORENET_DEVDISR_DMA2 0x00400000
1616 #define FSL_CORENET_DEVDISR_USB1 0x00080000
1617 #define FSL_CORENET_DEVDISR_USB2 0x00040000
1618 #define FSL_CORENET_DEVDISR_SATA1 0x00008000
1619 #define FSL_CORENET_DEVDISR_SATA2 0x00004000
1620 #define FSL_CORENET_DEVDISR_PME 0x00000800
1621 #define FSL_CORENET_DEVDISR_SEC 0x00000200
1622 #define FSL_CORENET_DEVDISR_RMU 0x00000080
1623 #define FSL_CORENET_DEVDISR_DCE 0x00000040
1624 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
1625 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
1626 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
1627 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
1628 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
1629 #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
1630 #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
1631 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
1632 #ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
1633 #define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000
1634 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000
1635 #else
1636 #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
1637 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
1638 #define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
1639 #define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
1640 #endif
1641 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
1642 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
1643 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
1644 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
1645 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
1646 #define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
1647 #define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
1648 #define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
1649 #define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
1650 #define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
1651 #define FSL_CORENET_DEVDISR2_FM1 0x00000080
1652 #define FSL_CORENET_DEVDISR2_FM2 0x00000040
1653 #define FSL_CORENET_DEVDISR2_CPRI 0x00000008
1654 #define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
1655 #define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
1656 #define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
1657 #define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
1658 #define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
1659 #define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
1660 #define FSL_CORENET_DEVDISR3_QMAN 0x00080000
1661 #define FSL_CORENET_DEVDISR3_BMAN 0x00040000
1662 #define FSL_CORENET_DEVDISR3_LA1 0x00008000
1663 #define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
1664 #define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
1665 #define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
1666 #define FSL_CORENET_DEVDISR4_I2C1 0x80000000
1667 #define FSL_CORENET_DEVDISR4_I2C2 0x40000000
1668 #define FSL_CORENET_DEVDISR4_DUART1 0x20000000
1669 #define FSL_CORENET_DEVDISR4_DUART2 0x10000000
1670 #define FSL_CORENET_DEVDISR4_ESPI 0x08000000
1671 #define FSL_CORENET_DEVDISR5_DDR1 0x80000000
1672 #define FSL_CORENET_DEVDISR5_DDR2 0x40000000
1673 #define FSL_CORENET_DEVDISR5_DDR3 0x20000000
1674 #define FSL_CORENET_DEVDISR5_CPC1 0x08000000
1675 #define FSL_CORENET_DEVDISR5_CPC2 0x04000000
1676 #define FSL_CORENET_DEVDISR5_CPC3 0x02000000
1677 #define FSL_CORENET_DEVDISR5_IFC 0x00800000
1678 #define FSL_CORENET_DEVDISR5_GPIO 0x00400000
1679 #define FSL_CORENET_DEVDISR5_DBG 0x00200000
1680 #define FSL_CORENET_DEVDISR5_NAL 0x00100000
1681 #define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
1682 #define FSL_CORENET_NUM_DEVDISR 5
1683 #else
1684 #define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1685 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1686 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000
1687 #define FSL_CORENET_DEVDISR_PCIE4 0x10000000
1688 #define FSL_CORENET_DEVDISR_RMU 0x08000000
1689 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1690 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1691 #define FSL_CORENET_DEVDISR_DMA1 0x00400000
1692 #define FSL_CORENET_DEVDISR_DMA2 0x00200000
1693 #define FSL_CORENET_DEVDISR_DDR1 0x00100000
1694 #define FSL_CORENET_DEVDISR_DDR2 0x00080000
1695 #define FSL_CORENET_DEVDISR_DBG 0x00010000
1696 #define FSL_CORENET_DEVDISR_NAL 0x00008000
1697 #define FSL_CORENET_DEVDISR_SATA1 0x00004000
1698 #define FSL_CORENET_DEVDISR_SATA2 0x00002000
1699 #define FSL_CORENET_DEVDISR_ELBC 0x00001000
1700 #define FSL_CORENET_DEVDISR_USB1 0x00000800
1701 #define FSL_CORENET_DEVDISR_USB2 0x00000400
1702 #define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1703 #define FSL_CORENET_DEVDISR_GPIO 0x00000080
1704 #define FSL_CORENET_DEVDISR_ESPI 0x00000040
1705 #define FSL_CORENET_DEVDISR_I2C1 0x00000020
1706 #define FSL_CORENET_DEVDISR_I2C2 0x00000010
1707 #define FSL_CORENET_DEVDISR_DUART1 0x00000002
1708 #define FSL_CORENET_DEVDISR_DUART2 0x00000001
1709 #define FSL_CORENET_DEVDISR2_PME 0x80000000
1710 #define FSL_CORENET_DEVDISR2_SEC 0x40000000
1711 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1712 #define FSL_CORENET_DEVDISR2_FM1 0x02000000
1713 #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1714 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1715 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1716 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1717 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
1718 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
1719 #define FSL_CORENET_DEVDISR2_FM2 0x00020000
1720 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1721 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1722 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1723 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1724 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
1725 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
1726 #define FSL_CORENET_NUM_DEVDISR 2
1727 u32 powmgtcsr; /* Power management status & control */
1728 #endif
1729 u8 res8[12];
1730 u32 coredisru; /* uppper portion for support of 64 cores */
1731 u32 coredisrl; /* lower portion for support of 64 cores */
1732 u8 res9[8];
1733 u32 pvr; /* Processor version */
1734 u32 svr; /* System version */
1735 u8 res10[8];
1736 u32 rstcr; /* Reset control */
1737 u32 rstrqpblsr; /* Reset request preboot loader status */
1738 u8 res11[8];
1739 u32 rstrqmr1; /* Reset request mask */
1740 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1741 #define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800
1742 #endif
1743 u8 res12[4];
1744 u32 rstrqsr1; /* Reset request status */
1745 u8 res13[4];
1746 u8 res14[4];
1747 u32 rstrqwdtmrl; /* Reset request WDT mask */
1748 u8 res15[4];
1749 u32 rstrqwdtsrl; /* Reset request WDT status */
1750 u8 res16[4];
1751 u32 brrl; /* Boot release */
1752 u8 res17[24];
1753 u32 rcwsr[16]; /* Reset control word status */
1754 #define RCW_SB_EN_REG_INDEX 7
1755 #define RCW_SB_EN_MASK 0x00200000
1756
1757 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1758 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
1759 /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
1760 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
1761 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
1762 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
1763 defined(CONFIG_PPC_T4080)
1764 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
1765 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
1766 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1767 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1768 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
1769 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
1770 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
1771 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
1772 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1773 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
1774 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
1775 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
1776 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1777 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1778 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1779 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
1780 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
1781 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1782 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1783 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1784 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1785 #define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
1786 #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000
1787 #define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000
1788 #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
1789 #define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */
1790 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1791 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1792 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000
1793 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
1794 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
1795 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000
1796 #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
1797 #define PXCKEN_MASK 0x80000000
1798 #define PXCK_MASK 0x00FF0000
1799 #define PXCK_BITS_START 16
1800 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) || \
1801 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
1802 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
1803 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
1804 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1805 #define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
1806 #define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000
1807 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000
1808 #define FSL_CORENET_RCWSR13_EC2 0x0c000000
1809 #define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000
1810 #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
1811 #define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00
1812 #define PXCKEN_MASK 0x80000000
1813 #define PXCK_MASK 0x00FF0000
1814 #define PXCK_BITS_START 16
1815 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
1816 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1817 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1818 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1819 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1820 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1821 #endif
1822 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
1823 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
1824 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
1825 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
1826 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
1827 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
1828 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
1829 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
1830 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
1831 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011
1832 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1
1833
1834 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1835 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
1836 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
1837 #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
1838 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1839 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
1840 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
1841 #define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
1842 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1843 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
1844 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
1845 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1846
1847 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1848 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1849 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
1850 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
1851 #ifdef CONFIG_ARCH_P4080
1852 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1853 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
1854 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
1855 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1856 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1857 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
1858 #endif
1859 #if defined(CONFIG_ARCH_P2041) || \
1860 defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
1861 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
1862 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
1863 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
1864 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1865 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
1866 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
1867 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
1868 #endif
1869 #if defined(CONFIG_ARCH_P5040)
1870 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
1871 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
1872 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
1873 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1874 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
1875 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
1876 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
1877 #endif
1878 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
1879 defined(CONFIG_PPC_T4080)
1880 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1881 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
1882 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
1883 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1884 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1885 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
1886 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1887 #endif
1888 #if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
1889 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1890 #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
1891 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
1892 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1893 #define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
1894 #define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
1895 #define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
1896 #endif
1897 u8 res18[192];
1898 u32 scratchrw[4]; /* Scratch Read/Write */
1899 u8 res19[240];
1900 u32 scratchw1r[4]; /* Scratch Read (Write once) */
1901 u8 res20[240];
1902 u32 scrtsr[8]; /* Core reset status */
1903 u8 res21[224];
1904 u32 pex1liodnr; /* PCI Express 1 LIODN */
1905 u32 pex2liodnr; /* PCI Express 2 LIODN */
1906 u32 pex3liodnr; /* PCI Express 3 LIODN */
1907 u32 pex4liodnr; /* PCI Express 4 LIODN */
1908 u32 rio1liodnr; /* RIO 1 LIODN */
1909 u32 rio2liodnr; /* RIO 2 LIODN */
1910 u32 rio3liodnr; /* RIO 3 LIODN */
1911 u32 rio4liodnr; /* RIO 4 LIODN */
1912 u32 usb1liodnr; /* USB 1 LIODN */
1913 u32 usb2liodnr; /* USB 2 LIODN */
1914 u32 usb3liodnr; /* USB 3 LIODN */
1915 u32 usb4liodnr; /* USB 4 LIODN */
1916 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */
1917 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
1918 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
1919 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
1920 u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
1921 u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
1922 u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
1923 u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
1924 u32 sata1liodnr; /* SATA 1 LIODN */
1925 u32 sata2liodnr; /* SATA 2 LIODN */
1926 u32 sata3liodnr; /* SATA 3 LIODN */
1927 u32 sata4liodnr; /* SATA 4 LIODN */
1928 u8 res22[20];
1929 u32 tdmliodnr; /* TDM LIODN */
1930 u32 qeliodnr; /* QE LIODN */
1931 u8 res_57c[4];
1932 u32 dma1liodnr; /* DMA 1 LIODN */
1933 u32 dma2liodnr; /* DMA 2 LIODN */
1934 u32 dma3liodnr; /* DMA 3 LIODN */
1935 u32 dma4liodnr; /* DMA 4 LIODN */
1936 u8 res23[48];
1937 u8 res24[64];
1938 u32 pblsr; /* Preboot loader status */
1939 u32 pamubypenr; /* PAMU bypass enable */
1940 u32 dmacr1; /* DMA control */
1941 u8 res25[4];
1942 u32 gensr1; /* General status */
1943 u8 res26[12];
1944 u32 gencr1; /* General control */
1945 u8 res27[12];
1946 u8 res28[4];
1947 u32 cgensrl; /* Core general status */
1948 u8 res29[8];
1949 u8 res30[4];
1950 u32 cgencrl; /* Core general control */
1951 u8 res31[184];
1952 u32 sriopstecr; /* SRIO prescaler timer enable control */
1953 u32 dcsrcr; /* DCSR Control register */
1954 u8 res31a[56];
1955 u32 tp_ityp[64]; /* Topology Initiator Type Register */
1956 struct {
1957 u32 upper;
1958 u32 lower;
1959 } tp_cluster[16]; /* Core Cluster n Topology Register */
1960 u8 res32[1344];
1961 u32 pmuxcr; /* Pin multiplexing control */
1962 u8 res33[60];
1963 u32 iovselsr; /* I/O voltage selection status */
1964 u8 res34[28];
1965 u32 ddrclkdr; /* DDR clock disable */
1966 u8 res35;
1967 u32 elbcclkdr; /* eLBC clock disable */
1968 u8 res36[20];
1969 u32 sdhcpcr; /* eSDHC polarity configuration */
1970 u8 res37[380];
1971 } ccsr_gur_t;
1972
1973 #define TP_ITYP_AV 0x00000001 /* Initiator available */
1974 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
1975 #define TP_ITYP_TYPE_OTHER 0x0
1976 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
1977 #define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */
1978 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
1979 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
1980 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
1981
1982 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
1983 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
1984 #define TP_INIT_PER_CLUSTER 4
1985
1986 #define FSL_CORENET_DCSR_SZ_MASK 0x00000003
1987 #define FSL_CORENET_DCSR_SZ_4M 0x0
1988 #define FSL_CORENET_DCSR_SZ_1G 0x3
1989
1990 /*
1991 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
1992 * everything after has RMan thus msg unit LIODN is used for maintenance
1993 */
1994 #define rmuliodnr rio1maintliodnr
1995
1996 typedef struct ccsr_clk {
1997 struct {
1998 u32 clkcncsr; /* core cluster n clock control status */
1999 u8 res_004[0x0c];
2000 u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
2001 u8 res_014[0x0c];
2002 } clkcsr[12];
2003 u8 res_100[0x680]; /* 0x100 */
2004 struct {
2005 u32 pllcngsr;
2006 u8 res10[0x1c];
2007 } pllcgsr[12];
2008 u8 res21[0x280];
2009 u32 pllpgsr; /* 0xc00 Platform PLL General Status */
2010 u8 res16[0x1c];
2011 u32 plldgsr; /* 0xc20 DDR PLL General Status */
2012 u8 res17[0x3dc];
2013 } ccsr_clk_t;
2014
2015 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2016 typedef struct ccsr_rcpm {
2017 u8 res_00[12];
2018 u32 tph10sr0; /* Thread PH10 Status Register */
2019 u8 res_10[12];
2020 u32 tph10setr0; /* Thread PH10 Set Control Register */
2021 u8 res_20[12];
2022 u32 tph10clrr0; /* Thread PH10 Clear Control Register */
2023 u8 res_30[12];
2024 u32 tph10psr0; /* Thread PH10 Previous Status Register */
2025 u8 res_40[12];
2026 u32 twaitsr0; /* Thread Wait Status Register */
2027 u8 res_50[96];
2028 u32 pcph15sr; /* Physical Core PH15 Status Register */
2029 u32 pcph15setr; /* Physical Core PH15 Set Control Register */
2030 u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
2031 u32 pcph15psr; /* Physical Core PH15 Prev Status Register */
2032 u8 res_c0[16];
2033 u32 pcph20sr; /* Physical Core PH20 Status Register */
2034 u32 pcph20setr; /* Physical Core PH20 Set Control Register */
2035 u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
2036 u32 pcph20psr; /* Physical Core PH20 Prev Status Register */
2037 u32 pcpw20sr; /* Physical Core PW20 Status Register */
2038 u8 res_e0[12];
2039 u32 pcph30sr; /* Physical Core PH30 Status Register */
2040 u32 pcph30setr; /* Physical Core PH30 Set Control Register */
2041 u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
2042 u32 pcph30psr; /* Physical Core PH30 Prev Status Register */
2043 u8 res_100[32];
2044 u32 ippwrgatecr; /* IP Power Gating Control Register */
2045 u8 res_124[12];
2046 u32 powmgtcsr; /* Power Management Control & Status Reg */
2047 u8 res_134[12];
2048 u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
2049 u8 res_150[12];
2050 u32 tpmimr0; /* Thread PM Interrupt Mask Reg */
2051 u8 res_160[12];
2052 u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
2053 u8 res_170[12];
2054 u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
2055 u8 res_180[12];
2056 u32 tpmnmimr0; /* Thread PM NMI Mask Reg */
2057 u8 res_190[12];
2058 u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
2059 u32 pctbenr; /* Physical Core Time Base Enable Reg */
2060 u32 pctbclkselr; /* Physical Core Time Base Clock Select */
2061 u32 tbclkdivr; /* Time Base Clock Divider Register */
2062 u8 res_1ac[4];
2063 u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
2064 u32 clpcl10sr; /* Cluster PCL10 Status Register */
2065 u32 clpcl10setr; /* Cluster PCL30 Set Control Register */
2066 u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
2067 u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
2068 u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
2069 u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
2070 u32 cdpwroksetr; /* Core Domain Power OK Set Register */
2071 u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
2072 u32 cdpwrensr; /* Core Domain Power Enable Status Register */
2073 u32 cddslsr; /* Core Domain Deep Sleep Status Register */
2074 u8 res_1e8[8];
2075 u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
2076 u8 res_300[3568];
2077 } ccsr_rcpm_t;
2078
2079 #define ctbenrl pctbenr
2080
2081 #else
2082 typedef struct ccsr_rcpm {
2083 u8 res1[4];
2084 u32 cdozsrl; /* Core Doze Status */
2085 u8 res2[4];
2086 u32 cdozcrl; /* Core Doze Control */
2087 u8 res3[4];
2088 u32 cnapsrl; /* Core Nap Status */
2089 u8 res4[4];
2090 u32 cnapcrl; /* Core Nap Control */
2091 u8 res5[4];
2092 u32 cdozpsrl; /* Core Doze Previous Status */
2093 u8 res6[4];
2094 u32 cdozpcrl; /* Core Doze Previous Control */
2095 u8 res7[4];
2096 u32 cwaitsrl; /* Core Wait Status */
2097 u8 res8[8];
2098 u32 powmgtcsr; /* Power Mangement Control & Status */
2099 u8 res9[12];
2100 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */
2101 u8 res10[12];
2102 u8 res11[4];
2103 u32 cpmimrl; /* Core PM IRQ Masking */
2104 u8 res12[4];
2105 u32 cpmcimrl; /* Core PM Critical IRQ Masking */
2106 u8 res13[4];
2107 u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */
2108 u8 res14[4];
2109 u32 cpmnmimrl; /* Core PM NMI Masking */
2110 u8 res15[4];
2111 u32 ctbenrl; /* Core Time Base Enable */
2112 u8 res16[4];
2113 u32 ctbclkselrl; /* Core Time Base Clock Select */
2114 u8 res17[4];
2115 u32 ctbhltcrl; /* Core Time Base Halt Control */
2116 u8 res18[0xf68];
2117 } ccsr_rcpm_t;
2118 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2119
2120 #else
2121 typedef struct ccsr_gur {
2122 u32 porpllsr; /* POR PLL ratio status */
2123 #ifdef CONFIG_ARCH_MPC8536
2124 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
2125 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
2126 #elif defined(CONFIG_ARCH_C29X)
2127 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2128 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
2129 & MPC85xx_PORDEVSR2_DDR_SPD_0) \
2130 >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
2131 #else
2132 #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
2133 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2134 #else
2135 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
2136 #endif
2137 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
2138 #endif
2139 #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
2140 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
2141 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
2142 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
2143 u32 porbmsr; /* POR boot mode status */
2144 #define MPC85xx_PORBMSR_HA 0x00070000
2145 #define MPC85xx_PORBMSR_HA_SHIFT 16
2146 #define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
2147 #define PORBMSR_ROMLOC_SPI 0x6
2148 #define PORBMSR_ROMLOC_SDHC 0x7
2149 #define PORBMSR_ROMLOC_NAND_2K 0x9
2150 #define PORBMSR_ROMLOC_NOR 0xf
2151 u32 porimpscr; /* POR I/O impedance status & control */
2152 u32 pordevsr; /* POR I/O device status regsiter */
2153 #if defined(CONFIG_ARCH_P1023)
2154 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
2155 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
2156 #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
2157 #else
2158 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
2159 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
2160 #endif
2161 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
2162 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
2163 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
2164 #define MPC85xx_PORDEVSR_PCI1 0x00800000
2165 #if defined(CONFIG_ARCH_P1022)
2166 #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
2167 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
2168 #elif defined(CONFIG_ARCH_P1023)
2169 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2170 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2171 #else
2172 #if defined(CONFIG_ARCH_P1010)
2173 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2174 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2175 #elif defined(CONFIG_ARCH_BSC9132)
2176 #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
2177 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
2178 #elif defined(CONFIG_ARCH_C29X)
2179 #define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
2180 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2181 #else
2182 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000
2183 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
2184 #endif /* if defined(CONFIG_ARCH_P1010) */
2185 #endif
2186 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
2187 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
2188 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
2189 #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
2190 #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
2191 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
2192 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
2193 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
2194 u32 pordbgmsr; /* POR debug mode status */
2195 u32 pordevsr2; /* POR I/O device status 2 */
2196 #if defined(CONFIG_ARCH_C29X)
2197 #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
2198 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
2199 #endif
2200 #define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000
2201 /* The 8544 RM says this is bit 26, but it's really bit 24 */
2202 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
2203 u8 res1[8];
2204 u32 gpporcr; /* General-purpose POR configuration */
2205 u8 res2[12];
2206 #if defined(CONFIG_ARCH_MPC8536)
2207 u32 gencfgr; /* General Configuration Register */
2208 #define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
2209 #else
2210 u32 gpiocr; /* GPIO control */
2211 #endif
2212 u8 res3[12];
2213 #if defined(CONFIG_ARCH_MPC8569)
2214 u32 plppar1; /* Platform port pin assignment 1 */
2215 u32 plppar2; /* Platform port pin assignment 2 */
2216 u32 plpdir1; /* Platform port pin direction 1 */
2217 u32 plpdir2; /* Platform port pin direction 2 */
2218 #else
2219 u32 gpoutdr; /* General-purpose output data */
2220 u8 res4[12];
2221 #endif
2222 u32 gpindr; /* General-purpose input data */
2223 u8 res5[12];
2224 u32 pmuxcr; /* Alt. function signal multiplex control */
2225 #if defined(CONFIG_ARCH_P1010)
2226 #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
2227 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
2228 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
2229 #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
2230 #define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
2231 #define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
2232 #define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
2233 #define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
2234 #define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
2235 #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
2236 #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
2237 #define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
2238 #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
2239 #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
2240 #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
2241 #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
2242 #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
2243 #define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
2244 #define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
2245 #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
2246 #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
2247 #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
2248 #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
2249 #define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
2250 #define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
2251 #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
2252 #define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
2253 #define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
2254 #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
2255 #define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
2256 #define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
2257 #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
2258 #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
2259 #define MPC85xx_PMUXCR_LCLK_RES 0x00000040
2260 #define MPC85xx_PMUXCR_LCLK_USB 0x00000080
2261 #define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
2262 #define MPC85xx_PMUXCR_SPI_RES 0x00000030
2263 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
2264 #define MPC85xx_PMUXCR_CAN1_UART 0x00000004
2265 #define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
2266 #define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
2267 #define MPC85xx_PMUXCR_CAN2_UART 0x00000001
2268 #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
2269 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003
2270 #endif
2271 #if defined(CONFIG_ARCH_P1023)
2272 #define MPC85xx_PMUXCR_TSEC1_1 0x10000000
2273 #else
2274 #define MPC85xx_PMUXCR_SD_DATA 0x80000000
2275 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000
2276 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000
2277 #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
2278 #define MPC85xx_PMUXCR_TDM_ENA 0x00800000
2279 #define MPC85xx_PMUXCR_QE0 0x00008000
2280 #define MPC85xx_PMUXCR_QE1 0x00004000
2281 #define MPC85xx_PMUXCR_QE2 0x00002000
2282 #define MPC85xx_PMUXCR_QE3 0x00001000
2283 #define MPC85xx_PMUXCR_QE4 0x00000800
2284 #define MPC85xx_PMUXCR_QE5 0x00000400
2285 #define MPC85xx_PMUXCR_QE6 0x00000200
2286 #define MPC85xx_PMUXCR_QE7 0x00000100
2287 #define MPC85xx_PMUXCR_QE8 0x00000080
2288 #define MPC85xx_PMUXCR_QE9 0x00000040
2289 #define MPC85xx_PMUXCR_QE10 0x00000020
2290 #define MPC85xx_PMUXCR_QE11 0x00000010
2291 #define MPC85xx_PMUXCR_QE12 0x00000008
2292 #endif
2293 #if defined(CONFIG_ARCH_P1022)
2294 #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
2295 #define MPC85xx_PMUXCR_TDM 0x00014800
2296 #define MPC85xx_PMUXCR_SPI_MASK 0x00600000
2297 #define MPC85xx_PMUXCR_SPI 0x00000000
2298 #endif
2299 #if defined(CONFIG_ARCH_BSC9131)
2300 #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
2301 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
2302 #define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
2303 #define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
2304 #define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
2305 #define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
2306 #define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
2307 #define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
2308 #define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
2309 #define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
2310 #define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
2311 #define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
2312 #define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
2313 #define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
2314 #define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
2315 #define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
2316 #define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
2317 #define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
2318 #define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
2319 #define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
2320 #define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
2321 #define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
2322 #define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
2323 #define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
2324 #define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
2325 #define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
2326 #define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
2327 #define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
2328 #define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
2329 #define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
2330 #define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
2331 #define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
2332 #define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
2333 #define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
2334 #define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
2335 #define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
2336 #define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
2337 #define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
2338 #define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
2339 #define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
2340 #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
2341 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
2342 #endif
2343 #ifdef CONFIG_ARCH_BSC9132
2344 #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
2345 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
2346 #endif
2347 #if defined(CONFIG_ARCH_C29X)
2348 #define MPC85xx_PMUXCR_SPI_MASK 0x00000300
2349 #define MPC85xx_PMUXCR_SPI 0x00000000
2350 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
2351 #endif
2352 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
2353 #if defined(CONFIG_ARCH_P1010)
2354 #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
2355 #define MPC85xx_PMUXCR2_UART_TDM 0x80000000
2356 #define MPC85xx_PMUXCR2_UART_RES 0xC0000000
2357 #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
2358 #define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
2359 #define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
2360 #define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
2361 #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
2362 #define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
2363 #define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
2364 #define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
2365 #define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
2366 #define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
2367 #define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
2368 #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
2369 #define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
2370 #define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
2371 #define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
2372 #define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
2373 #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
2374 #define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
2375 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
2376 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
2377 #endif
2378 #if defined(CONFIG_ARCH_P1022)
2379 #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
2380 #define MPC85xx_PMUXCR2_USB 0x00150000
2381 #endif
2382 #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
2383 #if defined(CONFIG_ARCH_BSC9131)
2384 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
2385 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
2386 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
2387 #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
2388 #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
2389 #define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
2390 #define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
2391 #define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
2392 #define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
2393 #define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
2394 #define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
2395 #define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
2396 #define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
2397 #define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
2398 #define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
2399 #define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
2400 #define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
2401 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
2402 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
2403 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
2404 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
2405 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
2406 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
2407 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
2408 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
2409 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
2410 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
2411 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
2412 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
2413 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
2414 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
2415 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
2416 #define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
2417 #define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
2418 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
2419 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
2420 #define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
2421 #define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
2422 #define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
2423 #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
2424 #define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
2425 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
2426 #endif
2427 u32 pmuxcr3;
2428 #if defined(CONFIG_ARCH_BSC9131)
2429 #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
2430 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
2431 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
2432 #define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
2433 #define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
2434 #define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
2435 #define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
2436 #define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
2437 #define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
2438 #define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
2439 #define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
2440 #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
2441 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
2442 #define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
2443 #endif
2444 #ifdef CONFIG_ARCH_BSC9132
2445 #define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
2446 #define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
2447 #define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
2448 #define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
2449 #endif
2450 u32 pmuxcr4;
2451 #else
2452 u8 res6[8];
2453 #endif
2454 u32 devdisr; /* Device disable control */
2455 #define MPC85xx_DEVDISR_PCI1 0x80000000
2456 #define MPC85xx_DEVDISR_PCI2 0x40000000
2457 #define MPC85xx_DEVDISR_PCIE 0x20000000
2458 #define MPC85xx_DEVDISR_LBC 0x08000000
2459 #define MPC85xx_DEVDISR_PCIE2 0x04000000
2460 #define MPC85xx_DEVDISR_PCIE3 0x02000000
2461 #define MPC85xx_DEVDISR_SEC 0x01000000
2462 #define MPC85xx_DEVDISR_SRIO 0x00080000
2463 #define MPC85xx_DEVDISR_RMSG 0x00040000
2464 #define MPC85xx_DEVDISR_DDR 0x00010000
2465 #define MPC85xx_DEVDISR_CPU 0x00008000
2466 #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
2467 #define MPC85xx_DEVDISR_TB 0x00004000
2468 #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
2469 #define MPC85xx_DEVDISR_CPU1 0x00002000
2470 #define MPC85xx_DEVDISR_TB1 0x00001000
2471 #define MPC85xx_DEVDISR_DMA 0x00000400
2472 #define MPC85xx_DEVDISR_TSEC1 0x00000080
2473 #define MPC85xx_DEVDISR_TSEC2 0x00000040
2474 #define MPC85xx_DEVDISR_TSEC3 0x00000020
2475 #define MPC85xx_DEVDISR_TSEC4 0x00000010
2476 #define MPC85xx_DEVDISR_I2C 0x00000004
2477 #define MPC85xx_DEVDISR_DUART 0x00000002
2478 u8 res7[12];
2479 u32 powmgtcsr; /* Power management status & control */
2480 u8 res8[12];
2481 u32 mcpsumr; /* Machine check summary */
2482 u8 res9[12];
2483 u32 pvr; /* Processor version */
2484 u32 svr; /* System version */
2485 u8 res10[8];
2486 u32 rstcr; /* Reset control */
2487 #if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569)
2488 u8 res11a[76];
2489 par_io_t qe_par_io[7];
2490 u8 res11b[1600];
2491 #elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
2492 u8 res11a[12];
2493 u32 iovselsr;
2494 u8 res11b[60];
2495 par_io_t qe_par_io[3];
2496 u8 res11c[1496];
2497 #else
2498 u8 res11a[1868];
2499 #endif
2500 u32 clkdvdr; /* Clock Divide register */
2501 u8 res12[1532];
2502 u32 clkocr; /* Clock out select */
2503 u8 res13[12];
2504 u32 ddrdllcr; /* DDR DLL control */
2505 u8 res14[12];
2506 u32 lbcdllcr; /* LBC DLL control */
2507 #if defined(CONFIG_ARCH_BSC9131)
2508 u8 res15[12];
2509 u32 halt_req_mask;
2510 #define HALTED_TO_HALT_REQ_MASK_0 0x80000000
2511 u8 res18[232];
2512 #else
2513 u8 res15[248];
2514 #endif
2515 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
2516 u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
2517 u32 ddrioovcr; /* DDR IO Override Control */
2518 u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
2519 u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
2520 u8 res16[52];
2521 u32 sdhcdcr; /* SDHC debug control register */
2522 u8 res17[61592];
2523 } ccsr_gur_t;
2524 #endif
2525
2526 #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
2527
2528 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2529 #define MAX_SERDES 4
2530 #define SRDS_MAX_LANES 8
2531 #define SRDS_MAX_BANK 2
2532 typedef struct serdes_corenet {
2533 struct {
2534 u32 rstctl; /* Reset Control Register */
2535 #define SRDS_RSTCTL_RST 0x80000000
2536 #define SRDS_RSTCTL_RSTDONE 0x40000000
2537 #define SRDS_RSTCTL_RSTERR 0x20000000
2538 #define SRDS_RSTCTL_SWRST 0x10000000
2539 #define SRDS_RSTCTL_SDEN 0x00000020
2540 #define SRDS_RSTCTL_SDRST_B 0x00000040
2541 #define SRDS_RSTCTL_PLLRST_B 0x00000080
2542 #define SRDS_RSTCTL_RSTERR_SHIFT 29
2543 u32 pllcr0; /* PLL Control Register 0 */
2544 #define SRDS_PLLCR0_POFF 0x80000000
2545 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2546 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2547 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2548 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2549 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2550 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2551 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
2552 #define SRDS_PLLCR0_PLL_LCK 0x00800000
2553 #define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
2554 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
2555 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2556 #define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000
2557 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
2558 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
2559 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
2560 #define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000
2561 #define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000
2562 #define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000
2563 #define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
2564 #define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
2565 u32 pllcr1; /* PLL Control Register 1 */
2566 #define SRDS_PLLCR1_BCAP_EN 0x20000000
2567 #define SRDS_PLLCR1_BCAP_OVD 0x10000000
2568 #define SRDS_PLLCR1_PLL_FCAP 0x001F8000
2569 #define SRDS_PLLCR1_PLL_FCAP_SHIFT 15
2570 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2571 #define SRDS_PLLCR1_BYP_CAL 0x02000000
2572 u32 pllsr2; /* At 0x00c, PLL Status Register 2 */
2573 #define SRDS_PLLSR2_BCAP_EN 0x00800000
2574 #define SRDS_PLLSR2_BCAP_EN_SHIFT 23
2575 #define SRDS_PLLSR2_FCAP 0x003F0000
2576 #define SRDS_PLLSR2_FCAP_SHIFT 16
2577 #define SRDS_PLLSR2_DCBIAS 0x000F0000
2578 #define SRDS_PLLSR2_DCBIAS_SHIFT 16
2579 u32 pllcr3;
2580 u32 pllcr4;
2581 u8 res_18[0x20-0x18];
2582 } bank[2];
2583 u8 res_40[0x90-0x40];
2584 u32 srdstcalcr; /* 0x90 TX Calibration Control */
2585 u8 res_94[0xa0-0x94];
2586 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
2587 u8 res_a4[0xb0-0xa4];
2588 u32 srdsgr0; /* 0xb0 General Register 0 */
2589 u8 res_b4[0xe0-0xb4];
2590 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
2591 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
2592 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
2593 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
2594 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
2595 u8 res_f4[0x100-0xf4];
2596 struct {
2597 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
2598 u8 res_104[0x120-0x104];
2599 } srdslnpssr[8];
2600 u8 res_200[0x800-0x200];
2601 struct {
2602 u32 gcr0; /* 0x800 General Control Register 0 */
2603 u32 gcr1; /* 0x804 General Control Register 1 */
2604 u32 gcr2; /* 0x808 General Control Register 2 */
2605 u32 res_80c;
2606 u32 recr0; /* 0x810 Receive Equalization Control */
2607 u32 res_814;
2608 u32 tecr0; /* 0x818 Transmit Equalization Control */
2609 u32 res_81c;
2610 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
2611 u8 res_824[0x840-0x824];
2612 } lane[8]; /* Lane A, B, C, D, E, F, G, H */
2613 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
2614 } serdes_corenet_t;
2615
2616 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2617
2618 #define SRDS_MAX_LANES 18
2619 #define SRDS_MAX_BANK 3
2620 typedef struct serdes_corenet {
2621 struct {
2622 u32 rstctl; /* Reset Control Register */
2623 #define SRDS_RSTCTL_RST 0x80000000
2624 #define SRDS_RSTCTL_RSTDONE 0x40000000
2625 #define SRDS_RSTCTL_RSTERR 0x20000000
2626 #define SRDS_RSTCTL_SDPD 0x00000020
2627 u32 pllcr0; /* PLL Control Register 0 */
2628 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2629 #define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
2630 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2631 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2632 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2633 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2634 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2635 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
2636 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2637 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
2638 u32 pllcr1; /* PLL Control Register 1 */
2639 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2640 u32 res[5];
2641 } bank[3];
2642 u32 res1[12];
2643 u32 srdstcalcr; /* TX Calibration Control */
2644 u32 res2[3];
2645 u32 srdsrcalcr; /* RX Calibration Control */
2646 u32 res3[3];
2647 u32 srdsgr0; /* General Register 0 */
2648 u32 res4[11];
2649 u32 srdspccr0; /* Protocol Converter Config 0 */
2650 u32 srdspccr1; /* Protocol Converter Config 1 */
2651 u32 srdspccr2; /* Protocol Converter Config 2 */
2652 #define SRDS_PCCR2_RST_XGMII1 0x00800000
2653 #define SRDS_PCCR2_RST_XGMII2 0x00400000
2654 u32 res5[197];
2655 struct serdes_lane {
2656 u32 gcr0; /* General Control Register 0 */
2657 #define SRDS_GCR0_RRST 0x00400000
2658 #define SRDS_GCR0_1STLANE 0x00010000
2659 #define SRDS_GCR0_UOTHL 0x00100000
2660 u32 gcr1; /* General Control Register 1 */
2661 #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2662 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2663 #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2664 #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2665 #define SRDS_GCR1_OPAD_CTL 0x04000000
2666 u32 res1[4];
2667 u32 tecr0; /* TX Equalization Control Reg 0 */
2668 #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2669 #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2670 u32 res3;
2671 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
2672 #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
2673 #define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
2674 #define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
2675 #define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
2676 #define SRDS_TTLCR0_PM_DIS 0x00004000
2677 #define SRDS_TTLCR0_FREQOVD_EN 0x00000001
2678 u32 res4[7];
2679 } lane[24];
2680 u32 res6[384];
2681 } serdes_corenet_t;
2682 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2683
2684 enum {
2685 FSL_SRDS_B1_LANE_A = 0,
2686 FSL_SRDS_B1_LANE_B = 1,
2687 FSL_SRDS_B1_LANE_C = 2,
2688 FSL_SRDS_B1_LANE_D = 3,
2689 FSL_SRDS_B1_LANE_E = 4,
2690 FSL_SRDS_B1_LANE_F = 5,
2691 FSL_SRDS_B1_LANE_G = 6,
2692 FSL_SRDS_B1_LANE_H = 7,
2693 FSL_SRDS_B1_LANE_I = 8,
2694 FSL_SRDS_B1_LANE_J = 9,
2695 FSL_SRDS_B2_LANE_A = 16,
2696 FSL_SRDS_B2_LANE_B = 17,
2697 FSL_SRDS_B2_LANE_C = 18,
2698 FSL_SRDS_B2_LANE_D = 19,
2699 FSL_SRDS_B3_LANE_A = 20,
2700 FSL_SRDS_B3_LANE_B = 21,
2701 FSL_SRDS_B3_LANE_C = 22,
2702 FSL_SRDS_B3_LANE_D = 23,
2703 };
2704
2705 typedef struct ccsr_qman {
2706 #ifdef CONFIG_SYS_FSL_QMAN_V3
2707 u8 res0[0x200];
2708 #else
2709 struct {
2710 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2711 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2712 u32 res;
2713 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
2714 } qcsp[32];
2715 #endif
2716 /* Not actually reserved, but irrelevant to u-boot */
2717 u8 res[0xbf8 - 0x200];
2718 u32 ip_rev_1;
2719 u32 ip_rev_2;
2720 u32 fqd_bare; /* FQD Extended Base Addr Register */
2721 u32 fqd_bar; /* FQD Base Addr Register */
2722 u8 res1[0x8];
2723 u32 fqd_ar; /* FQD Attributes Register */
2724 u8 res2[0xc];
2725 u32 pfdr_bare; /* PFDR Extended Base Addr Register */
2726 u32 pfdr_bar; /* PFDR Base Addr Register */
2727 u8 res3[0x8];
2728 u32 pfdr_ar; /* PFDR Attributes Register */
2729 u8 res4[0x4c];
2730 u32 qcsp_bare; /* QCSP Extended Base Addr Register */
2731 u32 qcsp_bar; /* QCSP Base Addr Register */
2732 u8 res5[0x78];
2733 u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
2734 u32 srcidr; /* Source ID Register */
2735 u32 liodnr; /* LIODN Register */
2736 u8 res6[4];
2737 u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
2738 u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
2739 u8 res7[0x2e8];
2740 #ifdef CONFIG_SYS_FSL_QMAN_V3
2741 struct {
2742 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2743 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2744 u32 res;
2745 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
2746 } qcsp[50];
2747 #endif
2748 } ccsr_qman_t;
2749
2750 typedef struct ccsr_bman {
2751 /* Not actually reserved, but irrelevant to u-boot */
2752 u8 res[0xbf8];
2753 u32 ip_rev_1;
2754 u32 ip_rev_2;
2755 u32 fbpr_bare; /* FBPR Extended Base Addr Register */
2756 u32 fbpr_bar; /* FBPR Base Addr Register */
2757 u8 res1[0x8];
2758 u32 fbpr_ar; /* FBPR Attributes Register */
2759 u8 res2[0xf0];
2760 u32 srcidr; /* Source ID Register */
2761 u32 liodnr; /* LIODN Register */
2762 u8 res7[0x2f4];
2763 } ccsr_bman_t;
2764
2765 typedef struct ccsr_pme {
2766 u8 res0[0x804];
2767 u32 liodnbr; /* LIODN Base Register */
2768 u8 res1[0x1f8];
2769 u32 srcidr; /* Source ID Register */
2770 u8 res2[8];
2771 u32 liodnr; /* LIODN Register */
2772 u8 res3[0x1e8];
2773 u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/
2774 u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/
2775 u8 res4[0x400];
2776 } ccsr_pme_t;
2777
2778 struct ccsr_pamu {
2779 u32 ppbah;
2780 u32 ppbal;
2781 u32 pplah;
2782 u32 pplal;
2783 u32 spbah;
2784 u32 spbal;
2785 u32 splah;
2786 u32 splal;
2787 u32 obah;
2788 u32 obal;
2789 u32 olah;
2790 u32 olal;
2791 };
2792
2793 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
2794 struct ccsr_raide {
2795 u8 res0[0x543];
2796 u32 liodnbr; /* LIODN Base Register */
2797 u8 res1[0xab8];
2798 struct {
2799 struct {
2800 u32 cfg0; /* cfg register 0 */
2801 u32 cfg1; /* cfg register 1 */
2802 u8 res1[0x3f8];
2803 } ring[2];
2804 u8 res[0x800];
2805 } jq[2];
2806 };
2807 #endif
2808
2809 #ifdef CONFIG_SYS_DPAA_RMAN
2810 struct ccsr_rman {
2811 u8 res0[0xf64];
2812 u32 mmliodnbr; /* Message Manager LIODN Base Register */
2813 u32 mmitar; /* RMAN Inbound Translation Address Register */
2814 u32 mmitdr; /* RMAN Inbound Translation Data Register */
2815 u8 res4[0x1f090];
2816 };
2817 #endif
2818
2819 #ifdef CONFIG_SYS_PMAN
2820 struct ccsr_pman {
2821 u8 res_00[0x40];
2822 u32 poes1; /* PMAN Operation Error Status Register 1 */
2823 u32 poes2; /* PMAN Operation Error Status Register 2 */
2824 u32 poeah; /* PMAN Operation Error Address High */
2825 u32 poeal; /* PMAN Operation Error Address Low */
2826 u8 res_50[0x50];
2827 u32 pr1; /* PMAN Revision Register 1 */
2828 u32 pr2; /* PMAN Revision Register 2 */
2829 u8 res_a8[0x8];
2830 u32 pcap; /* PMAN Capabilities Register */
2831 u8 res_b4[0xc];
2832 u32 pc1; /* PMAN Control Register 1 */
2833 u32 pc2; /* PMAN Control Register 2 */
2834 u32 pc3; /* PMAN Control Register 3 */
2835 u32 pc4; /* PMAN Control Register 4 */
2836 u32 pc5; /* PMAN Control Register 5 */
2837 u32 pc6; /* PMAN Control Register 6 */
2838 u8 res_d8[0x8];
2839 u32 ppa1; /* PMAN Prefetch Attributes Register 1 */
2840 u32 ppa2; /* PMAN Prefetch Attributes Register 2 */
2841 u8 res_e8[0x8];
2842 u32 pics; /* PMAN Interrupt Control and Status */
2843 u8 res_f4[0xf0c];
2844 };
2845 #endif
2846
2847 #ifdef CONFIG_FSL_CORENET
2848 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
2849 #ifdef CONFIG_SYS_PMAN
2850 #define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
2851 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
2852 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
2853 #endif
2854 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
2855 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
2856 #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
2857 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2858 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
2859 #ifdef CONFIG_SYS_FSL_SFP_VER_3_0
2860 /* In SFPv3, OSPR register is now at offset 0x200.
2861 * * So directly mapping sfp register map to this address */
2862 #define CONFIG_SYS_OSPR_OFFSET 0x200
2863 #define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
2864 #else
2865 #define CONFIG_SYS_SFP_OFFSET 0xE8000
2866 #endif
2867 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
2868 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
2869 #define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
2870 #define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
2871 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
2872 #define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
2873 #define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
2874 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2875 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
2876 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
2877 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
2878 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2879 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2880 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
2881 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
2882 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
2883 #define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
2884 #define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
2885 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
2886 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
2887 !defined(CONFIG_ARCH_B4420)
2888 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
2889 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
2890 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
2891 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
2892 #else
2893 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2894 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2895 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2896 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
2897 #endif
2898 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2899 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
2900 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
2901 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
2902 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2903 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
2904 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
2905 #define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
2906 #define CONFIG_SYS_SEC_MON_OFFSET 0x314000
2907 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
2908 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
2909 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
2910 #define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
2911 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
2912 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
2913 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
2914 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
2915 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
2916 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
2917 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
2918 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
2919 #define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
2920 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
2921 #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
2922 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
2923 #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
2924 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
2925 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
2926 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
2927 #define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
2928 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
2929 #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
2930 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
2931 #else
2932 #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
2933 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
2934 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
2935 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
2936 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
2937 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
2938 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
2939 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
2940 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
2941 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
2942 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
2943 #if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
2944 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
2945 #else
2946 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
2947 #endif
2948 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
2949 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
2950 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
2951 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
2952 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
2953 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
2954 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
2955 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
2956 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
2957 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
2958 #ifdef CONFIG_TSECV2
2959 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000
2960 #elif defined(CONFIG_TSECV2_1)
2961 #define CONFIG_SYS_TSEC1_OFFSET 0x10000
2962 #else
2963 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
2964 #endif
2965 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
2966 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
2967 #if defined(CONFIG_ARCH_C29X)
2968 #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
2969 #define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
2970 #else
2971 #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
2972 #define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
2973 #endif
2974 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
2975 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
2976 #define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
2977 #define CONFIG_SYS_SFP_OFFSET 0xE7000
2978 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
2979 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
2980 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
2981 #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
2982 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
2983 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
2984 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
2985 #endif
2986
2987 #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
2988 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
2989 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
2990
2991 #if defined(CONFIG_ARCH_BSC9132)
2992 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
2993 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
2994 (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
2995 #endif
2996
2997 #define CONFIG_SYS_FSL_CPC_ADDR \
2998 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
2999 #define CONFIG_SYS_FSL_SCFG_ADDR \
3000 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
3001 #define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
3002 (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
3003 #define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
3004 (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
3005 #define CONFIG_SYS_FSL_QMAN_ADDR \
3006 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
3007 #define CONFIG_SYS_FSL_BMAN_ADDR \
3008 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
3009 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
3010 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
3011 #define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
3012 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
3013 #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
3014 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
3015 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
3016 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
3017 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
3018 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
3019 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
3020 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
3021 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
3022 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
3023 #define CONFIG_SYS_MPC85xx_ECM_ADDR \
3024 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
3025 #define CONFIG_SYS_FSL_DDR_ADDR \
3026 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
3027 #define CONFIG_SYS_FSL_DDR2_ADDR \
3028 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
3029 #define CONFIG_SYS_FSL_DDR3_ADDR \
3030 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
3031 #define CONFIG_SYS_LBC_ADDR \
3032 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
3033 #define CONFIG_SYS_IFC_ADDR \
3034 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
3035 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \
3036 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
3037 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \
3038 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
3039 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
3040 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
3041 #define CONFIG_SYS_MPC85xx_GPIO_ADDR \
3042 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
3043 #define CONFIG_SYS_MPC85xx_SATA1_ADDR \
3044 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
3045 #define CONFIG_SYS_MPC85xx_SATA2_ADDR \
3046 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
3047 #define CONFIG_SYS_MPC85xx_L2_ADDR \
3048 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
3049 #define CONFIG_SYS_MPC85xx_DMA_ADDR \
3050 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
3051 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
3052 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
3053 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \
3054 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
3055 #define CONFIG_SYS_MPC85xx_CPM_ADDR \
3056 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
3057 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
3058 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
3059 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
3060 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
3061 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
3062 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
3063 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
3064 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
3065 #define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
3066 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
3067 #define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
3068 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
3069 #define CONFIG_SYS_MPC85xx_USB1_ADDR \
3070 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
3071 #define CONFIG_SYS_MPC85xx_USB2_ADDR \
3072 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
3073 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
3074 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
3075 #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
3076 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
3077 #define CONFIG_SYS_FSL_SEC_ADDR \
3078 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
3079 #define CONFIG_SYS_FSL_JR0_ADDR \
3080 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
3081 #define CONFIG_SYS_FSL_FM1_ADDR \
3082 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
3083 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
3084 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
3085 #define CONFIG_SYS_FSL_FM2_ADDR \
3086 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
3087 #define CONFIG_SYS_FSL_SRIO_ADDR \
3088 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
3089 #define CONFIG_SYS_PAMU_ADDR \
3090 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
3091
3092 #define CONFIG_SYS_PCI1_ADDR \
3093 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
3094 #define CONFIG_SYS_PCI2_ADDR \
3095 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
3096 #define CONFIG_SYS_PCIE1_ADDR \
3097 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
3098 #define CONFIG_SYS_PCIE2_ADDR \
3099 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
3100 #define CONFIG_SYS_PCIE3_ADDR \
3101 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
3102 #define CONFIG_SYS_PCIE4_ADDR \
3103 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
3104
3105 #define CONFIG_SYS_SFP_ADDR \
3106 (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
3107
3108 #define CONFIG_SYS_SEC_MON_ADDR \
3109 (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
3110
3111 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
3112 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
3113
3114 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
3115 struct ccsr_cluster_l2 {
3116 u32 l2csr0; /* 0x000 L2 cache control and status register 0 */
3117 u32 l2csr1; /* 0x004 L2 cache control and status register 1 */
3118 u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */
3119 u8 res_0c[500];/* 0x00c - 0x1ff */
3120 u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */
3121 u8 res_204[4];
3122 u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */
3123 u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */
3124 u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */
3125 u8 res_214[4];
3126 u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */
3127 u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */
3128 u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */
3129 u8 res_224[4];
3130 u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */
3131 u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */
3132 u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */
3133 u8 res_234[4];
3134 u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */
3135 u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */
3136 u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */
3137 u8 res244[4];
3138 u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */
3139 u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */
3140 u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */
3141 u8 res_254[4];
3142 u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */
3143 u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */
3144 u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */
3145 u8 res_264[4];
3146 u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */
3147 u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */
3148 u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */
3149 u8 res274[4];
3150 u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */
3151 u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */
3152 u8 res_280[0xb80]; /* 0x280 - 0xdff */
3153 u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */
3154 u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */
3155 u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
3156 u8 res_e0c[20]; /* 0xe0c - 0x01f */
3157 u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
3158 u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
3159 u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */
3160 u8 res_e2c[20]; /* 0xe2c - 0xe3f */
3161 u32 l2errdet; /* 0xe40 L2 cache error detect */
3162 u32 l2errdis; /* 0xe44 L2 cache error disable */
3163 u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */
3164 u32 l2errattr; /* 0xe4c L2 cache error attribute */
3165 u32 l2erreaddr; /* 0xe50 L2 cache error extended address */
3166 u32 l2erraddr; /* 0xe54 L2 cache error address */
3167 u32 l2errctl; /* 0xe58 L2 cache error control */
3168 };
3169 #define CONFIG_SYS_FSL_CLUSTER_1_L2 \
3170 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
3171 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
3172
3173 #define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
3174 struct dcsr_dcfg_regs {
3175 u8 res_0[0x520];
3176 u32 ecccr1;
3177 #define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
3178 #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
3179 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
3180 };
3181
3182 #define CONFIG_SYS_MPC85xx_SCFG \
3183 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
3184 #define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
3185 /* The supplement configuration unit register */
3186 struct ccsr_scfg {
3187 u32 dpslpcr; /* 0x000 Deep Sleep Control register */
3188 u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
3189 u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
3190 u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
3191 u32 res1[4];
3192 u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
3193 u32 res2;
3194 u32 pixclkcr; /* 0x028 Pixel Clock Control register */
3195 u32 res3[245];
3196 u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */
3197 u32 emiiocr; /* 0x404 EMI MDIO Control Register */
3198 u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
3199 u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */
3200 u32 res4[60];
3201 u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */
3202 };
3203 #endif /*__IMMAP_85xx__*/
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