arch/powerpc/include/asm/ppc405ex.h

   1 /*
   2  * (C) Copyright 2010
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #ifndef _PPC405EX_H_
  22 #define _PPC405EX_H_
  23
  24 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2    /* IBM DDR(2) controller */
  25
  26 #define CONFIG_NAND_NDFC
  27
  28 /* Memory mapped register */
  29 #define CONFIG_SYS_PERIPHERAL_BASE      0xef600000 /* Internal Peripherals */
  30
  31 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
  32 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
  33
  34 #define GPIO0_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
  35
  36 /* SDR */
  37 #define SDR0_SDCS0              0x0060
  38 #define SDR0_UART0              0x0120  /* UART0 Config */
  39 #define SDR0_UART1              0x0121  /* UART1 Config */
  40 #define SDR0_SRST               0x0200
  41 #define SDR0_CUST0              0x4000
  42 #define SDR0_PFC0               0x4100
  43 #define SDR0_PFC1               0x4101
  44 #define SDR0_MFR                0x4300  /* SDR0_MFR reg */
  45
  46 #define SDR0_ECID0              0x0080
  47 #define SDR0_ECID1              0x0081
  48 #define SDR0_ECID2              0x0082
  49 #define SDR0_ECID3              0x0083
  50
  51 #define SDR0_SDCS_SDD           (0x80000000 >> 31)
  52
  53 #define SDR0_SRST_DMC           (0x80000000 >> 10)
  54
  55 #define SDR0_CUST0_MUX_E_N_G_MASK       0xC0000000 /* Mux_Emac_NDFC_GPIO */
  56 #define SDR0_CUST0_MUX_EMAC_SEL         0x40000000 /* Emac Selection */
  57 #define SDR0_CUST0_MUX_NDFC_SEL         0x80000000 /* NDFC Selection */
  58 #define SDR0_CUST0_MUX_GPIO_SEL         0xC0000000 /* GPIO Selection */
  59
  60 #define SDR0_CUST0_NDFC_EN_MASK         0x20000000 /* NDFC Enable Mask */
  61 #define SDR0_CUST0_NDFC_ENABLE          0x20000000 /* NDFC Enable */
  62 #define SDR0_CUST0_NDFC_DISABLE         0x00000000 /* NDFC Disable */
  63
  64 #define SDR0_CUST0_NDFC_BW_MASK         0x10000000 /* NDFC Boot Width */
  65 #define SDR0_CUST0_NDFC_BW_16_BIT       0x10000000 /* NDFC Boot Width= 16 Bit */
  66 #define SDR0_CUST0_NDFC_BW_8_BIT        0x00000000 /* NDFC Boot Width=  8 Bit */
  67
  68 #define SDR0_CUST0_NDFC_BP_MASK         0x0F000000 /* NDFC Boot Page */
  69 #define SDR0_CUST0_NDFC_BP_ENCODE(n)    ((((u32)(n)) & 0xF) << 24)
  70 #define SDR0_CUST0_NDFC_BP_DECODE(n)    ((((u32)(n)) >> 24) & 0xF)
  71
  72 #define SDR0_CUST0_NDFC_BAC_MASK        0x00C00000 /* NDFC Boot Address Cycle */
  73 #define SDR0_CUST0_NDFC_BAC_ENCODE(n)   ((((u32)(n)) & 0x3) << 22)
  74 #define SDR0_CUST0_NDFC_BAC_DECODE(n)   ((((u32)(n)) >> 22) & 0x3)
  75
  76 #define SDR0_CUST0_NDFC_ARE_MASK        0x00200000 /* NDFC Auto Read Enable */
  77 #define SDR0_CUST0_NDFC_ARE_ENABLE      0x00200000 /* NDFC Auto Read Enable */
  78 #define SDR0_CUST0_NDFC_ARE_DISABLE     0x00000000 /* NDFC Auto Read Disable */
  79
  80 #define SDR0_CUST0_NRB_MASK             0x00100000 /* NDFC Ready / Busy */
  81 #define SDR0_CUST0_NRB_BUSY             0x00100000 /* Busy */
  82 #define SDR0_CUST0_NRB_READY            0x00000000 /* Ready */
  83
  84 #define SDR0_PFC1_U1ME                  0x02000000
  85 #define SDR0_PFC1_U0ME                  0x00080000
  86 #define SDR0_PFC1_U0IM                  0x00040000
  87 #define SDR0_PFC1_SIS                   0x00020000
  88 #define SDR0_PFC1_DMAAEN                0x00010000
  89 #define SDR0_PFC1_DMADEN                0x00008000
  90 #define SDR0_PFC1_USBEN                 0x00004000
  91 #define SDR0_PFC1_AHBSWAP               0x00000020
  92 #define SDR0_PFC1_USBBIGEN              0x00000010
  93 #define SDR0_PFC1_GPT_FREQ              0x0000000f
  94
  95 #endif /* _PPC405EX_H_ */