arch/powerpc/include/asm/ppc405gp.h

   1 /*
   2  * (C) Copyright 2010
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #ifndef _PPC405GP_H_
  22 #define _PPC405GP_H_
  23
  24 #define CONFIG_SDRAM_PPC4xx_IBM_SDRAM   /* IBM SDRAM controller */
  25
  26 /* Memory mapped register */
  27 #define CONFIG_SYS_PERIPHERAL_BASE      0xef600000 /* Internal Peripherals */
  28
  29 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
  30 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
  31
  32 #define GPIO0_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
  33
  34 /* DCR's */
  35 #define DCP0_CFGADDR    0x0014          /* Decompression controller addr reg */
  36 #define DCP0_CFGDATA    0x0015          /* Decompression controller data reg */
  37 #define OCM0_ISCNTL     0x0019  /* OCM I-side control reg */
  38 #define OCM0_DSARC      0x001a  /* OCM D-side address compare */
  39 #define OCM0_DSCNTL     0x001b  /* OCM D-side control */
  40 #define CPC0_PLLMR      0x00b0          /* PLL mode  register */
  41 #define CPC0_CR0        0x00b1          /* chip control register 0 */
  42 #define CPC0_CR1        0x00b2          /* chip control register 1 */
  43 #define CPC0_PSR        0x00b4          /* chip pin strapping reg */
  44 #define CPC0_EIRR       0x00b6          /* ext interrupt routing reg */
  45 #define CPC0_SR         0x00b8          /* Power management status */
  46 #define CPC0_ER         0x00b9          /* Power management enable */
  47 #define CPC0_FR         0x00ba          /* Power management force */
  48 #define CPC0_ECR        0x00aa          /* edge conditioner register */
  49
  50 /* values for kiar register - indirect addressing of these regs */
  51 #define KCONF           0x40            /* decompression core config register */
  52
  53 #define PLLMR_FWD_DIV_MASK      0xE0000000      /* Forward Divisor */
  54 #define PLLMR_FWD_DIV_BYPASS    0xE0000000
  55 #define PLLMR_FWD_DIV_3         0xA0000000
  56 #define PLLMR_FWD_DIV_4         0x80000000
  57 #define PLLMR_FWD_DIV_6         0x40000000
  58
  59 #define PLLMR_FB_DIV_MASK       0x1E000000      /* Feedback Divisor */
  60 #define PLLMR_FB_DIV_1          0x02000000
  61 #define PLLMR_FB_DIV_2          0x04000000
  62 #define PLLMR_FB_DIV_3          0x06000000
  63 #define PLLMR_FB_DIV_4          0x08000000
  64
  65 #define PLLMR_TUNING_MASK       0x01F80000
  66
  67 #define PLLMR_CPU_TO_PLB_MASK   0x00060000      /* CPU:PLB Frequency Divisor */
  68 #define PLLMR_CPU_PLB_DIV_1     0x00000000
  69 #define PLLMR_CPU_PLB_DIV_2     0x00020000
  70 #define PLLMR_CPU_PLB_DIV_3     0x00040000
  71 #define PLLMR_CPU_PLB_DIV_4     0x00060000
  72
  73 #define PLLMR_OPB_TO_PLB_MASK   0x00018000      /* OPB:PLB Frequency Divisor */
  74 #define PLLMR_OPB_PLB_DIV_1     0x00000000
  75 #define PLLMR_OPB_PLB_DIV_2     0x00008000
  76 #define PLLMR_OPB_PLB_DIV_3     0x00010000
  77 #define PLLMR_OPB_PLB_DIV_4     0x00018000
  78
  79 #define PLLMR_PCI_TO_PLB_MASK   0x00006000      /* PCI:PLB Frequency Divisor */
  80 #define PLLMR_PCI_PLB_DIV_1     0x00000000
  81 #define PLLMR_PCI_PLB_DIV_2     0x00002000
  82 #define PLLMR_PCI_PLB_DIV_3     0x00004000
  83 #define PLLMR_PCI_PLB_DIV_4     0x00006000
  84
  85 #define PLLMR_EXB_TO_PLB_MASK   0x00001800      /* External Bus:PLB Divisor */
  86 #define PLLMR_EXB_PLB_DIV_2     0x00000000
  87 #define PLLMR_EXB_PLB_DIV_3     0x00000800
  88 #define PLLMR_EXB_PLB_DIV_4     0x00001000
  89 #define PLLMR_EXB_PLB_DIV_5     0x00001800
  90
  91 /* definitions for PPC405GPr (new mode strapping) */
  92 #define PLLMR_FWDB_DIV_MASK     0x00000007      /* Forward Divisor B */
  93
  94 #define PSR_PLL_FWD_MASK        0xC0000000
  95 #define PSR_PLL_FDBACK_MASK     0x30000000
  96 #define PSR_PLL_TUNING_MASK     0x0E000000
  97 #define PSR_PLB_CPU_MASK        0x01800000
  98 #define PSR_OPB_PLB_MASK        0x00600000
  99 #define PSR_PCI_PLB_MASK        0x00180000
 100 #define PSR_EB_PLB_MASK         0x00060000
 101 #define PSR_ROM_WIDTH_MASK      0x00018000
 102 #define PSR_ROM_LOC             0x00004000
 103 #define PSR_PCI_ASYNC_EN        0x00001000
 104 #define PSR_PERCLK_SYNC_MODE_EN 0x00000800      /* PPC405GPr only */
 105 #define PSR_PCI_ARBIT_EN        0x00000400
 106 #define PSR_NEW_MODE_EN         0x00000020      /* PPC405GPr only */
 107
 108 #endif /* _PPC405GP_H_ */