arch/x86/cpu/irq.c

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <fdtdec.h>
  11 #include <malloc.h>
  12 #include <asm/io.h>
  13 #include <asm/irq.h>
  14 #include <asm/pci.h>
  15 #include <asm/pirq_routing.h>
  16 #include <asm/tables.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
  21 {
  22         struct irq_router *priv = dev_get_priv(dev);
  23         u8 pirq;
  24         int base = priv->link_base;
  25
  26         if (priv->config == PIRQ_VIA_PCI)
  27                 dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq);
  28         else
  29                 pirq = readb((uintptr_t)priv->ibase + LINK_N2V(link, base));
  30
  31         pirq &= 0xf;
  32
  33         /* IRQ# 0/1/2/8/13 are reserved */
  34         if (pirq < 3 || pirq == 8 || pirq == 13)
  35                 return false;
  36
  37         return pirq == irq ? true : false;
  38 }
  39
  40 int pirq_translate_link(struct udevice *dev, int link)
  41 {
  42         struct irq_router *priv = dev_get_priv(dev);
  43
  44         return LINK_V2N(link, priv->link_base);
  45 }
  46
  47 void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
  48 {
  49         struct irq_router *priv = dev_get_priv(dev);
  50         int base = priv->link_base;
  51
  52         /* IRQ# 0/1/2/8/13 are reserved */
  53         if (irq < 3 || irq == 8 || irq == 13)
  54                 return;
  55
  56         if (priv->config == PIRQ_VIA_PCI)
  57                 dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq);
  58         else
  59                 writeb(irq, (uintptr_t)priv->ibase + LINK_N2V(link, base));
  60 }
  61
  62 static struct irq_info *check_dup_entry(struct irq_info *slot_base,
  63                                         int entry_num, int bus, int device)
  64 {
  65         struct irq_info *slot = slot_base;
  66         int i;
  67
  68         for (i = 0; i < entry_num; i++) {
  69                 if (slot->bus == bus && slot->devfn == (device << 3))
  70                         break;
  71                 slot++;
  72         }
  73
  74         return (i == entry_num) ? NULL : slot;
  75 }
  76
  77 static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot,
  78                                  int bus, int device, int pin, int pirq)
  79 {
  80         slot->bus = bus;
  81         slot->devfn = (device << 3) | 0;
  82         slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base);
  83         slot->irq[pin - 1].bitmap = priv->irq_mask;
  84 }
  85
  86 static int create_pirq_routing_table(struct udevice *dev)
  87 {
  88         struct irq_router *priv = dev_get_priv(dev);
  89         const void *blob = gd->fdt_blob;
  90         int node;
  91         int len, count;
  92         const u32 *cell;
  93         struct irq_routing_table *rt;
  94         struct irq_info *slot, *slot_base;
  95         int irq_entries = 0;
  96         int i;
  97         int ret;
  98
  99         node = dev_of_offset(dev);
 100
 101         /* extract the bdf from fdt_pci_addr */
 102         priv->bdf = dm_pci_get_bdf(dev->parent);
 103
 104         ret = fdt_stringlist_search(blob, node, "intel,pirq-config", "pci");
 105         if (!ret) {
 106                 priv->config = PIRQ_VIA_PCI;
 107         } else {
 108                 ret = fdt_stringlist_search(blob, node, "intel,pirq-config",
 109                                             "ibase");
 110                 if (!ret)
 111                         priv->config = PIRQ_VIA_IBASE;
 112                 else
 113                         return -EINVAL;
 114         }
 115
 116         ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
 117         if (ret == -1)
 118                 return ret;
 119         priv->link_base = ret;
 120
 121         priv->irq_mask = fdtdec_get_int(blob, node,
 122                                         "intel,pirq-mask", PIRQ_BITMAP);
 123
 124         if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
 125                 /* Reserve IRQ9 for SCI */
 126                 priv->irq_mask &= ~(1 << 9);
 127         }
 128
 129         if (priv->config == PIRQ_VIA_IBASE) {
 130                 int ibase_off;
 131
 132                 ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
 133                 if (!ibase_off)
 134                         return -EINVAL;
 135
 136                 /*
 137                  * Here we assume that the IBASE register has already been
 138                  * properly configured by U-Boot before.
 139                  *
 140                  * By 'valid' we mean:
 141                  *   1) a valid memory space carved within system memory space
 142                  *      assigned to IBASE register block.
 143                  *   2) memory range decoding is enabled.
 144                  * Hence we don't do any santify test here.
 145                  */
 146                 dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase);
 147                 priv->ibase &= ~0xf;
 148         }
 149
 150         priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
 151         priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
 152
 153         cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
 154         if (!cell || len % sizeof(struct pirq_routing))
 155                 return -EINVAL;
 156         count = len / sizeof(struct pirq_routing);
 157
 158         rt = calloc(1, sizeof(struct irq_routing_table));
 159         if (!rt)
 160                 return -ENOMEM;
 161
 162         /* Populate the PIRQ table fields */
 163         rt->signature = PIRQ_SIGNATURE;
 164         rt->version = PIRQ_VERSION;
 165         rt->rtr_bus = PCI_BUS(priv->bdf);
 166         rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf);
 167         rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
 168         rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
 169
 170         slot_base = rt->slots;
 171
 172         /* Now fill in the irq_info entries in the PIRQ table */
 173         for (i = 0; i < count;
 174              i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) {
 175                 struct pirq_routing pr;
 176
 177                 pr.bdf = fdt_addr_to_cpu(cell[0]);
 178                 pr.pin = fdt_addr_to_cpu(cell[1]);
 179                 pr.pirq = fdt_addr_to_cpu(cell[2]);
 180
 181                 debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n",
 182                       i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
 183                       PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
 184                       'A' + pr.pirq);
 185
 186                 slot = check_dup_entry(slot_base, irq_entries,
 187                                        PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
 188                 if (slot) {
 189                         debug("found entry for bus %d device %d, ",
 190                               PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
 191
 192                         if (slot->irq[pr.pin - 1].link) {
 193                                 debug("skipping\n");
 194
 195                                 /*
 196                                  * Sanity test on the routed PIRQ pin
 197                                  *
 198                                  * If they don't match, show a warning to tell
 199                                  * there might be something wrong with the PIRQ
 200                                  * routing information in the device tree.
 201                                  */
 202                                 if (slot->irq[pr.pin - 1].link !=
 203                                         LINK_N2V(pr.pirq, priv->link_base))
 204                                         debug("WARNING: Inconsistent PIRQ routing information\n");
 205                                 continue;
 206                         }
 207                 } else {
 208                         slot = slot_base + irq_entries++;
 209                 }
 210                 debug("writing INT%c\n", 'A' + pr.pin - 1);
 211                 fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
 212                               pr.pin, pr.pirq);
 213         }
 214
 215         rt->size = irq_entries * sizeof(struct irq_info) + 32;
 216
 217         /* Fix up the table checksum */
 218         rt->checksum = table_compute_checksum(rt, rt->size);
 219
 220         gd->arch.pirq_routing_table = rt;
 221
 222         return 0;
 223 }
 224
 225 static void irq_enable_sci(struct udevice *dev)
 226 {
 227         struct irq_router *priv = dev_get_priv(dev);
 228
 229         if (priv->actl_8bit) {
 230                 /* Bit7 must be turned on to enable ACPI */
 231                 dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
 232         } else {
 233                 /* Write 0 to enable SCI on IRQ9 */
 234                 if (priv->config == PIRQ_VIA_PCI)
 235                         dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
 236                 else
 237                         writel(0, (uintptr_t)priv->ibase + priv->actl_addr);
 238         }
 239 }
 240
 241 int irq_router_common_init(struct udevice *dev)
 242 {
 243         int ret;
 244
 245         ret = create_pirq_routing_table(dev);
 246         if (ret) {
 247                 debug("Failed to create pirq routing table\n");
 248                 return ret;
 249         }
 250         /* Route PIRQ */
 251         pirq_route_irqs(dev, gd->arch.pirq_routing_table->slots,
 252                         get_irq_slot_count(gd->arch.pirq_routing_table));
 253
 254         if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
 255                 irq_enable_sci(dev);
 256
 257         return 0;
 258 }
 259
 260 int irq_router_probe(struct udevice *dev)
 261 {
 262         return irq_router_common_init(dev);
 263 }
 264
 265 ulong write_pirq_routing_table(ulong addr)
 266 {
 267         if (!gd->arch.pirq_routing_table)
 268                 return addr;
 269
 270         return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table);
 271 }
 272
 273 static const struct udevice_id irq_router_ids[] = {
 274         { .compatible = "intel,irq-router" },
 275         { }
 276 };
 277
 278 U_BOOT_DRIVER(irq_router_drv) = {
 279         .name           = "intel_irq",
 280         .id             = UCLASS_IRQ,
 281         .of_match       = irq_router_ids,
 282         .probe          = irq_router_probe,
 283         .priv_auto_alloc_size = sizeof(struct irq_router),
 284 };
 285
 286 UCLASS_DRIVER(irq) = {
 287         .id             = UCLASS_IRQ,
 288         .name           = "irq",
 289 };