board/actux4/actux4.c

   1 /*
   2  * (C) Copyright 2007
   3  * Michael Schwingen, michael@schwingen.org
   4  *
   5  * (C) Copyright 2006
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * (C) Copyright 2002
   9  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  10  *
  11  * (C) Copyright 2002
  12  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  13  * Marius Groeger <mgroeger@sysgo.de>
  14  *
  15  * See file CREDITS for list of people who contributed to this
  16  * project.
  17  *
  18  * This program is free software; you can redistribute it and/or
  19  * modify it under the terms of the GNU General Public License as
  20  * published by the Free Software Foundation; either version 2 of
  21  * the License, or (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  31  * MA 02111-1307 USA
  32  */
  33
  34 #include <common.h>
  35 #include <command.h>
  36 #include <malloc.h>
  37 #include <asm/arch/ixp425.h>
  38
  39 #include <miiphy.h>
  40
  41 #include "actux4_hw.h"
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 int board_init (void)
  46 {
  47         gd->bd->bi_arch_number = MACH_TYPE_ACTUX4;
  48
  49         /* adress of boot parameters */
  50         gd->bd->bi_boot_params = 0x00000100;
  51
  52         GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_nPWRON);
  53         GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_nPWRON);
  54
  55         GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
  56         GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
  57
  58         /* led not populated on board*/
  59         GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED3);
  60         GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED3);
  61
  62         /* middle LED */
  63         GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED2);
  64         GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED2);
  65
  66         /* right LED */
  67         /* weak pulldown = LED weak on */
  68         GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_LED1);
  69         GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED1);
  70
  71         /* Setup GPIO's for Interrupt inputs */
  72         GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTA);
  73         GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTB);
  74         GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTC);
  75         GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_RTCINT);
  76         GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTA);
  77         GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTB);
  78
  79         GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTA);
  80         GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTB);
  81         GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTC);
  82         GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_RTCINT);
  83         GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTA);
  84         GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTB);
  85
  86         /* Setup GPIO's for 33MHz clock output */
  87         *IXP425_GPIO_GPCLKR = 0x011001FF;
  88         GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
  89         GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
  90
  91         *IXP425_EXP_CS1 = 0xbd113c42;
  92
  93         udelay (10000);
  94         GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
  95         udelay (10000);
  96         GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
  97         udelay (10000);
  98         GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
  99
 100         return 0;
 101 }
 102
 103 /* Check Board Identity */
 104 int checkboard (void)
 105 {
 106         puts ("Board: AcTux-4\n");
 107         return (0);
 108 }
 109
 110 int dram_init (void)
 111 {
 112         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 113         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 114
 115         return (0);
 116 }
 117
 118 /*
 119  * Hardcoded flash setup:
 120  * Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus.
 121  * Flash 1 is an Intel *16 flash using the CFI driver.
 122  */
 123 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
 124 {
 125         if (banknum == 0) {     /* non-CFI boot flash */
 126                 info->portwidth = 1;
 127                 info->chipwidth = 1;
 128                 info->interface = FLASH_CFI_X8;
 129                 return 1;
 130         } else
 131                 return 0;
 132 }