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git.ipfire.org Git - people/ms/u-boot.git/blob - board/ads5121/pci.c
2 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/global_data.h>
28 #if defined(CONFIG_OF_LIBFDT)
30 #include <fdt_support.h>
33 DECLARE_GLOBAL_DATA_PTR
;
35 /* System RAM mapped to PCI space */
36 #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
37 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
39 static struct pci_controller pci_hose
;
42 /**************************************************************************
49 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
50 volatile law512x_t
*pci_law
;
51 volatile pot512x_t
*pci_pot
;
52 volatile pcictrl512x_t
*pci_ctrl
;
53 volatile pciconf512x_t
*pci_conf
;
57 struct pci_controller
*hose
;
59 /* Set PCI divider for 33MHz */
60 reg32
= immr
->clk
.scfr
[0];
61 reg32
&= ~(SCFR1_PCI_DIV_MASK
);
62 reg32
|= SCFR1_PCI_DIV
<< SCFR1_PCI_DIV_SHIFT
;
63 immr
->clk
.scfr
[0] = reg32
;
65 pci_law
= immr
->sysconf
.pcilaw
;
66 pci_pot
= immr
->ios
.pot
;
67 pci_ctrl
= &immr
->pci_ctrl
;
68 pci_conf
= &immr
->pci_conf
;
73 * Release PCI RST Output signal
79 /* We need to wait at least a 1sec based on PCI specs */
83 for (i
= 0; i
< 1000; i
++)
88 * Configure PCI Local Access Windows
90 pci_law
[0].bar
= CONFIG_SYS_PCI_MEM_PHYS
& LAWBAR_BAR
;
91 pci_law
[0].ar
= LAWAR_EN
| LAWAR_SIZE_512M
;
93 pci_law
[1].bar
= CONFIG_SYS_PCI_IO_PHYS
& LAWBAR_BAR
;
94 pci_law
[1].ar
= LAWAR_EN
| LAWAR_SIZE_16M
;
97 * Configure PCI Outbound Translation Windows
100 /* PCI mem space - prefetch */
101 pci_pot
[0].potar
= (CONFIG_SYS_PCI_MEM_BASE
>> 12) & POTAR_TA_MASK
;
102 pci_pot
[0].pobar
= (CONFIG_SYS_PCI_MEM_PHYS
>> 12) & POBAR_BA_MASK
;
103 pci_pot
[0].pocmr
= POCMR_EN
| POCMR_PRE
| POCMR_CM_256M
;
106 pci_pot
[1].potar
= (CONFIG_SYS_PCI_IO_BASE
>> 12) & POTAR_TA_MASK
;
107 pci_pot
[1].pobar
= (CONFIG_SYS_PCI_IO_PHYS
>> 12) & POBAR_BA_MASK
;
108 pci_pot
[1].pocmr
= POCMR_EN
| POCMR_IO
| POCMR_CM_16M
;
110 /* PCI mmio - non-prefetch mem space */
111 pci_pot
[2].potar
= (CONFIG_SYS_PCI_MMIO_BASE
>> 12) & POTAR_TA_MASK
;
112 pci_pot
[2].pobar
= (CONFIG_SYS_PCI_MMIO_PHYS
>> 12) & POBAR_BA_MASK
;
113 pci_pot
[2].pocmr
= POCMR_EN
| POCMR_CM_256M
;
116 * Configure PCI Inbound Translation Windows
119 /* we need RAM mapped to PCI space for the devices to
120 * access main memory */
121 pci_ctrl
[0].pitar1
= 0x0;
122 pci_ctrl
[0].pibar1
= 0x0;
123 pci_ctrl
[0].piebar1
= 0x0;
124 pci_ctrl
[0].piwar1
= PIWAR_EN
| PIWAR_PF
| PIWAR_RTT_SNOOP
|
125 PIWAR_WTT_SNOOP
| (__ilog2(gd
->ram_size
) - 1);
127 hose
->first_busno
= 0;
128 hose
->last_busno
= 0xff;
130 /* PCI memory prefetch space */
131 pci_set_region(hose
->regions
+ 0,
132 CONFIG_SYS_PCI_MEM_BASE
,
133 CONFIG_SYS_PCI_MEM_PHYS
,
134 CONFIG_SYS_PCI_MEM_SIZE
,
135 PCI_REGION_MEM
|PCI_REGION_PREFETCH
);
137 /* PCI memory space */
138 pci_set_region(hose
->regions
+ 1,
139 CONFIG_SYS_PCI_MMIO_BASE
,
140 CONFIG_SYS_PCI_MMIO_PHYS
,
141 CONFIG_SYS_PCI_MMIO_SIZE
,
145 pci_set_region(hose
->regions
+ 2,
146 CONFIG_SYS_PCI_IO_BASE
,
147 CONFIG_SYS_PCI_IO_PHYS
,
148 CONFIG_SYS_PCI_IO_SIZE
,
151 /* System memory space */
152 pci_set_region(hose
->regions
+ 3,
153 CONFIG_PCI_SYS_MEM_BUS
,
154 CONFIG_PCI_SYS_MEM_PHYS
,
156 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
158 hose
->region_count
= 4;
160 pci_setup_indirect(hose
,
161 (CONFIG_SYS_IMMR
+ 0x8300),
162 (CONFIG_SYS_IMMR
+ 0x8304));
164 pci_register_hose(hose
);
167 * Write to Command register
170 dev
= PCI_BDF(hose
->first_busno
, 0, 0);
171 pci_hose_read_config_word(hose
, dev
, PCI_COMMAND
, ®16
);
172 reg16
|= PCI_COMMAND_SERR
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
;
173 pci_hose_write_config_word(hose
, dev
, PCI_COMMAND
, reg16
);
176 * Clear non-reserved bits in status register.
178 pci_hose_write_config_word(hose
, dev
, PCI_STATUS
, 0xffff);
179 pci_hose_write_config_byte(hose
, dev
, PCI_LATENCY_TIMER
, 0x80);
180 pci_hose_write_config_byte(hose
, dev
, PCI_CACHE_LINE_SIZE
, 0x08);
182 #ifdef CONFIG_PCI_SCAN_SHOW
183 printf("PCI: Bus Dev VenId DevId Class Int\n");
188 hose
->last_busno
= pci_hose_scan(hose
);
191 #if defined(CONFIG_OF_LIBFDT)
192 void ft_pci_setup(void *blob
, bd_t
*bd
)
198 nodeoffset
= fdt_path_offset(blob
, "/aliases");
199 if (nodeoffset
>= 0) {
200 path
= fdt_getprop(blob
, nodeoffset
, "pci", NULL
);
202 tmp
[0] = cpu_to_be32(pci_hose
.first_busno
);
203 tmp
[1] = cpu_to_be32(pci_hose
.last_busno
);
204 do_fixup_by_path(blob
, path
, "bus-range",
205 &tmp
, sizeof(tmp
), 1);
207 tmp
[0] = cpu_to_be32(gd
->pci_clk
);
208 do_fixup_by_path(blob
, path
, "clock-frequency",
209 &tmp
, sizeof(tmp
[0]), 1);
213 #endif /* CONFIG_OF_LIBFDT */