board/amcc/bamboo/init.S

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <asm-offsets.h>
  27 #include <ppc_asm.tmpl>
  28 #include <config.h>
  29 #include <asm/mmu.h>
  30
  31 /**************************************************************************
  32  * TLB TABLE
  33  *
  34  * This table is used by the cpu boot code to setup the initial tlb
  35  * entries. Rather than make broad assumptions in the cpu source tree,
  36  * this table lets each board set things up however they like.
  37  *
  38  *  Pointer to the table is returned in r1
  39  *
  40  *************************************************************************/
  41         .section .bootpg,"ax"
  42         .globl tlbtab
  43
  44 tlbtab:
  45         tlbtab_start
  46
  47         /*
  48          * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
  49          * speed up boot process. It is patched after relocation to enable SA_I
  50          */
  51 #ifndef CONFIG_NAND_SPL
  52         tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
  53 #else
  54         tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G)
  55         tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
  56 #endif
  57
  58         /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
  59         tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
  60
  61         /* PCI base & peripherals */
  62         tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG)
  63
  64         tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I)
  65         tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I)
  66
  67         /* PCI */
  68         tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG)
  69         tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG)
  70         tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG)
  71         tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG)
  72
  73         /* USB 2.0 Device */
  74         tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
  75
  76         tlbtab_end
  77
  78 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  79         /*
  80          * For NAND booting the first TLB has to be reconfigured to full size
  81          * and with caching disabled after running from RAM!
  82          */
  83 #define TLB00   TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
  84 #define TLB01   TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
  85 #define TLB02   TLB2(AC_RWX | SA_IG)
  86
  87         .globl  reconfig_tlb0
  88 reconfig_tlb0:
  89         sync
  90         isync
  91         addi    r4,r0,0x0000            /* TLB entry #0 */
  92         lis     r5,TLB00@h
  93         ori     r5,r5,TLB00@l
  94         tlbwe   r5,r4,0x0000            /* Save it out */
  95         lis     r5,TLB01@h
  96         ori     r5,r5,TLB01@l
  97         tlbwe   r5,r4,0x0001            /* Save it out */
  98         lis     r5,TLB02@h
  99         ori     r5,r5,TLB02@l
 100         tlbwe   r5,r4,0x0002            /* Save it out */
 101         sync
 102         isync
 103         blr
 104 #endif