2 * Copyright (C) 2004 PaulReynolds@lhsolutions.com
5 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <spd_sdram.h>
29 #include <ppc4xx_enet.h>
32 #ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
33 void show_reset_reg(void);
36 DECLARE_GLOBAL_DATA_PTR
;
40 int board_early_init_f (void)
43 volatile unsigned int *GpioOdr
;
44 volatile unsigned int *GpioTcr
;
45 volatile unsigned int *GpioOr
;
47 /*-------------------------------------------------------------------------+
48 | Initialize EBC CONFIG
49 +-------------------------------------------------------------------------*/
50 mtebc(xbcfg
, EBC_CFG_LE_UNLOCK
|
51 EBC_CFG_PTD_ENABLE
| EBC_CFG_RTC_64PERCLK
|
52 EBC_CFG_ATC_PREVIOUS
| EBC_CFG_DTC_PREVIOUS
|
53 EBC_CFG_CTC_PREVIOUS
| EBC_CFG_EMC_DEFAULT
|
54 EBC_CFG_PME_DISABLE
| EBC_CFG_PR_32
);
56 /*-------------------------------------------------------------------------+
57 | 64MB FLASH. Initialize bank 0 with default values.
58 +-------------------------------------------------------------------------*/
59 mtebc(pb0ap
, EBC_BXAP_BME_DISABLED
|EBC_BXAP_TWT_ENCODE(15) |
60 EBC_BXAP_BCE_DISABLE
|
61 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
62 EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
63 EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED
|
64 EBC_BXAP_BEM_WRITEONLY
|
65 EBC_BXAP_PEN_DISABLED
);
66 mtebc(pb0cr
, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE
) |
67 EBC_BXCR_BS_64MB
| EBC_BXCR_BU_RW
|EBC_BXCR_BW_32BIT
);
69 /*-------------------------------------------------------------------------+
70 | FPGA. Initialize bank 1 with default values.
71 +-------------------------------------------------------------------------*/
72 mtebc(pb1ap
, EBC_BXAP_BME_DISABLED
|EBC_BXAP_TWT_ENCODE(5) |
73 EBC_BXAP_BCE_DISABLE
|
74 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
75 EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
76 EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED
|
77 EBC_BXAP_BEM_WRITEONLY
|
78 EBC_BXAP_PEN_DISABLED
);
79 mtebc(pb1cr
, EBC_BXCR_BAS_ENCODE(0x41000000) |
80 EBC_BXCR_BS_1MB
| EBC_BXCR_BU_RW
| EBC_BXCR_BW_8BIT
);
82 /*-------------------------------------------------------------------------+
83 | LCM. Initialize bank 2 with default values.
84 +-------------------------------------------------------------------------*/
85 mtebc(pb2ap
, EBC_BXAP_BME_DISABLED
| EBC_BXAP_TWT_ENCODE(64) |
86 EBC_BXAP_BCE_DISABLE
|
87 EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
88 EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
89 EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED
|
90 EBC_BXAP_BEM_WRITEONLY
|
91 EBC_BXAP_PEN_DISABLED
);
92 mtebc(pb2cr
, EBC_BXCR_BAS_ENCODE(0x42000000) |
93 EBC_BXCR_BS_1MB
| EBC_BXCR_BU_RW
|EBC_BXCR_BW_8BIT
);
95 /*-------------------------------------------------------------------------+
96 | TMP. Initialize bank 3 with default values.
97 +-------------------------------------------------------------------------*/
98 mtebc(pb3ap
, EBC_BXAP_BME_DISABLED
| EBC_BXAP_TWT_ENCODE(128) |
99 EBC_BXAP_BCE_DISABLE
|
100 EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
101 EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
102 EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED
|
103 EBC_BXAP_BEM_WRITEONLY
|
104 EBC_BXAP_PEN_DISABLED
);
105 mtebc(pb3cr
, EBC_BXCR_BAS_ENCODE(0x48000000) |
106 EBC_BXCR_BS_64MB
| EBC_BXCR_BU_RW
| EBC_BXCR_BW_32BIT
);
108 /*-------------------------------------------------------------------------+
109 | Connector 4~7. Initialize bank 3~ 7 with default values.
110 +-------------------------------------------------------------------------*/
120 /*--------------------------------------------------------------------
121 * Setup the interrupt controller polarities, triggers, etc.
122 *-------------------------------------------------------------------*/
124 * Because of the interrupt handling rework to handle 440GX interrupts
125 * with the common code, we needed to change names of the UIC registers.
126 * Here the new relationship:
128 * U-Boot name 440GX name
129 * -----------------------
135 mtdcr (uic1sr
, 0xffffffff); /* clear all */
136 mtdcr (uic1er
, 0x00000000); /* disable all */
137 mtdcr (uic1cr
, 0x00000009); /* SMI & UIC1 crit are critical */
138 mtdcr (uic1pr
, 0xfffffe13); /* per ref-board manual */
139 mtdcr (uic1tr
, 0x01c00008); /* per ref-board manual */
140 mtdcr (uic1vr
, 0x00000001); /* int31 highest, base=0x000 */
141 mtdcr (uic1sr
, 0xffffffff); /* clear all */
143 mtdcr (uic2sr
, 0xffffffff); /* clear all */
144 mtdcr (uic2er
, 0x00000000); /* disable all */
145 mtdcr (uic2cr
, 0x00000000); /* all non-critical */
146 mtdcr (uic2pr
, 0xffffe0ff); /* per ref-board manual */
147 mtdcr (uic2tr
, 0x00ffc000); /* per ref-board manual */
148 mtdcr (uic2vr
, 0x00000001); /* int31 highest, base=0x000 */
149 mtdcr (uic2sr
, 0xffffffff); /* clear all */
151 mtdcr (uic3sr
, 0xffffffff); /* clear all */
152 mtdcr (uic3er
, 0x00000000); /* disable all */
153 mtdcr (uic3cr
, 0x00000000); /* all non-critical */
154 mtdcr (uic3pr
, 0xffffffff); /* per ref-board manual */
155 mtdcr (uic3tr
, 0x00ff8c0f); /* per ref-board manual */
156 mtdcr (uic3vr
, 0x00000001); /* int31 highest, base=0x000 */
157 mtdcr (uic3sr
, 0xffffffff); /* clear all */
159 mtdcr (uic0sr
, 0xfc000000); /* clear all */
160 mtdcr (uic0er
, 0x00000000); /* disable all */
161 mtdcr (uic0cr
, 0x00000000); /* all non-critical */
162 mtdcr (uic0pr
, 0xfc000000); /* */
163 mtdcr (uic0tr
, 0x00000000); /* */
164 mtdcr (uic0vr
, 0x00000001); /* */
166 /* Enable two GPIO 10~11 and TraceA signal */
175 /* Set GPIO 10 and 11 as output */
176 GpioOdr
= (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE
+0x718);
177 GpioTcr
= (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE
+0x704);
178 GpioOr
= (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE
+0x700);
180 *GpioOdr
&= ~(0x00300000);
181 *GpioTcr
|= 0x00300000;
182 *GpioOr
|= 0x00300000;
187 int misc_init_r(void)
194 int checkboard (void)
196 char *s
= getenv ("serial#");
198 printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
205 #ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
212 /*************************************************************************
215 * This routine is called just prior to registering the hose and gives
216 * the board the opportunity to check things. Returning a value of zero
217 * indicates that things are bad & PCI initialization should be aborted.
219 * Different boards may wish to customize the pci controller structure
220 * (add regions, override default access routines, etc) or perform
221 * certain pre-initialization actions.
223 ************************************************************************/
224 #if defined(CONFIG_PCI)
225 int pci_pre_init(struct pci_controller
* hose
)
229 /*--------------------------------------------------------------------------+
230 * The ocotea board is always configured as the host & requires the
231 * PCI arbiter to be enabled.
232 *--------------------------------------------------------------------------*/
233 mfsdr(sdr_sdstp1
, strap
);
234 if( (strap
& SDR0_SDSTP1_PAE_MASK
) == 0 ){
235 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap
);
241 #endif /* defined(CONFIG_PCI) */
243 /*************************************************************************
246 * The bootstrap configuration provides default settings for the pci
247 * inbound map (PIM). But the bootstrap config choices are limited and
248 * may not be sufficient for a given board.
250 ************************************************************************/
251 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
252 void pci_target_init(struct pci_controller
* hose
)
254 /*--------------------------------------------------------------------------+
256 *--------------------------------------------------------------------------*/
257 out32r( PCIX0_PIM0SA
, 0 ); /* disable */
258 out32r( PCIX0_PIM1SA
, 0 ); /* disable */
259 out32r( PCIX0_PIM2SA
, 0 ); /* disable */
260 out32r( PCIX0_EROMBA
, 0 ); /* disable expansion rom */
262 /*--------------------------------------------------------------------------+
263 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
264 * options to not support sizes such as 128/256 MB.
265 *--------------------------------------------------------------------------*/
266 out32r( PCIX0_PIM0LAL
, CONFIG_SYS_SDRAM_BASE
);
267 out32r( PCIX0_PIM0LAH
, 0 );
268 out32r( PCIX0_PIM0SA
, ~(gd
->ram_size
- 1) | 1 );
270 out32r( PCIX0_BAR0
, 0 );
272 /*--------------------------------------------------------------------------+
273 * Program the board's subsystem id/vendor id
274 *--------------------------------------------------------------------------*/
275 out16r( PCIX0_SBSYSVID
, CONFIG_SYS_PCI_SUBSYS_VENDORID
);
276 out16r( PCIX0_SBSYSID
, CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
278 out16r( PCIX0_CMD
, in16r(PCIX0_CMD
) | PCI_COMMAND_MEMORY
);
280 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
282 /*************************************************************************
285 * This routine is called to determine if a pci scan should be
286 * performed. With various hardware environments (especially cPCI and
287 * PPMC) it's insufficient to depend on the state of the arbiter enable
288 * bit in the strap register, or generic host/adapter assumptions.
290 * Rather than hard-code a bad assumption in the general 440 code, the
291 * 440 pci code requires the board to decide at runtime.
293 * Return 0 for adapter mode, non-zero for host (monarch) mode.
296 ************************************************************************/
297 #if defined(CONFIG_PCI)
298 int is_pci_host(struct pci_controller
*hose
)
300 /* The ocotea board is always configured as host. */
303 #endif /* defined(CONFIG_PCI) */
307 * Returns 1 if keys pressed to start the power-on long-running tests
308 * Called from board_init_f().
310 int post_hotkeys_pressed(void)
316 int board_eth_init(bd_t
*bis
)
318 return pci_eth_init(bis
);