board/comelit/dig297/dig297.h

   1 /*
   2  * (C) Copyright 2011 Comelit Group SpA
   3  * Luca Ceresoli <luca.ceresoli@comelit.it>
   4  *
   5  * Based on board/ti/beagle/beagle.h:
   6  * (C) Copyright 2008
   7  * Dirk Behme <dirk.behme@gmail.com>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27 #ifndef _DIG297_H_
  28 #define _DIG297_H_
  29
  30 const omap3_sysinfo sysinfo = {
  31         DDR_STACKED,
  32         "OMAP3 DIG297 board",
  33         "NAND",
  34 };
  35
  36 /*
  37  * IEN  - Input Enable
  38  * IDIS - Input Disable
  39  * PTD  - Pull type Down
  40  * PTU  - Pull type Up
  41  * DIS  - Pull type selection is inactive
  42  * EN   - Pull type selection is active
  43  * M0   - Mode 0
  44  * The commented string gives the final mux configuration for that pin
  45  */
  46 #define MUX_DIG297() \
  47 /*SDRC*/\
  48         MUX_VAL(CP(SDRC_D0),        (IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
  49         MUX_VAL(CP(SDRC_D1),        (IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
  50         MUX_VAL(CP(SDRC_D2),        (IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
  51         MUX_VAL(CP(SDRC_D3),        (IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
  52         MUX_VAL(CP(SDRC_D4),        (IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
  53         MUX_VAL(CP(SDRC_D5),        (IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
  54         MUX_VAL(CP(SDRC_D6),        (IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
  55         MUX_VAL(CP(SDRC_D7),        (IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
  56         MUX_VAL(CP(SDRC_D8),        (IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
  57         MUX_VAL(CP(SDRC_D9),        (IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
  58         MUX_VAL(CP(SDRC_D10),       (IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
  59         MUX_VAL(CP(SDRC_D11),       (IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
  60         MUX_VAL(CP(SDRC_D12),       (IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
  61         MUX_VAL(CP(SDRC_D13),       (IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
  62         MUX_VAL(CP(SDRC_D14),       (IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
  63         MUX_VAL(CP(SDRC_D15),       (IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
  64         MUX_VAL(CP(SDRC_D16),       (IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
  65         MUX_VAL(CP(SDRC_D17),       (IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
  66         MUX_VAL(CP(SDRC_D18),       (IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
  67         MUX_VAL(CP(SDRC_D19),       (IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
  68         MUX_VAL(CP(SDRC_D20),       (IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
  69         MUX_VAL(CP(SDRC_D21),       (IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
  70         MUX_VAL(CP(SDRC_D22),       (IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
  71         MUX_VAL(CP(SDRC_D23),       (IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
  72         MUX_VAL(CP(SDRC_D24),       (IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
  73         MUX_VAL(CP(SDRC_D25),       (IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
  74         MUX_VAL(CP(SDRC_D26),       (IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
  75         MUX_VAL(CP(SDRC_D27),       (IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
  76         MUX_VAL(CP(SDRC_D28),       (IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
  77         MUX_VAL(CP(SDRC_D29),       (IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
  78         MUX_VAL(CP(SDRC_D30),       (IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
  79         MUX_VAL(CP(SDRC_D31),       (IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
  80         MUX_VAL(CP(SDRC_CLK),       (IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
  81         MUX_VAL(CP(SDRC_DQS0),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
  82         MUX_VAL(CP(SDRC_DQS1),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
  83         MUX_VAL(CP(SDRC_DQS2),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
  84         MUX_VAL(CP(SDRC_DQS3),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
  85         MUX_VAL(CP(SDRC_CKE0),      (IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
  86         MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | DIS | M0)) /*sdrc_cke1: NC*/\
  87 /*GPMC*/\
  88         MUX_VAL(CP(GPMC_A1),        (IDIS | PTU | EN  | M0)) /*GPMC_A1*/\
  89         MUX_VAL(CP(GPMC_A2),        (IDIS | PTU | EN  | M0)) /*GPMC_A2*/\
  90         MUX_VAL(CP(GPMC_A3),        (IDIS | PTU | EN  | M0)) /*GPMC_A3*/\
  91         MUX_VAL(CP(GPMC_A4),        (IDIS | PTU | EN  | M0)) /*GPMC_A4*/\
  92         MUX_VAL(CP(GPMC_A5),        (IDIS | PTU | EN  | M0)) /*GPMC_A5*/\
  93         MUX_VAL(CP(GPMC_A6),        (IDIS | PTU | EN  | M0)) /*GPMC_A6*/\
  94         MUX_VAL(CP(GPMC_A7),        (IDIS | PTU | EN  | M0)) /*GPMC_A7*/\
  95         MUX_VAL(CP(GPMC_A8),        (IDIS | PTU | EN  | M0)) /*GPMC_A8*/\
  96         MUX_VAL(CP(GPMC_A9),        (IDIS | PTU | EN  | M0)) /*GPMC_A9*/\
  97         MUX_VAL(CP(GPMC_A10),       (IDIS | PTU | EN  | M0)) /*GPMC_A10*/\
  98         MUX_VAL(CP(GPMC_D0),        (IEN  | PTU | EN  | M0)) /*GPMC_D0*/\
  99         MUX_VAL(CP(GPMC_D1),        (IEN  | PTU | EN  | M0)) /*GPMC_D1*/\
 100         MUX_VAL(CP(GPMC_D2),        (IEN  | PTU | EN  | M0)) /*GPMC_D2*/\
 101         MUX_VAL(CP(GPMC_D3),        (IEN  | PTU | EN  | M0)) /*GPMC_D3*/\
 102         MUX_VAL(CP(GPMC_D4),        (IEN  | PTU | EN  | M0)) /*GPMC_D4*/\
 103         MUX_VAL(CP(GPMC_D5),        (IEN  | PTU | EN  | M0)) /*GPMC_D5*/\
 104         MUX_VAL(CP(GPMC_D6),        (IEN  | PTU | EN  | M0)) /*GPMC_D6*/\
 105         MUX_VAL(CP(GPMC_D7),        (IEN  | PTU | EN  | M0)) /*GPMC_D7*/\
 106         MUX_VAL(CP(GPMC_D8),        (IEN  | PTU | EN  | M0)) /*GPMC_D8*/\
 107         MUX_VAL(CP(GPMC_D9),        (IEN  | PTU | EN  | M0)) /*GPMC_D9*/\
 108         MUX_VAL(CP(GPMC_D10),       (IEN  | PTU | EN  | M0)) /*GPMC_D10*/\
 109         MUX_VAL(CP(GPMC_D11),       (IEN  | PTU | EN  | M0)) /*GPMC_D11*/\
 110         MUX_VAL(CP(GPMC_D12),       (IEN  | PTU | EN  | M0)) /*GPMC_D12*/\
 111         MUX_VAL(CP(GPMC_D13),       (IEN  | PTU | EN  | M0)) /*GPMC_D13*/\
 112         MUX_VAL(CP(GPMC_D14),       (IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
 113         MUX_VAL(CP(GPMC_D15),       (IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
 114         MUX_VAL(CP(GPMC_NCS0),      (IDIS | PTU | EN  | M0)) /*NAND*/\
 115         /* GPMC_nCS1/2: not available on CUS package*/\
 116         MUX_VAL(CP(GPMC_NCS3),      (IDIS | PTU | DIS | M0)) /*GPMC_nCS3*/\
 117         MUX_VAL(CP(GPMC_NCS4),      (IDIS | PTU | DIS | M0)) /*GPMC_nCS4*/\
 118         MUX_VAL(CP(GPMC_NCS5),      (IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
 119         MUX_VAL(CP(GPMC_NCS6),      (IEN  | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
 120         MUX_VAL(CP(GPMC_NCS7),      (IEN  | PTU | EN  | M1)) /*SYS_nDMA_REQ3*/\
 121         MUX_VAL(CP(GPMC_NBE1),      (IDIS | PTD | DIS | M0)) /*GPMC_nBE1: NC*/\
 122         /* GPMC_WAIT2: not available on CUS package*/\
 123         MUX_VAL(CP(GPMC_WAIT3),     (IDIS | PTU | DIS | M0)) /*GPMC_WAIT3: NC*/\
 124         /* GPMC_CLK: NC (only asyncronous peripherals are connected) */\
 125         MUX_VAL(CP(GPMC_CLK),       (IDIS | PTD | DIS | M0)) \
 126         MUX_VAL(CP(GPMC_NADV_ALE),  (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
 127         MUX_VAL(CP(GPMC_NOE),       (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
 128         MUX_VAL(CP(GPMC_NWE),       (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
 129         MUX_VAL(CP(GPMC_NBE0_CLE),  (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
 130         MUX_VAL(CP(GPMC_NWP),       (IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
 131         MUX_VAL(CP(GPMC_WAIT0),     (IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
 132         /* GPMC_WAIT1: not available on CUS package*/\
 133 /*DSS*/\
 134         MUX_VAL(CP(DSS_PCLK),       (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
 135         MUX_VAL(CP(DSS_HSYNC),      (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
 136         MUX_VAL(CP(DSS_VSYNC),      (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
 137         /* DSS_ACBIAS: AC BIAS: connected to TFT, not to be driven */\
 138         MUX_VAL(CP(DSS_ACBIAS),     (IDIS | PTU | EN  | M7))\
 139         MUX_VAL(CP(DSS_DATA0),      (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
 140         MUX_VAL(CP(DSS_DATA1),      (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
 141         MUX_VAL(CP(DSS_DATA2),      (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
 142         MUX_VAL(CP(DSS_DATA3),      (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
 143         MUX_VAL(CP(DSS_DATA4),      (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
 144         MUX_VAL(CP(DSS_DATA5),      (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
 145         MUX_VAL(CP(DSS_DATA6),      (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
 146         MUX_VAL(CP(DSS_DATA7),      (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
 147         MUX_VAL(CP(DSS_DATA8),      (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
 148         MUX_VAL(CP(DSS_DATA9),      (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
 149         MUX_VAL(CP(DSS_DATA10),     (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
 150         MUX_VAL(CP(DSS_DATA11),     (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
 151         MUX_VAL(CP(DSS_DATA12),     (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
 152         MUX_VAL(CP(DSS_DATA13),     (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
 153         MUX_VAL(CP(DSS_DATA14),     (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
 154         MUX_VAL(CP(DSS_DATA15),     (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
 155         MUX_VAL(CP(DSS_DATA16),     (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
 156         MUX_VAL(CP(DSS_DATA17),     (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
 157         MUX_VAL(CP(DSS_DATA18),     (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
 158         MUX_VAL(CP(DSS_DATA19),     (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
 159         MUX_VAL(CP(DSS_DATA20),     (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
 160         MUX_VAL(CP(DSS_DATA21),     (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
 161         MUX_VAL(CP(DSS_DATA22),     (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
 162         MUX_VAL(CP(DSS_DATA23),     (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
 163 /*CAMERA*/\
 164         MUX_VAL(CP(CAM_HS),         (IEN  | PTU | EN  | M0)) /*CAM_HS */\
 165         MUX_VAL(CP(CAM_VS),         (IEN  | PTU | EN  | M0)) /*CAM_VS */\
 166         MUX_VAL(CP(CAM_XCLKA),      (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
 167         MUX_VAL(CP(CAM_PCLK),       (IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
 168         MUX_VAL(CP(CAM_FLD),        (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
 169         MUX_VAL(CP(CAM_D0),         (IEN  | PTD | DIS | M0)) /*CAM_D0*/\
 170         MUX_VAL(CP(CAM_D1),         (IEN  | PTD | DIS | M0)) /*CAM_D1*/\
 171         MUX_VAL(CP(CAM_D2),         (IEN  | PTD | DIS | M0)) /*CAM_D2*/\
 172         MUX_VAL(CP(CAM_D3),         (IEN  | PTD | DIS | M0)) /*CAM_D3*/\
 173         MUX_VAL(CP(CAM_D4),         (IEN  | PTD | DIS | M0)) /*CAM_D4*/\
 174         MUX_VAL(CP(CAM_D5),         (IEN  | PTD | DIS | M0)) /*CAM_D5*/\
 175         MUX_VAL(CP(CAM_D6),         (IEN  | PTD | DIS | M0)) /*CAM_D6*/\
 176         MUX_VAL(CP(CAM_D7),         (IEN  | PTD | DIS | M0)) /*CAM_D7*/\
 177         MUX_VAL(CP(CAM_D8),         (IEN  | PTD | DIS | M0)) /*CAM_D8*/\
 178         MUX_VAL(CP(CAM_D9),         (IEN  | PTD | DIS | M0)) /*CAM_D9*/\
 179         MUX_VAL(CP(CAM_D10),        (IEN  | PTD | DIS | M0)) /*CAM_D10*/\
 180         MUX_VAL(CP(CAM_D11),        (IEN  | PTD | DIS | M0)) /*CAM_D11*/\
 181         MUX_VAL(CP(CAM_XCLKB),      (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
 182         MUX_VAL(CP(CAM_WEN),        (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
 183         MUX_VAL(CP(CAM_STROBE),     (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
 184         MUX_VAL(CP(CSI2_DX0),       (IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
 185         MUX_VAL(CP(CSI2_DY0),       (IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
 186         MUX_VAL(CP(CSI2_DX1),       (IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
 187         MUX_VAL(CP(CSI2_DY1),       (IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
 188 /*Audio Interface */\
 189         MUX_VAL(CP(MCBSP2_FSX),     (IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
 190         MUX_VAL(CP(MCBSP2_CLKX),    (IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
 191         MUX_VAL(CP(MCBSP2_DR),      (IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
 192         MUX_VAL(CP(MCBSP2_DX),      (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
 193 /*Expansion card */\
 194         MUX_VAL(CP(MMC1_CLK),       (IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
 195         MUX_VAL(CP(MMC1_CMD),       (IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
 196         MUX_VAL(CP(MMC1_DAT0),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
 197         MUX_VAL(CP(MMC1_DAT1),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
 198         MUX_VAL(CP(MMC1_DAT2),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
 199         MUX_VAL(CP(MMC1_DAT3),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
 200         MUX_VAL(CP(MMC1_DAT4),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
 201         MUX_VAL(CP(MMC1_DAT5),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
 202         MUX_VAL(CP(MMC1_DAT6),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
 203         MUX_VAL(CP(MMC1_DAT7),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
 204 /*Wireless LAN */\
 205         MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
 206         MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
 207         MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
 208         MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
 209         MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
 210         MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
 211         MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
 212         MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
 213         MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
 214         MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
 215 /*Bluetooth*/\
 216         MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
 217         MUX_VAL(CP(MCBSP3_DR),      (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
 218         MUX_VAL(CP(MCBSP3_CLKX),    (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
 219         MUX_VAL(CP(MCBSP3_FSX),     (IEN  | PTD | DIS | M1)) /*UART2_RX*/\
 220         MUX_VAL(CP(UART2_CTS),      (IEN  | PTD | DIS | M4)) /*GPIO_144*/\
 221         MUX_VAL(CP(UART2_RTS),      (IEN  | PTD | DIS | M4)) /*GPIO_145*/\
 222         MUX_VAL(CP(UART2_TX),       (IEN  | PTD | DIS | M4)) /*GPIO_146*/\
 223         MUX_VAL(CP(UART2_RX),       (IEN  | PTD | DIS | M4)) /*GPIO_147*/\
 224 /*Modem Interface */\
 225         MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
 226         MUX_VAL(CP(UART1_RTS),      (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
 227         MUX_VAL(CP(UART1_CTS),      (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
 228         MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M0)) /*UART1_RX*/\
 229         MUX_VAL(CP(MCBSP4_CLKX),    (IEN  | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
 230         MUX_VAL(CP(MCBSP4_DR),      (IEN  | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
 231         MUX_VAL(CP(MCBSP4_DX),      (IEN  | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
 232         MUX_VAL(CP(MCBSP4_FSX),     (IEN  | PTD | DIS | M1)) /*SSI1_WAKE*/\
 233         MUX_VAL(CP(MCBSP_CLKS),     (IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
 234 /*Serial Interface*/\
 235         MUX_VAL(CP(UART3_CTS_RCTX), (IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
 236         MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
 237         MUX_VAL(CP(UART3_TX_IRTX),  (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
 238         MUX_VAL(CP(HSUSB0_CLK),     (IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
 239         MUX_VAL(CP(HSUSB0_STP),     (IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
 240         MUX_VAL(CP(HSUSB0_DIR),     (IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
 241         MUX_VAL(CP(HSUSB0_NXT),     (IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
 242         MUX_VAL(CP(HSUSB0_DATA0),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
 243         MUX_VAL(CP(HSUSB0_DATA1),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
 244         MUX_VAL(CP(HSUSB0_DATA2),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
 245         MUX_VAL(CP(HSUSB0_DATA3),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
 246         MUX_VAL(CP(HSUSB0_DATA4),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
 247         MUX_VAL(CP(HSUSB0_DATA5),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
 248         MUX_VAL(CP(HSUSB0_DATA6),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
 249         MUX_VAL(CP(HSUSB0_DATA7),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
 250         MUX_VAL(CP(I2C1_SCL),       (IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
 251         MUX_VAL(CP(I2C1_SDA),       (IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
 252         MUX_VAL(CP(I2C2_SCL),       (IEN  | PTU | EN  | M4)) /*GPIO_168*/\
 253         MUX_VAL(CP(I2C2_SDA),       (IEN  | PTU | EN  | M4)) /*GPIO_183*/\
 254         MUX_VAL(CP(I2C3_SCL),       (IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
 255         MUX_VAL(CP(I2C3_SDA),       (IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
 256         MUX_VAL(CP(I2C4_SCL),       (IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
 257         MUX_VAL(CP(I2C4_SDA),       (IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
 258 /* USB EHCI (port 2) */\
 259         MUX_VAL(CP(ETK_D14_ES2),    (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
 260         MUX_VAL(CP(ETK_D15_ES2),    (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
 261 /* MCSPI1: to TOUCH controller TSC2046 (ADS7846 compatible).*/\
 262         /*
 263          * McSPI1_CLK.
 264          * IEN needed fot the McSPI to "receive" the clock and be able to
 265          * sample SOMI. See http://e2e.ti.com/support/arm174_microprocessors/
 266          * omap_applications_processors/f/42/p/29444/102394.aspx#102394
 267          */\
 268         MUX_VAL(CP(MCSPI1_CLK),     (IEN  | PTD | EN  | M0))\
 269         MUX_VAL(CP(MCSPI1_SIMO),    (IDIS | PTD | EN  | M0)) /*McSPI1_SIMO*/\
 270         MUX_VAL(CP(MCSPI1_SOMI),    (IEN  | PTD | EN  | M0)) /*McSPI1_SOMI*/\
 271         MUX_VAL(CP(MCSPI1_CS0),     (IDIS | PTU | EN  | M0)) /*McSPI1_CS0*/\
 272 /* MCSPI2: to HIMAX TFT controller.*/\
 273         MUX_VAL(CP(MCSPI2_CLK),     (IDIS | PTD | EN  | M0)) /*MCSPI2_CLK*/\
 274         MUX_VAL(CP(MCSPI2_SIMO),    (IDIS | PTD | EN  | M0)) /*MCSPI3_SIMO*/\
 275         /* MCSPI3_SOMI: NC because HIMAX in monodirectional (no SOMI line) */\
 276         MUX_VAL(CP(MCSPI2_SOMI),    (IDIS | PTU | DIS | M7))\
 277         MUX_VAL(CP(MCSPI2_CS0),     (IDIS | PTU | EN  | M0)) /*MCSPI3_CS0*/\
 278         MUX_VAL(CP(MCSPI2_CS1),     (IDIS | PTU | DIS | M7)) /*Safe mode: NC*/\
 279 /* GPIO */\
 280         MUX_VAL(CP(SYS_BOOT5),      (IEN  | PTD | DIS | M4)) /*GPIO_7*/\
 281         MUX_VAL(CP(ETK_CLK_ES2),    (IDIS | PTU | EN  | M4)) /*GPIO_12*/\
 282         MUX_VAL(CP(ETK_CTL_ES2),    (IEN  | PTU | EN  | M4)) /*GPIO_13*/\
 283         MUX_VAL(CP(ETK_D0_ES2),     (IEN  | PTU | DIS | M4)) /*GPIO_14*/\
 284         MUX_VAL(CP(ETK_D1_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_15*/\
 285         MUX_VAL(CP(ETK_D2_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_16*/\
 286         MUX_VAL(CP(ETK_D3_ES2),     (IEN  | PTU | DIS | M4)) /*GPIO_17*/\
 287         MUX_VAL(CP(ETK_D4_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_18*/\
 288         MUX_VAL(CP(ETK_D5_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_19*/\
 289         MUX_VAL(CP(ETK_D6_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_20*/\
 290         MUX_VAL(CP(ETK_D7_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_21*/\
 291         MUX_VAL(CP(ETK_D9_ES2),     (IEN  | PTU | DIS | M4)) /*GPIO_23*/\
 292         MUX_VAL(CP(ETK_D10_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_24*/\
 293         MUX_VAL(CP(ETK_D11_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_25*/\
 294         MUX_VAL(CP(ETK_D12_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_26*/\
 295         MUX_VAL(CP(ETK_D13_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_27*/\
 296         MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTD | DIS | M4)) /*GPIO_156*/\
 297         MUX_VAL(CP(MCBSP1_FSR),     (IEN  | PTU | EN  | M4)) /*GPIO_157*/\
 298         MUX_VAL(CP(MCBSP1_DX),      (IEN  | PTD | DIS | M4)) /*GPIO_158*/\
 299         MUX_VAL(CP(MCBSP1_DR),      (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
 300         MUX_VAL(CP(MCBSP1_FSX),     (IEN  | PTD | DIS | M4)) /*GPIO_161*/\
 301         MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_162*/\
 302         MUX_VAL(CP(UART3_RTS_SD),   (IDIS | PTD | EN  | M4)) /*GPIO_164*/\
 303         MUX_VAL(CP(HDQ_SIO),        (IDIS | PTU | DIS | M4)) /*GPIO_170*/\
 304         MUX_VAL(CP(MCSPI1_CS3),     (IEN  | PTU | EN  | M4)) /*GPIO_177*/\
 305 /*Control and debug */\
 306         MUX_VAL(CP(SYS_32K),        (IEN  | PTD | DIS | M0)) /*SYS_32K*/\
 307         MUX_VAL(CP(SYS_CLKREQ),     (IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
 308         MUX_VAL(CP(SYS_NIRQ),       (IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
 309         MUX_VAL(CP(SYS_BOOT0),      (IEN  | PTD | DIS | M4)) /*GPIO_2*/\
 310         MUX_VAL(CP(SYS_BOOT1),      (IEN  | PTD | DIS | M4)) /*GPIO_3*/\
 311         MUX_VAL(CP(SYS_BOOT2),      (IEN  | PTD | DIS | M4)) /*GPIO_4*/\
 312         MUX_VAL(CP(SYS_BOOT3),      (IEN  | PTD | DIS | M4)) /*GPIO_5*/\
 313         MUX_VAL(CP(SYS_BOOT4),      (IEN  | PTD | DIS | M4)) /*GPIO_6*/\
 314         MUX_VAL(CP(SYS_BOOT6),      (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
 315         MUX_VAL(CP(SYS_OFF_MODE),   (IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
 316         MUX_VAL(CP(SYS_CLKOUT1),    (IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
 317         MUX_VAL(CP(SYS_CLKOUT2),    (IEN  | PTU | EN  | M4)) /*GPIO_186*/\
 318         MUX_VAL(CP(ETK_D8_ES2),     (IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
 319         MUX_VAL(CP(D2D_MCAD1),      (IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
 320         MUX_VAL(CP(D2D_MCAD2),      (IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
 321         MUX_VAL(CP(D2D_MCAD3),      (IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
 322         MUX_VAL(CP(D2D_MCAD4),      (IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
 323         MUX_VAL(CP(D2D_MCAD5),      (IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
 324         MUX_VAL(CP(D2D_MCAD6),      (IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
 325         MUX_VAL(CP(D2D_MCAD7),      (IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
 326         MUX_VAL(CP(D2D_MCAD8),      (IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
 327         MUX_VAL(CP(D2D_MCAD9),      (IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
 328         MUX_VAL(CP(D2D_MCAD10),     (IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
 329         MUX_VAL(CP(D2D_MCAD11),     (IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
 330         MUX_VAL(CP(D2D_MCAD12),     (IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
 331         MUX_VAL(CP(D2D_MCAD13),     (IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
 332         MUX_VAL(CP(D2D_MCAD14),     (IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
 333         MUX_VAL(CP(D2D_MCAD15),     (IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
 334         MUX_VAL(CP(D2D_MCAD16),     (IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
 335         MUX_VAL(CP(D2D_MCAD17),     (IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
 336         MUX_VAL(CP(D2D_MCAD18),     (IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
 337         MUX_VAL(CP(D2D_MCAD19),     (IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
 338         MUX_VAL(CP(D2D_MCAD20),     (IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
 339         MUX_VAL(CP(D2D_MCAD21),     (IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
 340         MUX_VAL(CP(D2D_MCAD22),     (IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
 341         MUX_VAL(CP(D2D_MCAD23),     (IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
 342         MUX_VAL(CP(D2D_MCAD24),     (IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
 343         MUX_VAL(CP(D2D_MCAD25),     (IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
 344         MUX_VAL(CP(D2D_MCAD26),     (IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
 345         MUX_VAL(CP(D2D_MCAD27),     (IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
 346         MUX_VAL(CP(D2D_MCAD28),     (IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
 347         MUX_VAL(CP(D2D_MCAD29),     (IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
 348         MUX_VAL(CP(D2D_MCAD30),     (IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
 349         MUX_VAL(CP(D2D_MCAD31),     (IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
 350         MUX_VAL(CP(D2D_MCAD32),     (IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
 351         MUX_VAL(CP(D2D_MCAD33),     (IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
 352         MUX_VAL(CP(D2D_MCAD34),     (IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
 353         MUX_VAL(CP(D2D_MCAD35),     (IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
 354         MUX_VAL(CP(D2D_MCAD36),     (IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
 355         MUX_VAL(CP(D2D_CLK26MI),    (IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
 356         MUX_VAL(CP(D2D_NRESPWRON),  (IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
 357         MUX_VAL(CP(D2D_NRESWARM),   (IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
 358         MUX_VAL(CP(D2D_ARM9NIRQ),   (IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
 359         MUX_VAL(CP(D2D_UMA2P6FIQ),  (IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
 360         MUX_VAL(CP(D2D_SPINT),      (IEN  | PTD | EN  | M0)) /*d2d_spint*/\
 361         MUX_VAL(CP(D2D_FRINT),      (IEN  | PTD | EN  | M0)) /*d2d_frint*/\
 362         MUX_VAL(CP(D2D_DMAREQ0),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
 363         MUX_VAL(CP(D2D_DMAREQ1),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
 364         MUX_VAL(CP(D2D_DMAREQ2),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
 365         MUX_VAL(CP(D2D_DMAREQ3),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
 366         MUX_VAL(CP(D2D_N3GTRST),    (IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
 367         MUX_VAL(CP(D2D_N3GTDI),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
 368         MUX_VAL(CP(D2D_N3GTDO),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
 369         MUX_VAL(CP(D2D_N3GTMS),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
 370         MUX_VAL(CP(D2D_N3GTCK),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
 371         MUX_VAL(CP(D2D_N3GRTCK),    (IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
 372         MUX_VAL(CP(D2D_MSTDBY),     (IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
 373         MUX_VAL(CP(D2D_SWAKEUP),    (IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
 374         MUX_VAL(CP(D2D_IDLEREQ),    (IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
 375         MUX_VAL(CP(D2D_IDLEACK),    (IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
 376         MUX_VAL(CP(D2D_MWRITE),     (IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
 377         MUX_VAL(CP(D2D_SWRITE),     (IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
 378         MUX_VAL(CP(D2D_MREAD),      (IEN  | PTD | DIS | M0)) /*d2d_mread*/\
 379         MUX_VAL(CP(D2D_SREAD),      (IEN  | PTD | DIS | M0)) /*d2d_sread*/\
 380         MUX_VAL(CP(D2D_MBUSFLAG),   (IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
 381         MUX_VAL(CP(D2D_SBUSFLAG),   (IEN  | PTD | DIS | M0)) /*d2d_sbusflag */
 382
 383 #endif