board/congatec/cgtqmx6eval/cgtqmx6eval.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  * Based on mx6qsabrelite.c file
   4  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   5  * Leo Sartre, <lsartre@adeneo-embedded.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/arch/imx-regs.h>
  27 #include <asm/arch/iomux.h>
  28 #include <asm/arch/mx6-pins.h>
  29 #include <asm/gpio.h>
  30 #include <asm/imx-common/iomux-v3.h>
  31 #include <asm/imx-common/boot_mode.h>
  32 #include <mmc.h>
  33 #include <fsl_esdhc.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
  38         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
  41         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  42
  43 int dram_init(void)
  44 {
  45         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  46
  47         return 0;
  48 }
  49
  50 iomux_v3_cfg_t const uart2_pads[] = {
  51         MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  52         MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  53 };
  54
  55 iomux_v3_cfg_t const usdhc2_pads[] = {
  56         MX6_PAD_SD2_CLK__USDHC2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  57         MX6_PAD_SD2_CMD__USDHC2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  58         MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  59         MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  60         MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  61         MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  62         MX6_PAD_GPIO_4__GPIO_1_4      | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  63 };
  64
  65 iomux_v3_cfg_t const usdhc4_pads[] = {
  66         MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67         MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  68         MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  69         MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70         MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71         MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72         MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73         MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74         MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75         MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76         MX6_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  77 };
  78
  79 static void setup_iomux_uart(void)
  80 {
  81         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  82 }
  83
  84 #ifdef CONFIG_FSL_ESDHC
  85 struct fsl_esdhc_cfg usdhc_cfg[] = {
  86         {USDHC2_BASE_ADDR},
  87         {USDHC4_BASE_ADDR},
  88 };
  89
  90 int board_mmc_getcd(struct mmc *mmc)
  91 {
  92         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  93         int ret = 0;
  94
  95         switch (cfg->esdhc_base) {
  96         case USDHC2_BASE_ADDR:
  97                 gpio_direction_input(IMX_GPIO_NR(1, 4));
  98                 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
  99                 break;
 100         case USDHC4_BASE_ADDR:
 101                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 102                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 103                 break;
 104         default:
 105                 printf("Bad USDHC interface\n");
 106         }
 107
 108         return ret;
 109 }
 110
 111 int board_mmc_init(bd_t *bis)
 112 {
 113         s32 status = 0;
 114
 115         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 116         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 117
 118         imx_iomux_v3_setup_multiple_pads(
 119                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 120         imx_iomux_v3_setup_multiple_pads(
 121                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 122
 123         status = fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
 124                      fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
 125
 126         return status;
 127 }
 128 #endif
 129
 130 int board_early_init_f(void)
 131 {
 132         setup_iomux_uart();
 133
 134         return 0;
 135 }
 136
 137 int board_init(void)
 138 {
 139         /* address of boot parameters */
 140         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 141
 142         return 0;
 143 }
 144
 145 int checkboard(void)
 146 {
 147         puts("Board: Conga-QEVAL QMX6 Quad\n");
 148
 149         return 0;
 150 }
 151
 152 #ifdef CONFIG_CMD_BMODE
 153 static const struct boot_mode board_boot_modes[] = {
 154         /* 4 bit bus width */
 155         {"mmc0",        MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
 156         {"mmc1",        MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
 157         {NULL,          0},
 158 };
 159 #endif
 160
 161 int misc_init_r(void)
 162 {
 163 #ifdef CONFIG_CMD_BMODE
 164         add_board_boot_modes(board_boot_modes);
 165 #endif
 166         return 0;
 167 }