board/d-link/dns325/dns325.c

   1 /*
   2  * Copyright (C) 2011
   3  * Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
   4  *
   5  * Based on Kirkwood support:
   6  * (C) Copyright 2009
   7  * Marvell Semiconductor <www.marvell.com>
   8  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  26  * MA 02110-1301 USA
  27  */
  28
  29 #include <common.h>
  30 #include <miiphy.h>
  31 #include <netdev.h>
  32 #include <asm/arch/cpu.h>
  33 #include <asm/arch/kirkwood.h>
  34 #include <asm/arch/mpp.h>
  35 #include <asm/arch/gpio.h>
  36 #include "dns325.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 int board_early_init_f(void)
  41 {
  42         /* Gpio configuration */
  43         kw_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
  44                         DNS325_OE_LOW, DNS325_OE_HIGH);
  45
  46         /* Multi-Purpose Pins Functionality configuration */
  47         static const u32 kwmpp_config[] = {
  48                 MPP0_NF_IO2,
  49                 MPP1_NF_IO3,
  50                 MPP2_NF_IO4,
  51                 MPP3_NF_IO5,
  52                 MPP4_NF_IO6,
  53                 MPP5_NF_IO7,
  54                 MPP6_SYSRST_OUTn,
  55                 MPP7_GPO,
  56                 MPP8_TW_SDA,
  57                 MPP9_TW_SCK,
  58                 MPP10_UART0_TXD,
  59                 MPP11_UART0_RXD,
  60                 MPP12_SD_CLK,
  61                 MPP13_SD_CMD,
  62                 MPP14_SD_D0,
  63                 MPP15_SD_D1,
  64                 MPP16_SD_D2,
  65                 MPP17_SD_D3,
  66                 MPP18_NF_IO0,
  67                 MPP19_NF_IO1,
  68                 MPP20_SATA1_ACTn,       /* sata1(left) status led */
  69                 MPP21_SATA0_ACTn,       /* sata0(right) status led */
  70                 MPP22_GPIO,
  71                 MPP23_GPIO,
  72                 MPP24_GPIO,             /* power off out */
  73                 MPP25_GPIO,
  74                 MPP26_GPIO,             /* power led */
  75                 MPP27_GPIO,             /* sata0(right) error led */
  76                 MPP28_GPIO,             /* sata1(left) error led */
  77                 MPP29_GPIO,             /* usb error led */
  78                 MPP30_GPIO,
  79                 MPP31_GPIO,
  80                 MPP32_GPIO,
  81                 MPP33_GPIO,
  82                 MPP34_GPIO,             /* power key */
  83                 MPP35_GPIO,
  84                 MPP36_GPIO,
  85                 MPP37_GPIO,
  86                 MPP38_GPIO,
  87                 MPP39_GPIO,             /* enable sata 0 */
  88                 MPP40_GPIO,             /* enable sata 1 */
  89                 MPP41_GPIO,             /* hdd0 present */
  90                 MPP42_GPIO,             /* hdd1 present */
  91                 MPP43_GPIO,             /* usb status led */
  92                 MPP44_GPIO,             /* fan status */
  93                 MPP45_GPIO,             /* fan high speed */
  94                 MPP46_GPIO,             /* fan low speed */
  95                 MPP47_GPIO,             /* usb umount */
  96                 MPP48_GPIO,             /* factory reset */
  97                 MPP49_GPIO,             /* thermal sensor */
  98                 0
  99         };
 100         kirkwood_mpp_conf(kwmpp_config, NULL);
 101
 102         kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
 103
 104         kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
 105         return 0;
 106 }
 107
 108 int board_init(void)
 109 {
 110         /* Boot parameters address */
 111         gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 112
 113         return 0;
 114 }
 115
 116 #ifdef CONFIG_RESET_PHY_R
 117 /* Configure and initialize PHY */
 118 void reset_phy(void)
 119 {
 120         u16 reg;
 121         u16 devadr;
 122         char *name = "egiga0";
 123
 124         if (miiphy_set_current_dev(name))
 125                 return;
 126
 127         /* command to read PHY dev address */
 128         if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 129                 printf("Err..(%s) could not read PHY dev address\n", __func__);
 130                 return;
 131         }
 132
 133         /*
 134          * Enable RGMII delay on Tx and Rx for CPU port
 135          * Ref: sec 4.7.2 of chip datasheet
 136          */
 137         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
 138         miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
 139         reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
 140         miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
 141         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
 142
 143         /* reset the phy */
 144         miiphy_reset(name, devadr);
 145
 146         debug("88E1116 Initialized on %s\n", name);
 147 }
 148 #endif /* CONFIG_RESET_PHY_R */