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[people/ms/u-boot.git] / board / engicam / icorem6 / icorem6.c
1 /*
2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <common.h>
10 #include <mmc.h>
11
12 #include <asm/io.h>
13 #include <asm/gpio.h>
14 #include <linux/sizes.h>
15
16 #include <asm/arch/clock.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/imx-common/iomux-v3.h>
22 #include <asm/imx-common/video.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
27 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
28 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
29
30 static iomux_v3_cfg_t const uart4_pads[] = {
31 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
32 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
33 };
34
35 #ifdef CONFIG_NAND_MXS
36
37 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
38 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
39 PAD_CTL_SRE_FAST)
40 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
41
42 iomux_v3_cfg_t gpmi_pads[] = {
43 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
44 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
45 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
46 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
47 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
48 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
49 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
50 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
51 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
52 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
53 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
54 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
55 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
56 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
57 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
58 };
59
60 static void setup_gpmi_nand(void)
61 {
62 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
63
64 /* config gpmi nand iomux */
65 SETUP_IOMUX_PADS(gpmi_pads);
66
67 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
68 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
69
70 /* config gpmi and bch clock to 100 MHz */
71 clrsetbits_le32(&mxc_ccm->cs2cdr,
72 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
73 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
74 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
75 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
76 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
77 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
78
79 /* enable ENFC_CLK_ROOT clock */
80 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
81
82 /* enable gpmi and bch clock gating */
83 setbits_le32(&mxc_ccm->CCGR4,
84 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
85 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
86 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
87 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
88 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
89
90 /* enable apbh clock gating */
91 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
92 }
93 #endif
94
95 #if defined(CONFIG_VIDEO_IPUV3)
96 static iomux_v3_cfg_t const rgb_pads[] = {
97 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
98 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
99 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
100 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
101 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
102 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
103 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
104 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
105 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
106 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
107 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
108 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
109 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
110 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
111 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
112 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
113 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
114 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
115 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
116 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
117 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
118 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
119 };
120
121 static void enable_rgb(struct display_info_t const *dev)
122 {
123 SETUP_IOMUX_PADS(rgb_pads);
124 }
125
126 struct display_info_t const displays[] = {
127 {
128 .bus = -1,
129 .addr = 0,
130 .pixfmt = IPU_PIX_FMT_RGB666,
131 .detect = NULL,
132 .enable = enable_rgb,
133 .mode = {
134 .name = "Amp-WD",
135 .refresh = 60,
136 .xres = 800,
137 .yres = 480,
138 .pixclock = 30000,
139 .left_margin = 30,
140 .right_margin = 30,
141 .upper_margin = 5,
142 .lower_margin = 5,
143 .hsync_len = 64,
144 .vsync_len = 20,
145 .sync = FB_SYNC_EXT,
146 .vmode = FB_VMODE_NONINTERLACED
147 }
148 },
149 };
150
151 size_t display_count = ARRAY_SIZE(displays);
152
153 static void setup_display(void)
154 {
155 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
156 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
157 int reg;
158
159 enable_ipu_clock();
160
161 /* Turn on LDB0,IPU,IPU DI0 clocks */
162 reg = __raw_readl(&mxc_ccm->CCGR3);
163 reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
164 writel(reg, &mxc_ccm->CCGR3);
165
166 /* set LDB0, LDB1 clk select to 011/011 */
167 reg = readl(&mxc_ccm->cs2cdr);
168 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
169 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
170 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
171 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
172 writel(reg, &mxc_ccm->cs2cdr);
173
174 reg = readl(&mxc_ccm->cscmr2);
175 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
176 writel(reg, &mxc_ccm->cscmr2);
177
178 reg = readl(&mxc_ccm->chsccdr);
179 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
180 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
181 writel(reg, &mxc_ccm->chsccdr);
182
183 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
184 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
185 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
186 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
187 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
188 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
189 IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
190 IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
191 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
192 writel(reg, &iomux->gpr[2]);
193
194 reg = readl(&iomux->gpr[3]);
195 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
196 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
197 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
198 writel(reg, &iomux->gpr[3]);
199 }
200 #endif /* CONFIG_VIDEO_IPUV3 */
201
202 int board_early_init_f(void)
203 {
204 SETUP_IOMUX_PADS(uart4_pads);
205
206 return 0;
207 }
208
209 #ifdef CONFIG_ENV_IS_IN_MMC
210 static void mmc_late_init(void)
211 {
212 char cmd[32];
213 char mmcblk[32];
214 u32 dev_no = mmc_get_env_dev();
215
216 setenv_ulong("mmcdev", dev_no);
217
218 /* Set mmcblk env */
219 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
220 setenv("mmcroot", mmcblk);
221
222 sprintf(cmd, "mmc dev %d", dev_no);
223 run_command(cmd, 0);
224 }
225 #endif
226
227 int board_late_init(void)
228 {
229 switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
230 IMX6_BMODE_SHIFT) {
231 case IMX6_BMODE_SD:
232 case IMX6_BMODE_ESD:
233 #ifdef CONFIG_ENV_IS_IN_MMC
234 mmc_late_init();
235 #endif
236 setenv("modeboot", "mmcboot");
237 break;
238 case IMX6_BMODE_NAND:
239 setenv("modeboot", "nandboot");
240 break;
241 default:
242 setenv("modeboot", "");
243 break;
244 }
245
246 return 0;
247 }
248
249 int board_init(void)
250 {
251 /* Address of boot parameters */
252 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
253
254 #ifdef CONFIG_NAND_MXS
255 setup_gpmi_nand();
256 #endif
257
258 #ifdef CONFIG_VIDEO_IPUV3
259 setup_display();
260 #endif
261
262 return 0;
263 }
264
265 int dram_init(void)
266 {
267 gd->ram_size = imx_ddr_size();
268
269 return 0;
270 }
271
272 #ifdef CONFIG_SPL_BUILD
273 #include <libfdt.h>
274 #include <spl.h>
275
276 #include <asm/arch/crm_regs.h>
277 #include <asm/arch/mx6-ddr.h>
278
279 /* MMC board initialization is needed till adding DM support in SPL */
280 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
281 #include <mmc.h>
282 #include <fsl_esdhc.h>
283
284 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
285 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
286 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
287
288 static iomux_v3_cfg_t const usdhc1_pads[] = {
289 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
290 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
291 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
292 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
293 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
294 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
295 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
296 };
297
298 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
299
300 struct fsl_esdhc_cfg usdhc_cfg[1] = {
301 {USDHC1_BASE_ADDR, 0, 4},
302 };
303
304 int board_mmc_getcd(struct mmc *mmc)
305 {
306 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
307 int ret = 0;
308
309 switch (cfg->esdhc_base) {
310 case USDHC1_BASE_ADDR:
311 ret = !gpio_get_value(USDHC1_CD_GPIO);
312 break;
313 }
314
315 return ret;
316 }
317
318 int board_mmc_init(bd_t *bis)
319 {
320 int i, ret;
321
322 /*
323 * According to the board_mmc_init() the following map is done:
324 * (U-boot device node) (Physical Port)
325 * mmc0 USDHC1
326 */
327 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
328 switch (i) {
329 case 0:
330 SETUP_IOMUX_PADS(usdhc1_pads);
331 gpio_direction_input(USDHC1_CD_GPIO);
332 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
333 break;
334 default:
335 printf("Warning - USDHC%d controller not supporting\n",
336 i + 1);
337 return 0;
338 }
339
340 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
341 if (ret) {
342 printf("Warning: failed to initialize mmc dev %d\n", i);
343 return ret;
344 }
345 }
346
347 return 0;
348 }
349 #endif
350
351 /*
352 * Driving strength:
353 * 0x30 == 40 Ohm
354 * 0x28 == 48 Ohm
355 */
356
357 #define IMX6DQ_DRIVE_STRENGTH 0x30
358 #define IMX6SDL_DRIVE_STRENGTH 0x28
359
360 /* configure MX6Q/DUAL mmdc DDR io registers */
361 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
362 .dram_sdqs0 = 0x28,
363 .dram_sdqs1 = 0x28,
364 .dram_sdqs2 = 0x28,
365 .dram_sdqs3 = 0x28,
366 .dram_sdqs4 = 0x28,
367 .dram_sdqs5 = 0x28,
368 .dram_sdqs6 = 0x28,
369 .dram_sdqs7 = 0x28,
370 .dram_dqm0 = 0x28,
371 .dram_dqm1 = 0x28,
372 .dram_dqm2 = 0x28,
373 .dram_dqm3 = 0x28,
374 .dram_dqm4 = 0x28,
375 .dram_dqm5 = 0x28,
376 .dram_dqm6 = 0x28,
377 .dram_dqm7 = 0x28,
378 .dram_cas = 0x30,
379 .dram_ras = 0x30,
380 .dram_sdclk_0 = 0x30,
381 .dram_sdclk_1 = 0x30,
382 .dram_reset = 0x30,
383 .dram_sdcke0 = 0x3000,
384 .dram_sdcke1 = 0x3000,
385 .dram_sdba2 = 0x00000000,
386 .dram_sdodt0 = 0x30,
387 .dram_sdodt1 = 0x30,
388 };
389
390 /* configure MX6Q/DUAL mmdc GRP io registers */
391 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
392 .grp_b0ds = 0x30,
393 .grp_b1ds = 0x30,
394 .grp_b2ds = 0x30,
395 .grp_b3ds = 0x30,
396 .grp_b4ds = 0x30,
397 .grp_b5ds = 0x30,
398 .grp_b6ds = 0x30,
399 .grp_b7ds = 0x30,
400 .grp_addds = 0x30,
401 .grp_ddrmode_ctl = 0x00020000,
402 .grp_ddrpke = 0x00000000,
403 .grp_ddrmode = 0x00020000,
404 .grp_ctlds = 0x30,
405 .grp_ddr_type = 0x000c0000,
406 };
407
408 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
409 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
410 .dram_sdclk_0 = 0x30,
411 .dram_sdclk_1 = 0x30,
412 .dram_cas = 0x30,
413 .dram_ras = 0x30,
414 .dram_reset = 0x30,
415 .dram_sdcke0 = 0x30,
416 .dram_sdcke1 = 0x30,
417 .dram_sdba2 = 0x00000000,
418 .dram_sdodt0 = 0x30,
419 .dram_sdodt1 = 0x30,
420 .dram_sdqs0 = 0x28,
421 .dram_sdqs1 = 0x28,
422 .dram_sdqs2 = 0x28,
423 .dram_sdqs3 = 0x28,
424 .dram_sdqs4 = 0x28,
425 .dram_sdqs5 = 0x28,
426 .dram_sdqs6 = 0x28,
427 .dram_sdqs7 = 0x28,
428 .dram_dqm0 = 0x28,
429 .dram_dqm1 = 0x28,
430 .dram_dqm2 = 0x28,
431 .dram_dqm3 = 0x28,
432 .dram_dqm4 = 0x28,
433 .dram_dqm5 = 0x28,
434 .dram_dqm6 = 0x28,
435 .dram_dqm7 = 0x28,
436 };
437
438 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
439 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
440 .grp_ddr_type = 0x000c0000,
441 .grp_ddrmode_ctl = 0x00020000,
442 .grp_ddrpke = 0x00000000,
443 .grp_addds = 0x30,
444 .grp_ctlds = 0x30,
445 .grp_ddrmode = 0x00020000,
446 .grp_b0ds = 0x28,
447 .grp_b1ds = 0x28,
448 .grp_b2ds = 0x28,
449 .grp_b3ds = 0x28,
450 .grp_b4ds = 0x28,
451 .grp_b5ds = 0x28,
452 .grp_b6ds = 0x28,
453 .grp_b7ds = 0x28,
454 };
455
456 /* mt41j256 */
457 static struct mx6_ddr3_cfg mt41j256 = {
458 .mem_speed = 1066,
459 .density = 2,
460 .width = 16,
461 .banks = 8,
462 .rowaddr = 13,
463 .coladdr = 10,
464 .pagesz = 2,
465 .trcd = 1375,
466 .trcmin = 4875,
467 .trasmin = 3500,
468 .SRT = 0,
469 };
470
471 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
472 .p0_mpwldectrl0 = 0x000E0009,
473 .p0_mpwldectrl1 = 0x0018000E,
474 .p1_mpwldectrl0 = 0x00000007,
475 .p1_mpwldectrl1 = 0x00000000,
476 .p0_mpdgctrl0 = 0x43280334,
477 .p0_mpdgctrl1 = 0x031C0314,
478 .p1_mpdgctrl0 = 0x4318031C,
479 .p1_mpdgctrl1 = 0x030C0258,
480 .p0_mprddlctl = 0x3E343A40,
481 .p1_mprddlctl = 0x383C3844,
482 .p0_mpwrdlctl = 0x40404440,
483 .p1_mpwrdlctl = 0x4C3E4446,
484 };
485
486 /* DDR 64bit */
487 static struct mx6_ddr_sysinfo mem_q = {
488 .ddr_type = DDR_TYPE_DDR3,
489 .dsize = 2,
490 .cs1_mirror = 0,
491 /* config for full 4GB range so that get_mem_size() works */
492 .cs_density = 32,
493 .ncs = 1,
494 .bi_on = 1,
495 .rtt_nom = 2,
496 .rtt_wr = 2,
497 .ralat = 5,
498 .walat = 0,
499 .mif3_mode = 3,
500 .rst_to_cke = 0x23,
501 .sde_to_rst = 0x10,
502 };
503
504 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
505 .p0_mpwldectrl0 = 0x001F0024,
506 .p0_mpwldectrl1 = 0x00110018,
507 .p1_mpwldectrl0 = 0x001F0024,
508 .p1_mpwldectrl1 = 0x00110018,
509 .p0_mpdgctrl0 = 0x4230022C,
510 .p0_mpdgctrl1 = 0x02180220,
511 .p1_mpdgctrl0 = 0x42440248,
512 .p1_mpdgctrl1 = 0x02300238,
513 .p0_mprddlctl = 0x44444A48,
514 .p1_mprddlctl = 0x46484A42,
515 .p0_mpwrdlctl = 0x38383234,
516 .p1_mpwrdlctl = 0x3C34362E,
517 };
518
519 /* DDR 64bit 1GB */
520 static struct mx6_ddr_sysinfo mem_dl = {
521 .dsize = 2,
522 .cs1_mirror = 0,
523 /* config for full 4GB range so that get_mem_size() works */
524 .cs_density = 32,
525 .ncs = 1,
526 .bi_on = 1,
527 .rtt_nom = 1,
528 .rtt_wr = 1,
529 .ralat = 5,
530 .walat = 0,
531 .mif3_mode = 3,
532 .rst_to_cke = 0x23,
533 .sde_to_rst = 0x10,
534 };
535
536 /* DDR 32bit 512MB */
537 static struct mx6_ddr_sysinfo mem_s = {
538 .dsize = 1,
539 .cs1_mirror = 0,
540 /* config for full 4GB range so that get_mem_size() works */
541 .cs_density = 32,
542 .ncs = 1,
543 .bi_on = 1,
544 .rtt_nom = 1,
545 .rtt_wr = 1,
546 .ralat = 5,
547 .walat = 0,
548 .mif3_mode = 3,
549 .rst_to_cke = 0x23,
550 .sde_to_rst = 0x10,
551 };
552
553 static void ccgr_init(void)
554 {
555 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
556
557 writel(0x00003F3F, &ccm->CCGR0);
558 writel(0x0030FC00, &ccm->CCGR1);
559 writel(0x000FC000, &ccm->CCGR2);
560 writel(0x3F300000, &ccm->CCGR3);
561 writel(0xFF00F300, &ccm->CCGR4);
562 writel(0x0F0000C3, &ccm->CCGR5);
563 writel(0x000003CC, &ccm->CCGR6);
564 }
565
566 static void gpr_init(void)
567 {
568 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
569
570 /* enable AXI cache for VDOA/VPU/IPU */
571 writel(0xF00000CF, &iomux->gpr[4]);
572 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
573 writel(0x007F007F, &iomux->gpr[6]);
574 writel(0x007F007F, &iomux->gpr[7]);
575 }
576
577 static void spl_dram_init(void)
578 {
579 if (is_mx6solo()) {
580 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
581 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
582 } else if (is_mx6dl()) {
583 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
584 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
585 } else if (is_mx6dq()) {
586 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
587 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
588 }
589
590 udelay(100);
591 }
592
593 void board_init_f(ulong dummy)
594 {
595 ccgr_init();
596
597 /* setup AIPS and disable watchdog */
598 arch_cpu_init();
599
600 gpr_init();
601
602 /* iomux */
603 board_early_init_f();
604
605 /* setup GP timer */
606 timer_init();
607
608 /* UART clocks enabled and gd valid - init serial console */
609 preloader_console_init();
610
611 /* DDR initialization */
612 spl_dram_init();
613
614 /* Clear the BSS. */
615 memset(__bss_start, 0, __bss_end - __bss_start);
616
617 /* load/boot image from boot device */
618 board_init_r(NULL, 0);
619 }
620 #endif
"Das U-Boot" Source Tree