board/esd/cms700/cms700.c

   1 /*
   2  * (C) Copyright 2005-2007
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <asm/io.h>
  27 #include <command.h>
  28 #include <malloc.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 extern void lxt971_no_sleep(void);
  33
  34 /* fpga configuration data - not compressed, generated by bin2c */
  35 const unsigned char fpgadata[] =
  36 {
  37 #include "fpgadata.c"
  38 };
  39 int filesize = sizeof(fpgadata);
  40
  41
  42 int board_early_init_f (void)
  43 {
  44         /*
  45          * IRQ 0-15  405GP internally generated; active high; level sensitive
  46          * IRQ 16    405GP internally generated; active low; level sensitive
  47          * IRQ 17-24 RESERVED
  48          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  49          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  50          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  51          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  52          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  53          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  54          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  55          */
  56         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  57         mtdcr(uicer, 0x00000000);       /* disable all ints */
  58         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
  59         mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
  60         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
  61         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
  62         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  63
  64         /*
  65          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
  66          */
  67         mtebc (epcr, 0xa8400000); /* ebc always driven */
  68
  69         /*
  70          * Reset CPLD via GPIO12 (CS3) pin
  71          */
  72         out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET);
  73         udelay(1000); /* wait 1ms */
  74         out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET);
  75         udelay(1000); /* wait 1ms */
  76
  77         return 0;
  78 }
  79
  80 int misc_init_r (void)
  81 {
  82         /* adjust flash start and offset */
  83         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  84         gd->bd->bi_flashoffset = 0;
  85
  86         /*
  87          * Setup and enable EEPROM write protection
  88          */
  89         out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
  90
  91         return (0);
  92 }
  93
  94
  95 /*
  96  * Check Board Identity:
  97  */
  98
  99 int checkboard (void)
 100 {
 101         char str[64];
 102         int flashcnt;
 103         int delay;
 104         volatile unsigned char *led_reg = (unsigned char *)((ulong)CONFIG_SYS_PLD_BASE + 0x1000);
 105         volatile unsigned char *ver_reg = (unsigned char *)((ulong)CONFIG_SYS_PLD_BASE + 0x1001);
 106
 107         puts ("Board: ");
 108
 109         if (getenv_r("serial#", str, sizeof(str))  == -1) {
 110                 puts ("### No HW ID - assuming CMS700");
 111         } else {
 112                 puts(str);
 113         }
 114
 115         printf(" (PLD-Version=%02d)\n", *ver_reg);
 116
 117         /*
 118          * Flash LEDs
 119          */
 120         for (flashcnt = 0; flashcnt < 3; flashcnt++) {
 121                 *led_reg = 0x00;        /* LEDs off */
 122                 for (delay = 0; delay < 100; delay++)
 123                         udelay(1000);
 124                 *led_reg = 0x0f;        /* LEDs on */
 125                 for (delay = 0; delay < 50; delay++)
 126                         udelay(1000);
 127         }
 128         *led_reg = 0x70;
 129
 130         return 0;
 131 }
 132
 133 /* ------------------------------------------------------------------------- */
 134
 135 #if defined(CONFIG_SYS_EEPROM_WREN)
 136 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 137  *         <state>     -1: deliver current state
 138  *                     0: disable write
 139  *                     1: enable write
 140  *  Returns:           -1: wrong device address
 141  *                      0: dis-/en- able done
 142  *                   0/1: current state if <state> was -1.
 143  */
 144 int eeprom_write_enable (unsigned dev_addr, int state)
 145 {
 146         if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 147                 return -1;
 148         } else {
 149                 switch (state) {
 150                 case 1:
 151                         /* Enable write access, clear bit GPIO_SINT2. */
 152                         out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
 153                         state = 0;
 154                         break;
 155                 case 0:
 156                         /* Disable write access, set bit GPIO_SINT2. */
 157                         out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 158                         state = 0;
 159                         break;
 160                 default:
 161                         /* Read current status back. */
 162                         state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
 163                         break;
 164                 }
 165         }
 166         return state;
 167 }
 168
 169 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 170 {
 171         int query = argc == 1;
 172         int state = 0;
 173
 174         if (query) {
 175                 /* Query write access state. */
 176                 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 177                 if (state < 0) {
 178                         puts ("Query of write access state failed.\n");
 179                 } else {
 180                         printf ("Write access for device 0x%0x is %sabled.\n",
 181                                 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 182                         state = 0;
 183                 }
 184         } else {
 185                 if ('0' == argv[1][0]) {
 186                         /* Disable write access. */
 187                         state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 188                 } else {
 189                         /* Enable write access. */
 190                         state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 191                 }
 192                 if (state < 0) {
 193                         puts ("Setup of write access state failed.\n");
 194                 }
 195         }
 196
 197         return state;
 198 }
 199
 200 U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 201            "eepwren - Enable / disable / query EEPROM write access\n",
 202            NULL);
 203 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 204
 205 /* ------------------------------------------------------------------------- */
 206
 207 void reset_phy(void)
 208 {
 209 #ifdef CONFIG_LXT971_NO_SLEEP
 210
 211         /*
 212          * Disable sleep mode in LXT971
 213          */
 214         lxt971_no_sleep();
 215 #endif
 216 }