board/esd/cms700/cms700.c

   1 /*
   2  * (C) Copyright 2005
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <command.h>
  27 #include <malloc.h>
  28
  29
  30 extern void lxt971_no_sleep(void);
  31
  32
  33 /* fpga configuration data - not compressed, generated by bin2c */
  34 const unsigned char fpgadata[] =
  35 {
  36 #include "fpgadata.c"
  37 };
  38 int filesize = sizeof(fpgadata);
  39
  40
  41 int board_early_init_f (void)
  42 {
  43         /*
  44          * IRQ 0-15  405GP internally generated; active high; level sensitive
  45          * IRQ 16    405GP internally generated; active low; level sensitive
  46          * IRQ 17-24 RESERVED
  47          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  48          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  49          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  50          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  51          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  52          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  53          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  54          */
  55         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  56         mtdcr(uicer, 0x00000000);       /* disable all ints */
  57         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
  58         mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
  59         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
  60         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
  61         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  62
  63         /*
  64          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
  65          */
  66         mtebc (epcr, 0xa8400000); /* ebc always driven */
  67
  68         /*
  69          * Reset CPLD via GPIO12 (CS3) pin
  70          */
  71         out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
  72         udelay(1000); /* wait 1ms */
  73         out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
  74         udelay(1000); /* wait 1ms */
  75
  76         return 0;
  77 }
  78
  79
  80 /* ------------------------------------------------------------------------- */
  81
  82 int misc_init_f (void)
  83 {
  84         return 0;  /* dummy implementation */
  85 }
  86
  87
  88 int misc_init_r (void)
  89 {
  90         DECLARE_GLOBAL_DATA_PTR;
  91
  92         /* adjust flash start and offset */
  93         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  94         gd->bd->bi_flashoffset = 0;
  95
  96         /*
  97          * Setup and enable EEPROM write protection
  98          */
  99         out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
 100
 101         /*
 102          * Set NAND-FLASH GPIO signals to default
 103          */
 104         out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
 105         out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
 106
 107         return (0);
 108 }
 109
 110
 111 /*
 112  * Check Board Identity:
 113  */
 114
 115 int checkboard (void)
 116 {
 117         char str[64];
 118         int flashcnt;
 119         int delay;
 120         volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000);
 121         volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001);
 122
 123         puts ("Board: ");
 124
 125         if (getenv_r("serial#", str, sizeof(str))  == -1) {
 126                 puts ("### No HW ID - assuming CMS700");
 127         } else {
 128                 puts(str);
 129         }
 130
 131         printf(" (PLD-Version=%02d)\n", *ver_reg);
 132
 133         /*
 134          * Flash LEDs
 135          */
 136         for (flashcnt = 0; flashcnt < 3; flashcnt++) {
 137                 *led_reg = 0x00;        /* LEDs off */
 138                 for (delay = 0; delay < 100; delay++)
 139                         udelay(1000);
 140                 *led_reg = 0x0f;        /* LEDs on */
 141                 for (delay = 0; delay < 50; delay++)
 142                         udelay(1000);
 143         }
 144         *led_reg = 0x70;
 145
 146         return 0;
 147 }
 148
 149 /* ------------------------------------------------------------------------- */
 150
 151 long int initdram (int board_type)
 152 {
 153         unsigned long val;
 154
 155         mtdcr(memcfga, mem_mb0cf);
 156         val = mfdcr(memcfgd);
 157
 158 #if 0
 159         printf("\nmb0cf=%x\n", val); /* test-only */
 160         printf("strap=%x\n", mfdcr(strap)); /* test-only */
 161 #endif
 162
 163         return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 164 }
 165
 166 /* ------------------------------------------------------------------------- */
 167
 168 #if defined(CFG_EEPROM_WREN)
 169 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 170  *         <state>     -1: deliver current state
 171  *                     0: disable write
 172  *                     1: enable write
 173  *  Returns:           -1: wrong device address
 174  *                      0: dis-/en- able done
 175  *                   0/1: current state if <state> was -1.
 176  */
 177 int eeprom_write_enable (unsigned dev_addr, int state)
 178 {
 179         if (CFG_I2C_EEPROM_ADDR != dev_addr) {
 180                 return -1;
 181         } else {
 182                 switch (state) {
 183                 case 1:
 184                         /* Enable write access, clear bit GPIO_SINT2. */
 185                         out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
 186                         state = 0;
 187                         break;
 188                 case 0:
 189                         /* Disable write access, set bit GPIO_SINT2. */
 190                         out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
 191                         state = 0;
 192                         break;
 193                 default:
 194                         /* Read current status back. */
 195                         state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
 196                         break;
 197                 }
 198         }
 199         return state;
 200 }
 201
 202 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 203 {
 204         int query = argc == 1;
 205         int state = 0;
 206
 207         if (query) {
 208                 /* Query write access state. */
 209                 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
 210                 if (state < 0) {
 211                         puts ("Query of write access state failed.\n");
 212                 } else {
 213                         printf ("Write access for device 0x%0x is %sabled.\n",
 214                                 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
 215                         state = 0;
 216                 }
 217         } else {
 218                 if ('0' == argv[1][0]) {
 219                         /* Disable write access. */
 220                         state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
 221                 } else {
 222                         /* Enable write access. */
 223                         state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
 224                 }
 225                 if (state < 0) {
 226                         puts ("Setup of write access state failed.\n");
 227                 }
 228         }
 229
 230         return state;
 231 }
 232
 233 U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 234            "eepwren - Enable / disable / query EEPROM write access\n",
 235            NULL);
 236 #endif /* #if defined(CFG_EEPROM_WREN) */
 237
 238 /* ------------------------------------------------------------------------- */
 239
 240 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 241 #include <linux/mtd/nand_legacy.h>
 242 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 243
 244 void nand_init(void)
 245 {
 246         nand_probe(CFG_NAND_BASE);
 247         if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 248                 print_size(nand_dev_desc[0].totlen, "\n");
 249         }
 250 }
 251 #endif
 252
 253 void reset_phy(void)
 254 {
 255 #ifdef CONFIG_LXT971_NO_SLEEP
 256
 257         /*
 258          * Disable sleep mode in LXT971
 259          */
 260         lxt971_no_sleep();
 261 #endif
 262 }