board/esd/cms700/cms700.c

   1 /*
   2  * (C) Copyright 2005-2007
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <asm/io.h>
  27 #include <command.h>
  28 #include <malloc.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 extern void lxt971_no_sleep(void);
  33
  34 /* fpga configuration data - not compressed, generated by bin2c */
  35 const unsigned char fpgadata[] =
  36 {
  37 #include "fpgadata.c"
  38 };
  39 int filesize = sizeof(fpgadata);
  40
  41
  42 int board_early_init_f (void)
  43 {
  44         /*
  45          * IRQ 0-15  405GP internally generated; active high; level sensitive
  46          * IRQ 16    405GP internally generated; active low; level sensitive
  47          * IRQ 17-24 RESERVED
  48          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  49          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  50          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  51          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  52          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  53          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  54          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  55          */
  56         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  57         mtdcr(uicer, 0x00000000);       /* disable all ints */
  58         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
  59         mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
  60         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
  61         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
  62         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  63
  64         /*
  65          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
  66          */
  67         mtebc (epcr, 0xa8400000); /* ebc always driven */
  68
  69         /*
  70          * Reset CPLD via GPIO12 (CS3) pin
  71          */
  72         out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET);
  73         udelay(1000); /* wait 1ms */
  74         out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET);
  75         udelay(1000); /* wait 1ms */
  76
  77         return 0;
  78 }
  79
  80
  81 /* ------------------------------------------------------------------------- */
  82
  83 int misc_init_f (void)
  84 {
  85         return 0;  /* dummy implementation */
  86 }
  87
  88
  89 int misc_init_r (void)
  90 {
  91         /* adjust flash start and offset */
  92         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  93         gd->bd->bi_flashoffset = 0;
  94
  95         /*
  96          * Setup and enable EEPROM write protection
  97          */
  98         out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
  99
 100         return (0);
 101 }
 102
 103
 104 /*
 105  * Check Board Identity:
 106  */
 107
 108 int checkboard (void)
 109 {
 110         char str[64];
 111         int flashcnt;
 112         int delay;
 113         volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000);
 114         volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001);
 115
 116         puts ("Board: ");
 117
 118         if (getenv_r("serial#", str, sizeof(str))  == -1) {
 119                 puts ("### No HW ID - assuming CMS700");
 120         } else {
 121                 puts(str);
 122         }
 123
 124         printf(" (PLD-Version=%02d)\n", *ver_reg);
 125
 126         /*
 127          * Flash LEDs
 128          */
 129         for (flashcnt = 0; flashcnt < 3; flashcnt++) {
 130                 *led_reg = 0x00;        /* LEDs off */
 131                 for (delay = 0; delay < 100; delay++)
 132                         udelay(1000);
 133                 *led_reg = 0x0f;        /* LEDs on */
 134                 for (delay = 0; delay < 50; delay++)
 135                         udelay(1000);
 136         }
 137         *led_reg = 0x70;
 138
 139         return 0;
 140 }
 141
 142 /* ------------------------------------------------------------------------- */
 143
 144 long int initdram (int board_type)
 145 {
 146         unsigned long val;
 147
 148         mtdcr(memcfga, mem_mb0cf);
 149         val = mfdcr(memcfgd);
 150
 151         return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 152 }
 153
 154 /* ------------------------------------------------------------------------- */
 155
 156 #if defined(CFG_EEPROM_WREN)
 157 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 158  *         <state>     -1: deliver current state
 159  *                     0: disable write
 160  *                     1: enable write
 161  *  Returns:           -1: wrong device address
 162  *                      0: dis-/en- able done
 163  *                   0/1: current state if <state> was -1.
 164  */
 165 int eeprom_write_enable (unsigned dev_addr, int state)
 166 {
 167         if (CFG_I2C_EEPROM_ADDR != dev_addr) {
 168                 return -1;
 169         } else {
 170                 switch (state) {
 171                 case 1:
 172                         /* Enable write access, clear bit GPIO_SINT2. */
 173                         out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP);
 174                         state = 0;
 175                         break;
 176                 case 0:
 177                         /* Disable write access, set bit GPIO_SINT2. */
 178                         out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
 179                         state = 0;
 180                         break;
 181                 default:
 182                         /* Read current status back. */
 183                         state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP));
 184                         break;
 185                 }
 186         }
 187         return state;
 188 }
 189
 190 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 191 {
 192         int query = argc == 1;
 193         int state = 0;
 194
 195         if (query) {
 196                 /* Query write access state. */
 197                 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
 198                 if (state < 0) {
 199                         puts ("Query of write access state failed.\n");
 200                 } else {
 201                         printf ("Write access for device 0x%0x is %sabled.\n",
 202                                 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
 203                         state = 0;
 204                 }
 205         } else {
 206                 if ('0' == argv[1][0]) {
 207                         /* Disable write access. */
 208                         state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
 209                 } else {
 210                         /* Enable write access. */
 211                         state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
 212                 }
 213                 if (state < 0) {
 214                         puts ("Setup of write access state failed.\n");
 215                 }
 216         }
 217
 218         return state;
 219 }
 220
 221 U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 222            "eepwren - Enable / disable / query EEPROM write access\n",
 223            NULL);
 224 #endif /* #if defined(CFG_EEPROM_WREN) */
 225
 226 /* ------------------------------------------------------------------------- */
 227
 228 void reset_phy(void)
 229 {
 230 #ifdef CONFIG_LXT971_NO_SLEEP
 231
 232         /*
 233          * Disable sleep mode in LXT971
 234          */
 235         lxt971_no_sleep();
 236 #endif
 237 }