board/esd/du440/init.S

   1 /*
   2  * (C) Copyright 2008
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <ppc_asm.tmpl>
  25 #include <asm-ppc/mmu.h>
  26 #include <config.h>
  27
  28 /*
  29  * TLB TABLE
  30  *
  31  * This table is used by the cpu boot code to setup the initial tlb
  32  * entries. Rather than make broad assumptions in the cpu source tree,
  33  * this table lets each board set things up however they like.
  34  *
  35  * Pointer to the table is returned in r1
  36  */
  37     .section .bootpg,"ax"
  38     .globl tlbtab
  39
  40 tlbtab:
  41         tlbtab_start
  42
  43         /*
  44          * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
  45          * speed up boot process. It is patched after relocation to enable SA_I
  46          */
  47         tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
  48
  49 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
  50         /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
  51         tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
  52 #endif
  53
  54         /* TLB-entry for PCI Memory */
  55         tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M,  CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
  56         tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
  57         tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
  58         tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
  59
  60         /* TLB-entry for PCI IO */
  61         tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I )
  62
  63         /* TLB-entries for EBC:  CPLD, DUMEM, DUIO */
  64         tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
  65         tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
  66         tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
  67
  68         /* TLB-entry for NAND */
  69         tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
  70         tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
  71
  72         /* TLB-entry for Internal Registers & OCM */
  73         tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I )
  74
  75         /* TLB-entry PCI registers */
  76         tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_R|AC_W|AC_X|SA_G|SA_I )
  77
  78         /* TLB-entry for peripherals */
  79         tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
  80
  81         tlbtab_end