board/faraday/a320evb/lowlevel_init.S

   1 /*
   2  * (C) Copyright 2009 Faraday Technology
   3  * Po-Yu Chuang <ratbert@faraday-tech.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <config.h>
  21 #include <version.h>
  22
  23 #include <asm/macro.h>
  24 #include <faraday/ftsdmc020.h>
  25
  26 /*
  27  * parameters for the SDRAM controller
  28  */
  29 #define TP0_A           (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
  30 #define TP1_A           (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
  31 #define CR_A            (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
  32 #define B0_BSR_A        (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
  33 #define ACR_A           (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
  34
  35 #define TP0_D           CONFIG_SYS_FTSDMC020_TP0
  36 #define TP1_D           CONFIG_SYS_FTSDMC020_TP1
  37 #define CR_D1           FTSDMC020_CR_IPREC
  38 #define CR_D2           FTSDMC020_CR_ISMR
  39 #define CR_D3           FTSDMC020_CR_IREF
  40
  41 #define B0_BSR_D        (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
  42                         FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
  43 #define ACR_D           FTSDMC020_ACR_TOC(0x18)
  44
  45 /*
  46  * numeric 7 segment display
  47  */
  48 .macro  led, num
  49         write32 CONFIG_DEBUG_LED, \num
  50 .endm
  51
  52 /*
  53  * Waiting for SDRAM to set up
  54  */
  55 .macro  wait_sdram
  56         ldr     r0, =CONFIG_FTSDMC020_BASE
  57 1:
  58         ldr     r1, [r0, #FTSDMC020_OFFSET_CR]
  59         cmp     r1, #0
  60         bne     1b
  61 .endm
  62
  63 .globl lowlevel_init
  64 lowlevel_init:
  65         mov     r11, lr
  66
  67         led     0x0
  68
  69         bl      init_sdmc
  70
  71         led     0x1
  72
  73         /* everything is fine now */
  74         mov     lr, r11
  75         mov     pc, lr
  76
  77 /*
  78  * memory initialization
  79  */
  80 init_sdmc:
  81         led     0x10
  82
  83         /* set SDRAM register */
  84
  85         write32 TP0_A, TP0_D
  86         led     0x11
  87
  88         write32 TP1_A, TP1_D
  89         led     0x12
  90
  91         /* set to precharge */
  92         write32 CR_A, CR_D1
  93         led     0x13
  94
  95         wait_sdram
  96         led     0x14
  97
  98         /* set mode register */
  99         write32 CR_A, CR_D2
 100         led     0x15
 101
 102         wait_sdram
 103         led     0x16
 104
 105         /* set to refresh */
 106         write32 CR_A, CR_D3
 107         led     0x17
 108
 109         wait_sdram
 110         led     0x18
 111
 112         write32 B0_BSR_A, B0_BSR_D
 113         led     0x19
 114
 115         write32 ACR_A, ACR_D
 116         led     0x1a
 117
 118         mov     pc, lr