board/freescale/m5235evb/mii.c

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/fec.h>
  26 #include <asm/immap.h>
  27
  28 #include <config.h>
  29 #include <net.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
  34 #undef MII_DEBUG
  35 #undef ET_DEBUG
  36
  37 int fecpin_setclear(struct eth_device *dev, int setclear)
  38 {
  39         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  40
  41         if (setclear) {
  42                 gpio->par_feci2c |=
  43                     (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
  44         } else {
  45                 gpio->par_feci2c &=
  46                     ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
  47         }
  48
  49         return 0;
  50 }
  51
  52 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII)
  53 #include <miiphy.h>
  54
  55 /* Make MII read/write commands for the FEC. */
  56 #define mk_mii_read(ADDR, REG)  (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
  57
  58 #define mk_mii_write(ADDR, REG, VAL)    (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
  59
  60 /* PHY identification */
  61 #define PHY_ID_LXT970           0x78100000      /* LXT970 */
  62 #define PHY_ID_LXT971           0x001378e0      /* LXT971 and 972 */
  63 #define PHY_ID_82555            0x02a80150      /* Intel 82555 */
  64 #define PHY_ID_QS6612           0x01814400      /* QS6612 */
  65 #define PHY_ID_AMD79C784        0x00225610      /* AMD 79C784 */
  66 #define PHY_ID_LSI80225         0x0016f870      /* LSI 80225 */
  67 #define PHY_ID_LSI80225B        0x0016f880      /* LSI 80225/B */
  68 #define PHY_ID_DP83848VV        0x20005C90      /* National 83848 */
  69 #define PHY_ID_DP83849          0x20005CA2      /* National 82849 */
  70 #define PHY_ID_KS8721BL         0x00221619      /* Micrel KS8721BL/SL */
  71
  72 #define STR_ID_LXT970           "LXT970"
  73 #define STR_ID_LXT971           "LXT971"
  74 #define STR_ID_82555            "Intel82555"
  75 #define STR_ID_QS6612           "QS6612"
  76 #define STR_ID_AMD79C784        "AMD79C784"
  77 #define STR_ID_LSI80225         "LSI80225"
  78 #define STR_ID_LSI80225B        "LSI80225/B"
  79 #define STR_ID_DP83848VV        "N83848"
  80 #define STR_ID_DP83849          "N83849"
  81 #define STR_ID_KS8721BL         "KS8721BL"
  82
  83 /****************************************************************************
  84  * mii_init -- Initialize the MII for MII command without ethernet
  85  * This function is a subset of eth_init
  86  ****************************************************************************
  87  */
  88 void mii_reset(struct fec_info_s *info)
  89 {
  90         volatile fec_t *fecp = (fec_t *) (info->miibase);
  91         int i;
  92
  93         fecp->ecr = FEC_ECR_RESET;
  94         for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
  95                 udelay(1);
  96         }
  97         if (i == FEC_RESET_DELAY) {
  98                 printf("FEC_RESET_DELAY timeout\n");
  99         }
 100 }
 101
 102 /* send command to phy using mii, wait for result */
 103 uint mii_send(uint mii_cmd)
 104 {
 105         struct fec_info_s *info;
 106         struct eth_device *dev;
 107         volatile fec_t *ep;
 108         uint mii_reply;
 109         int j = 0;
 110
 111         /* retrieve from register structure */
 112         dev = eth_get_dev();
 113         info = dev->priv;
 114
 115         ep = (fec_t *) info->miibase;
 116
 117         ep->mmfr = mii_cmd;     /* command to phy */
 118
 119         /* wait for mii complete */
 120         while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
 121                 udelay(1);
 122                 j++;
 123         }
 124         if (j >= MCFFEC_TOUT_LOOP) {
 125                 printf("MII not complete\n");
 126                 return -1;
 127         }
 128
 129         mii_reply = ep->mmfr;   /* result from phy */
 130         ep->eir = FEC_EIR_MII;  /* clear MII complete */
 131 #ifdef ET_DEBUG
 132         printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
 133                __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
 134 #endif
 135
 136         return (mii_reply & 0xffff);    /* data read from phy */
 137 }
 138 #endif                          /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
 139
 140 #if defined(CONFIG_SYS_DISCOVER_PHY)
 141 int mii_discover_phy(struct eth_device *dev)
 142 {
 143 #define MAX_PHY_PASSES 11
 144         struct fec_info_s *info = dev->priv;
 145         int phyaddr, pass;
 146         uint phyno, phytype;
 147
 148         if (info->phyname_init)
 149                 return info->phy_addr;
 150
 151         phyaddr = -1;           /* didn't find a PHY yet */
 152         for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
 153                 if (pass > 1) {
 154                         /* PHY may need more time to recover from reset.
 155                          * The LXT970 needs 50ms typical, no maximum is
 156                          * specified, so wait 10ms before try again.
 157                          * With 11 passes this gives it 100ms to wake up.
 158                          */
 159                         udelay(10000);  /* wait 10ms */
 160                 }
 161
 162                 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
 163
 164                         phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
 165 #ifdef ET_DEBUG
 166                         printf("PHY type 0x%x pass %d type\n", phytype, pass);
 167 #endif
 168                         if (phytype != 0xffff) {
 169                                 phyaddr = phyno;
 170                                 phytype <<= 16;
 171                                 phytype |=
 172                                     mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
 173
 174                                 switch (phytype & 0xffffffff) {
 175                                 case PHY_ID_KS8721BL:
 176                                         strcpy(info->phy_name,
 177                                                STR_ID_KS8721BL);
 178                                         info->phyname_init = 1;
 179                                         break;
 180                                 default:
 181                                         strcpy(info->phy_name, "unknown");
 182                                         info->phyname_init = 1;
 183                                         break;
 184                                 }
 185
 186 #ifdef ET_DEBUG
 187                                 printf("PHY @ 0x%x pass %d type ", phyno, pass);
 188                                 switch (phytype & 0xffffffff) {
 189                                 case PHY_ID_KS8721BL:
 190                                         printf(STR_ID_KS8721BL);
 191                                         break;
 192                                 default:
 193                                         printf("0x%08x\n", phytype);
 194                                         break;
 195                                 }
 196 #endif
 197                         }
 198                 }
 199         }
 200         if (phyaddr < 0)
 201                 printf("No PHY device found.\n");
 202
 203         return phyaddr;
 204 }
 205 #endif                          /* CONFIG_SYS_DISCOVER_PHY */
 206
 207 void mii_init(void) __attribute__((weak,alias("__mii_init")));
 208
 209 void __mii_init(void)
 210 {
 211         volatile fec_t *fecp;
 212         struct fec_info_s *info;
 213         struct eth_device *dev;
 214         int miispd = 0, i = 0;
 215         u16 autoneg = 0;
 216
 217         /* retrieve from register structure */
 218         dev = eth_get_dev();
 219         info = dev->priv;
 220
 221         fecp = (fec_t *) info->miibase;
 222
 223         fecpin_setclear(dev, 1);
 224
 225         mii_reset(info);
 226
 227         /* We use strictly polling mode only */
 228         fecp->eimr = 0;
 229
 230         /* Clear any pending interrupt */
 231         fecp->eir = 0xffffffff;
 232
 233         /* Set MII speed */
 234         miispd = (gd->bus_clk / 1000000) / 5;
 235         fecp->mscr = miispd << 1;
 236
 237         info->phy_addr = mii_discover_phy(dev);
 238
 239 #define AUTONEGLINK             (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
 240         while (i < MCFFEC_TOUT_LOOP) {
 241                 autoneg = 0;
 242                 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
 243                 i++;
 244
 245                 if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
 246                         break;
 247
 248                 udelay(500);
 249         }
 250         if (i >= MCFFEC_TOUT_LOOP) {
 251                 printf("Auto Negotiation not complete\n");
 252         }
 253
 254         /* adapt to the half/full speed settings */
 255         info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
 256         info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
 257 }
 258
 259 /*****************************************************************************
 260  * Read and write a MII PHY register, routines used by MII Utilities
 261  *
 262  * FIXME: These routines are expected to return 0 on success, but mii_send
 263  *        does _not_ return an error code. Maybe 0xFFFF means error, i.e.
 264  *        no PHY connected...
 265  *        For now always return 0.
 266  * FIXME: These routines only work after calling eth_init() at least once!
 267  *        Otherwise they hang in mii_send() !!! Sorry!
 268  *****************************************************************************/
 269
 270 int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
 271                        unsigned short *value)
 272 {
 273         short rdreg;            /* register working value */
 274
 275 #ifdef MII_DEBUG
 276         printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
 277 #endif
 278         rdreg = mii_send(mk_mii_read(addr, reg));
 279
 280         *value = rdreg;
 281
 282 #ifdef MII_DEBUG
 283         printf("0x%04x\n", *value);
 284 #endif
 285
 286         return 0;
 287 }
 288
 289 int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
 290                         unsigned short value)
 291 {
 292         short rdreg;            /* register working value */
 293
 294 #ifdef MII_DEBUG
 295         printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
 296 #endif
 297
 298         rdreg = mii_send(mk_mii_write(addr, reg, value));
 299
 300 #ifdef MII_DEBUG
 301         printf("0x%04x\n", value);
 302 #endif
 303
 304         return 0;
 305 }
 306
 307 #endif                          /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */