board/freescale/p2041rdb/cpld.h

   1 /**
   2  * Copyright 2011 Freescale Semiconductor
   3  * Author: Mingkai Hu <Mingkai.hu@freescale.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the Free
   7  * Software Foundation; either version 2 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * This file provides support for the ngPIXIS, a board-specific FPGA used on
  11  * some Freescale reference boards.
  12  */
  13
  14 /*
  15  * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
  16  */
  17 typedef struct cpld_data {
  18         u8 cpld_ver;            /* 0x0 - CPLD Major Revision Register */
  19         u8 cpld_ver_sub;        /* 0x1 - CPLD Minor Revision Register */
  20         u8 pcba_ver;            /* 0x2 - PCBA Revision Register */
  21         u8 system_rst;          /* 0x3 - system reset register */
  22         u8 res0;                /* 0x4 - not used */
  23         u8 sw_ctl_on;           /* 0x5 - Switch Control Enable Register */
  24         u8 por_cfg;             /* 0x6 - POR Control Register */
  25         u8 switch_strobe;       /* 0x7 - Multiplexed pin Select Register */
  26         u8 jtag_sel;            /* 0x8 - JTAG or AURORA Selection */
  27         u8 sdbank1_clk;         /* 0x9 - SerDes Bank1 Reference clock */
  28         u8 sdbank2_clk;         /* 0xa - SerDes Bank2 Reference clock */
  29         u8 fbank_sel;           /* 0xb - Flash bank selection */
  30         u8 serdes_mux;          /* 0xc - Multiplexed pin Select Register */
  31         u8 sw[1];               /* 0xd - SW2 Status */
  32         u8 system_rst_default;  /* 0xe - system reset to default register */
  33         u8 sysclk_sw1;          /* 0xf - sysclk configuration register */
  34 } __attribute__ ((packed)) cpld_data_t;
  35
  36 #define SERDES_MUX_LANE_6_MASK  0x2
  37 #define SERDES_MUX_LANE_6_SHIFT 1
  38 #define SERDES_MUX_LANE_A_MASK  0x1
  39 #define SERDES_MUX_LANE_A_SHIFT 0
  40 #define SERDES_MUX_LANE_C_MASK  0x4
  41 #define SERDES_MUX_LANE_C_SHIFT 2
  42 #define SERDES_MUX_LANE_D_MASK  0x8
  43 #define SERDES_MUX_LANE_D_SHIFT 3
  44 #define CPLD_SWITCH_BANK_ENABLE 0x40
  45 #define CPLD_SYSCLK_83          0x1     /* system clock 83.3MHz */
  46 #define CPLD_SYSCLK_100         0x2     /* system clock 100MHz */
  47
  48 /* Pointer to the CPLD register set */
  49 #define cpld ((cpld_data_t *)CPLD_BASE)
  50
  51 /* The CPLD SW register that corresponds to board switch X, where x >= 1 */
  52 #define CPLD_SW(x)              (cpld->sw[(x) - 2])
  53
  54 u8 cpld_read(unsigned int reg);
  55 void cpld_write(unsigned int reg, u8 value);
  56
  57 #define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg))
  58 #define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value)