board/kup/kup4k/kup4k.c

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <command.h>
  27 #include <libfdt.h>
  28 #include <mpc8xx.h>
  29 #include <hwconfig.h>
  30 #include <i2c.h>
  31 #include "../common/kup.h"
  32 #include <asm/io.h>
  33
  34 static unsigned char swapbyte(unsigned char c);
  35 static int read_diag(void);
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 /* ----------------------------------------------------------------------- */
  40
  41 #define _NOT_USED_      0xFFFFFFFF
  42
  43 const uint sdram_table[] = {
  44         /*
  45          * Single Read. (Offset 0 in UPMA RAM)
  46          */
  47         0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
  48         0x1FF77C47,             /* last */
  49
  50         /*
  51          * SDRAM Initialization (offset 5 in UPMA RAM)
  52          *
  53          * This is no UPM entry point. The following definition uses
  54          * the remaining space to establish an initialization
  55          * sequence, which is executed by a RUN command.
  56          *
  57          */
  58         0x1FF77C35, 0xEFEABC34, 0x1FB57C35,     /* last */
  59
  60         /*
  61          * Burst Read. (Offset 8 in UPMA RAM)
  62          */
  63         0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
  64         0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
  65         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  66         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  67
  68         /*
  69          * Single Write. (Offset 18 in UPMA RAM)
  70          */
  71         0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
  72         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  73
  74         /*
  75          * Burst Write. (Offset 20 in UPMA RAM)
  76          */
  77         0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
  78         0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47,     /* last */
  79         _NOT_USED_,
  80         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  81         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  82
  83         /*
  84          * Refresh  (Offset 30 in UPMA RAM)
  85          */
  86         0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  87         0xFFFFFC84, 0xFFFFFC07, /* last */
  88         _NOT_USED_, _NOT_USED_,
  89         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  90
  91         /*
  92          * Exception. (Offset 3c in UPMA RAM)
  93          */
  94         0x7FFFFC07,             /* last */
  95         _NOT_USED_, _NOT_USED_, _NOT_USED_,
  96 };
  97
  98 /* ----------------------------------------------------------------------- */
  99
 100 /*
 101  * Check Board Identity:
 102  */
 103
 104 int checkboard(void)
 105 {
 106         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 107         uchar rev,mod,tmp,pcf,ak_rev,ak_mod;
 108
 109         /*
 110          * Init ChipSelect #4 (CAN + HW-Latch)
 111          */
 112         out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
 113         out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
 114
 115         /*
 116          * Init ChipSelect #5 (S1D13768)
 117          */
 118         out_be32(&immap->im_memctl.memc_or5, CONFIG_SYS_OR5);
 119         out_be32(&immap->im_memctl.memc_br5, CONFIG_SYS_BR5);
 120
 121         tmp = swapbyte(in_8((unsigned char*) LATCH_ADDR));
 122         rev = (tmp & 0xF8) >> 3;
 123         mod = (tmp & 0x07);
 124
 125         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 126
 127         if (read_diag())
 128                 gd->flags &= ~GD_FLG_SILENT;
 129
 130         printf("Board: KUP4K Rev %d.%d AK:",rev,mod);
 131         /*
 132          * TI Application report: Before using the IO as an input,
 133          * a high must be written to the IO first
 134          */
 135         pcf = 0xFF;
 136         i2c_write(0x21, 0, 0 , &pcf, 1);
 137         if (i2c_read(0x21, 0, 0, &pcf, 1)) {
 138                 puts("n/a\n");
 139         } else {
 140                 ak_rev = (pcf & 0xF8) >> 3;
 141                 ak_mod = (pcf & 0x07);
 142                 printf("%d.%d\n", ak_rev, ak_mod);
 143         }
 144         return 0;
 145 }
 146
 147 /* ----------------------------------------------------------------------- */
 148
 149
 150 phys_size_t initdram(int board_type)
 151 {
 152         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 153         volatile memctl8xx_t *memctl = &immap->im_memctl;
 154         long int size = 0;
 155         uchar *latch, rev, tmp;
 156
 157         /*
 158          * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision
 159          * Rev 1..6 -> 48 MB RAM;   Rev >= 7 -> 96 MB
 160          */
 161         out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
 162         out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
 163
 164         latch = (uchar *)0x90000200;
 165         tmp = swapbyte(*latch);
 166         rev = (tmp & 0xF8) >> 3;
 167
 168         upmconfig(UPMA, (uint *) sdram_table,
 169                    sizeof (sdram_table) / sizeof (uint));
 170
 171         out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
 172
 173         out_be32(&memctl->memc_mar, 0x00000088);
 174         /* no refresh yet */
 175         if(rev >= 7) {
 176                 out_be32(&memctl->memc_mamr,
 177                                  CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)));
 178         } else {
 179                 out_be32(&memctl->memc_mamr,
 180                                  CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)));
 181         }
 182
 183         udelay(200);
 184
 185         /* perform SDRAM initializsation sequence */
 186
 187         /* SDRAM bank 0 */
 188         out_be32(&memctl->memc_mcr, 0x80002105);
 189         udelay(1);
 190         out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
 191         udelay(1);
 192         out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
 193         udelay(1);
 194
 195         /* SDRAM bank 1 */
 196         out_be32(&memctl->memc_mcr, 0x80004105);
 197         udelay(1);
 198         out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
 199         udelay(1);
 200         out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
 201         udelay(1);
 202
 203         /* SDRAM bank 2 */
 204         out_be32(&memctl->memc_mcr, 0x80006105);
 205         udelay(1);
 206         out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
 207         udelay(1);
 208         out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
 209         udelay(1);
 210
 211         setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
 212         udelay(1000);
 213
 214         out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
 215         udelay(1000);
 216         if(rev >= 7) {
 217                 size = 32 * 3 * 1024 * 1024;
 218                 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_9COL);
 219                 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_9COL);
 220                 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_9COL);
 221                 out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_9COL);
 222                 out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_9COL);
 223                 out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_9COL);
 224         } else {
 225                 size = 16 * 3 * 1024 * 1024;
 226                 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_8COL);
 227                 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_8COL);
 228                 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_8COL);
 229                 out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_8COL);
 230                 out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_8COL);
 231                 out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_8COL);
 232         }
 233         return (size);
 234 }
 235
 236 /* ----------------------------------------------------------------------- */
 237
 238
 239 int misc_init_r(void)
 240 {
 241         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 242
 243 #ifdef CONFIG_IDE_LED
 244         /* Configure PA8 as output port */
 245         setbits_be16(&immap->im_ioport.iop_padir, PA_8);
 246         setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
 247         clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
 248         setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
 249 #endif
 250         load_sernum_ethaddr();
 251         setenv("hw","4k");
 252         poweron_key();
 253         return (0);
 254 }
 255
 256
 257 static int read_diag(void)
 258 {
 259         int diag;
 260         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 261
 262         clrbits_be16(&immr->im_ioport.iop_pcdir, PC_4); /* input */
 263         clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */
 264         setbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* output */
 265         clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */
 266         setbits_be16(&immr->im_ioport.iop_pcdat, PC_5); /* 1 */
 267         udelay(500);
 268         if (in_be16(&immr->im_ioport.iop_pcdat) & PC_4) {
 269                 clrbits_be16(&immr->im_ioport.iop_pcdat, PC_5);/* 0 */
 270                 udelay(500);
 271                 if(in_be16(&immr->im_ioport.iop_pcdat) & PC_4)
 272                         diag = 0;
 273                 else
 274                         diag = 1;
 275         } else {
 276                 diag = 0;
 277         }
 278         clrbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* input */
 279         return (diag);
 280 }
 281
 282 static unsigned char swapbyte(unsigned char c)
 283 {
 284         unsigned char result = 0;
 285         int i = 0;
 286
 287         for(i = 0; i < 8; ++i) {
 288                 result = result << 1;
 289                 result |= (c & 1);
 290                 c = c >> 1;
 291         }
 292         return result;
 293 }
 294
 295 /*
 296  * Device Tree Support
 297  */
 298 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 299 void ft_board_setup(void *blob, bd_t *bd)
 300 {
 301         ft_cpu_setup(blob, bd);
 302 }
 303 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */