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1 /*
2 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <asm-offsets.h>
25 #include <ppc_asm.tmpl>
26 #include <asm/mmu.h>
27 #include <config.h>
28
29 /**************************************************************************
30 * TLB TABLE
31 *
32 * This table is used by the cpu boot code to setup the initial tlb
33 * entries. Rather than make broad assumptions in the cpu source tree,
34 * this table lets each board set things up however they like.
35 *
36 * Pointer to the table is returned in r1
37 *
38 *************************************************************************/
39
40 .section .bootpg,"ax"
41 .globl tlbtab
42
43 tlbtab:
44 tlbtab_start
45
46 /*
47 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
48 * speed up boot process. It is patched after relocation to enable SA_I
49 */
50 tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
51
52 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
53 tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
54
55 /*
56 * TLB entries for SDRAM are not needed on this platform.
57 * They are dynamically generated in the SPD DDR detection
58 * routine.
59 */
60
61 tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
62
63 /* PCI */
64 tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
65 tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
66 tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
67 tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
68
69 /* USB 2.0 Device */
70 tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
71
72 tlbtab_end