board/pm520/pm520.c

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <mpc5xxx.h>
  29 #include <pci.h>
  30 #include <netdev.h>
  31
  32 #if defined(CONFIG_MPC5200_DDR)
  33 #include "mt46v16m16-75.h"
  34 #else
  35 #include "mt48lc16m16a2-75.h"
  36 #endif
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #ifndef CONFIG_SYS_RAMBOOT
  41 static void sdram_start (int hi_addr)
  42 {
  43         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  44
  45         /* unlock mode register */
  46         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  47         __asm__ volatile ("sync");
  48
  49         /* precharge all banks */
  50         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  51         __asm__ volatile ("sync");
  52
  53 #if SDRAM_DDR
  54         /* set mode register: extended mode */
  55         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  56         __asm__ volatile ("sync");
  57
  58         /* set mode register: reset DLL */
  59         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  60         __asm__ volatile ("sync");
  61 #endif
  62
  63         /* precharge all banks */
  64         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  65         __asm__ volatile ("sync");
  66
  67         /* auto refresh */
  68         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  69         __asm__ volatile ("sync");
  70
  71         /* set mode register */
  72         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  73         __asm__ volatile ("sync");
  74
  75         /* normal operation */
  76         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  77         __asm__ volatile ("sync");
  78 }
  79 #endif
  80
  81 /*
  82  * ATTENTION: Although partially referenced initdram does NOT make real use
  83  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  84  *            is something else than 0x00000000.
  85  */
  86
  87 #if defined(CONFIG_MPC5200)
  88 phys_size_t initdram (int board_type)
  89 {
  90         ulong dramsize = 0;
  91         ulong dramsize2 = 0;
  92 #ifndef CONFIG_SYS_RAMBOOT
  93         ulong test1, test2;
  94
  95         /* setup SDRAM chip selects */
  96         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  97         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
  98         __asm__ volatile ("sync");
  99
 100         /* setup config registers */
 101         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 102         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 103         __asm__ volatile ("sync");
 104
 105 #if SDRAM_DDR
 106         /* set tap delay */
 107         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 108         __asm__ volatile ("sync");
 109 #endif
 110
 111         /* find RAM size using SDRAM CS0 only */
 112         sdram_start(0);
 113         test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 114         sdram_start(1);
 115         test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 116         if (test1 > test2) {
 117                 sdram_start(0);
 118                 dramsize = test1;
 119         } else {
 120                 dramsize = test2;
 121         }
 122
 123         /* memory smaller than 1MB is impossible */
 124         if (dramsize < (1 << 20)) {
 125                 dramsize = 0;
 126         }
 127
 128         /* set SDRAM CS0 size according to the amount of RAM found */
 129         if (dramsize > 0) {
 130                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 131         } else {
 132                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 133         }
 134
 135         /* let SDRAM CS1 start right after CS0 */
 136         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 137
 138         /* find RAM size using SDRAM CS1 only */
 139         if (!dramsize)
 140                 sdram_start(0);
 141         test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 142         if (!dramsize) {
 143                 sdram_start(1);
 144                 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 145         }
 146         if (test1 > test2) {
 147                 sdram_start(0);
 148                 dramsize2 = test1;
 149         } else {
 150                 dramsize2 = test2;
 151         }
 152
 153         /* memory smaller than 1MB is impossible */
 154         if (dramsize2 < (1 << 20)) {
 155                 dramsize2 = 0;
 156         }
 157
 158         /* set SDRAM CS1 size according to the amount of RAM found */
 159         if (dramsize2 > 0) {
 160                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 161                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 162         } else {
 163                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 164         }
 165
 166 #else /* CONFIG_SYS_RAMBOOT */
 167
 168         /* retrieve size of memory connected to SDRAM CS0 */
 169         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 170         if (dramsize >= 0x13) {
 171                 dramsize = (1 << (dramsize - 0x13)) << 20;
 172         } else {
 173                 dramsize = 0;
 174         }
 175
 176         /* retrieve size of memory connected to SDRAM CS1 */
 177         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 178         if (dramsize2 >= 0x13) {
 179                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 180         } else {
 181                 dramsize2 = 0;
 182         }
 183
 184 #endif /* CONFIG_SYS_RAMBOOT */
 185
 186         return dramsize + dramsize2;
 187 }
 188
 189 #elif defined(CONFIG_MGT5100)
 190
 191 phys_size_t initdram (int board_type)
 192 {
 193         ulong dramsize = 0;
 194 #ifndef CONFIG_SYS_RAMBOOT
 195         ulong test1, test2;
 196
 197         /* setup and enable SDRAM chip selects */
 198         *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
 199         *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
 200         *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
 201         __asm__ volatile ("sync");
 202
 203         /* setup config registers */
 204         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 205         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 206
 207         /* address select register */
 208         *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
 209         __asm__ volatile ("sync");
 210
 211         /* find RAM size */
 212         sdram_start(0);
 213         test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 214         sdram_start(1);
 215         test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 216         if (test1 > test2) {
 217                 sdram_start(0);
 218                 dramsize = test1;
 219         } else {
 220                 dramsize = test2;
 221         }
 222
 223         /* set SDRAM end address according to size */
 224         *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 225
 226 #else /* CONFIG_SYS_RAMBOOT */
 227
 228         /* Retrieve amount of SDRAM available */
 229         dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 230
 231 #endif /* CONFIG_SYS_RAMBOOT */
 232
 233         return dramsize;
 234 }
 235
 236 #else
 237 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
 238 #endif
 239
 240 int checkboard (void)
 241 {
 242 #if defined(CONFIG_MPC5200)
 243         puts ("Board: MicroSys PM520 \n");
 244 #elif defined(CONFIG_MGT5100)
 245         puts ("Board: MicroSys PM510 \n");
 246 #endif
 247         return 0;
 248 }
 249
 250 void flash_preinit(void)
 251 {
 252         /*
 253          * Now, when we are in RAM, enable flash write
 254          * access for detection process.
 255          * Note that CS_BOOT cannot be cleared when
 256          * executing in flash.
 257          */
 258 #if defined(CONFIG_MGT5100)
 259         *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
 260         *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
 261 #endif
 262         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 263 }
 264
 265 void flash_afterinit(ulong start, ulong size)
 266 {
 267 #if defined(CONFIG_BOOT_ROM)
 268         /* adjust mapping */
 269         *(vu_long *)MPC5XXX_CS1_START =
 270                         START_REG(start);
 271         *(vu_long *)MPC5XXX_CS1_STOP =
 272                         STOP_REG(start, size);
 273 #else
 274         /* adjust mapping */
 275         *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 276                         START_REG(start);
 277         *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 278                         STOP_REG(start, size);
 279 #endif
 280 }
 281
 282
 283 extern flash_info_t flash_info[];       /* info for FLASH chips */
 284
 285 int misc_init_r (void)
 286 {
 287         /* adjust flash start */
 288         gd->bd->bi_flashstart = flash_info[0].start[0];
 289         return (0);
 290 }
 291
 292 #ifdef  CONFIG_PCI
 293 static struct pci_controller hose;
 294
 295 extern void pci_mpc5xxx_init(struct pci_controller *);
 296
 297 void pci_init_board(void)
 298 {
 299         pci_mpc5xxx_init(&hose);
 300 }
 301 #endif
 302
 303 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 304
 305 void init_ide_reset (void)
 306 {
 307         debug ("init_ide_reset\n");
 308
 309 }
 310
 311 void ide_set_reset (int idereset)
 312 {
 313         debug ("ide_reset(%d)\n", idereset);
 314
 315 }
 316 #endif
 317
 318 #if defined(CONFIG_CMD_DOC)
 319 void doc_init (void)
 320 {
 321         doc_probe (CONFIG_SYS_DOC_BASE);
 322 }
 323 #endif
 324
 325 int board_eth_init(bd_t *bis)
 326 {
 327         cpu_eth_init(bis); /* Built in FEC comes first */
 328         return pci_eth_init(bis);
 329 }