3 * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include "metrobox_version.h"
28 #include <asm/processor.h>
30 #include <spd_sdram.h>
32 #include "../common/ppc440gx_i2c.h"
33 #include "../common/sb_common.h"
35 void fpga_init (void);
37 METROBOX_BOARD_ID_ST board_id_as
[] =
38 { {"Undefined"}, /* Not specified */
39 {"2x10Gb"}, /* 2 ports, 10 GbE */
40 {"20x1Gb"}, /* 20 ports, 1 GbE */
41 {"Reserved"}, /* Reserved for future use */
44 /*************************************************************************
47 * Setup chip selects, initialize the Opto-FPGA, initialize
48 * interrupt polarity and triggers.
49 ************************************************************************/
50 int board_early_init_f (void)
52 ppc440_gpio_regs_t
*gpio_regs
;
54 /* Enable GPIO interrupts */
55 mtsdr(sdr_pfc0
, 0x00103E00);
57 /* Setup access for LEDs, and system topology info */
58 gpio_regs
= (ppc440_gpio_regs_t
*)CONFIG_SYS_GPIO_BASE
;
59 gpio_regs
->open_drain
= SBCOMMON_GPIO_SYS_LEDS
;
60 gpio_regs
->tri_state
= SBCOMMON_GPIO_DBGLEDS
;
62 /* Turn on all the leds for now */
63 gpio_regs
->out
= SBCOMMON_GPIO_LEDS
;
65 /*--------------------------------------------------------------------+
66 | Initialize EBC CONFIG
67 +-------------------------------------------------------------------*/
69 EBC_CFG_LE_UNLOCK
| EBC_CFG_PTD_ENABLE
|
70 EBC_CFG_RTC_64PERCLK
| EBC_CFG_ATC_PREVIOUS
|
71 EBC_CFG_DTC_PREVIOUS
| EBC_CFG_CTC_PREVIOUS
|
72 EBC_CFG_EMC_DEFAULT
| EBC_CFG_PME_DISABLE
|
75 /*--------------------------------------------------------------------+
76 | 1/2 MB FLASH. Initialize bank 0 with default values.
77 +-------------------------------------------------------------------*/
79 EBC_BXAP_BME_DISABLED
| EBC_BXAP_TWT_ENCODE(8) |
80 EBC_BXAP_BCE_DISABLE
| EBC_BXAP_CSN_ENCODE(1) |
81 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
82 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
83 EBC_BXAP_RE_DISABLED
| EBC_BXAP_BEM_WRITEONLY
|
84 EBC_BXAP_PEN_DISABLED
);
86 mtebc(pb0cr
, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE
) |
87 EBC_BXCR_BS_1MB
| EBC_BXCR_BU_RW
| EBC_BXCR_BW_8BIT
);
88 /*--------------------------------------------------------------------+
89 | 8KB NVRAM/RTC. Initialize bank 1 with default values.
90 +-------------------------------------------------------------------*/
92 EBC_BXAP_BME_DISABLED
| EBC_BXAP_TWT_ENCODE(10) |
93 EBC_BXAP_BCE_DISABLE
| EBC_BXAP_CSN_ENCODE(1) |
94 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
95 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
96 EBC_BXAP_RE_DISABLED
| EBC_BXAP_BEM_WRITEONLY
|
97 EBC_BXAP_PEN_DISABLED
);
99 mtebc(pb1cr
, EBC_BXCR_BAS_ENCODE(0x48000000) |
100 EBC_BXCR_BS_1MB
| EBC_BXCR_BU_RW
| EBC_BXCR_BW_8BIT
);
102 /*--------------------------------------------------------------------+
103 | Compact Flash, uses 2 Chip Selects (2 & 6)
104 +-------------------------------------------------------------------*/
106 EBC_BXAP_BME_DISABLED
| EBC_BXAP_TWT_ENCODE(8) |
107 EBC_BXAP_BCE_DISABLE
| EBC_BXAP_CSN_ENCODE(1) |
108 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
109 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
110 EBC_BXAP_RE_DISABLED
| EBC_BXAP_BEM_WRITEONLY
|
111 EBC_BXAP_PEN_DISABLED
);
113 mtebc(pb2cr
, EBC_BXCR_BAS_ENCODE(0xF0000000) |
114 EBC_BXCR_BS_1MB
| EBC_BXCR_BU_RW
| EBC_BXCR_BW_16BIT
);
116 /*--------------------------------------------------------------------+
117 | OPTO & OFEM FPGA. Initialize bank 3 with default values.
118 +-------------------------------------------------------------------*/
120 EBC_BXAP_RE_ENABLED
| EBC_BXAP_SOR_NONDELAYED
|
121 EBC_BXAP_BME_DISABLED
| EBC_BXAP_TWT_ENCODE(3) |
122 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
123 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED
|
124 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW
);
126 mtebc(pb3cr
, EBC_BXCR_BAS_ENCODE(0x48200000) |
127 EBC_BXCR_BS_1MB
| EBC_BXCR_BU_RW
| EBC_BXCR_BW_32BIT
);
129 /*--------------------------------------------------------------------+
131 | MAC A & B for Kamino. OFEM FPGA decodes the addresses
132 | Initialize bank 4 with default values.
133 +-------------------------------------------------------------------*/
135 EBC_BXAP_RE_ENABLED
| EBC_BXAP_SOR_NONDELAYED
|
136 EBC_BXAP_BME_DISABLED
| EBC_BXAP_TWT_ENCODE(3) |
137 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
138 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED
|
139 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW
);
141 mtebc(pb4cr
, EBC_BXCR_BAS_ENCODE(0x48600000) |
142 EBC_BXCR_BS_1MB
| EBC_BXCR_BU_RW
| EBC_BXCR_BW_32BIT
);
144 /*--------------------------------------------------------------------+
145 | Metrobox MAC B Initialize bank 5 with default values.
146 | KA REF FPGA Initialize bank 5 with default values.
147 +-------------------------------------------------------------------*/
149 EBC_BXAP_RE_ENABLED
| EBC_BXAP_SOR_NONDELAYED
|
150 EBC_BXAP_BME_DISABLED
| EBC_BXAP_TWT_ENCODE(3) |
151 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
152 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED
|
153 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW
);
155 mtebc(pb5cr
, EBC_BXCR_BAS_ENCODE(0x48700000) |
156 EBC_BXCR_BS_1MB
| EBC_BXCR_BU_RW
| EBC_BXCR_BW_32BIT
);
158 /*--------------------------------------------------------------------+
159 | Compact Flash, uses 2 Chip Selects (2 & 6)
160 +-------------------------------------------------------------------*/
162 EBC_BXAP_BME_DISABLED
| EBC_BXAP_TWT_ENCODE(8) |
163 EBC_BXAP_BCE_DISABLE
| EBC_BXAP_CSN_ENCODE(1) |
164 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
165 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
166 EBC_BXAP_RE_DISABLED
| EBC_BXAP_BEM_WRITEONLY
|
167 EBC_BXAP_PEN_DISABLED
);
169 mtebc(pb6cr
, EBC_BXCR_BAS_ENCODE(0xF0100000) |
170 EBC_BXCR_BS_1MB
| EBC_BXCR_BU_RW
| EBC_BXCR_BW_16BIT
);
172 /*--------------------------------------------------------------------+
173 | BME-32. Initialize bank 7 with default values.
174 +-------------------------------------------------------------------*/
176 EBC_BXAP_RE_ENABLED
| EBC_BXAP_SOR_NONDELAYED
|
177 EBC_BXAP_BME_DISABLED
| EBC_BXAP_TWT_ENCODE(3) |
178 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
179 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED
|
180 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW
);
182 mtebc(pb7cr
, EBC_BXCR_BAS_ENCODE(0x48500000) |
183 EBC_BXCR_BS_1MB
| EBC_BXCR_BU_RW
| EBC_BXCR_BW_32BIT
);
185 /*--------------------------------------------------------------------+
186 * Setup the interrupt controller polarities, triggers, etc.
187 +-------------------------------------------------------------------*/
189 * Because of the interrupt handling rework to handle 440GX interrupts
190 * with the common code, we needed to change names of the UIC registers.
191 * Here the new relationship:
193 * U-Boot name 440GX name
194 * -----------------------
200 mtdcr (uic1sr
, 0xffffffff); /* clear all */
201 mtdcr (uic1er
, 0x00000000); /* disable all */
202 mtdcr (uic1cr
, 0x00000000); /* all non- critical */
203 mtdcr (uic1pr
, 0xfffffe03); /* polarity */
204 mtdcr (uic1tr
, 0x01c00000); /* trigger edge vs level */
205 mtdcr (uic1vr
, 0x00000001); /* int31 highest, base=0x000 */
206 mtdcr (uic1sr
, 0xffffffff); /* clear all */
208 mtdcr (uic2sr
, 0xffffffff); /* clear all */
209 mtdcr (uic2er
, 0x00000000); /* disable all */
210 mtdcr (uic2cr
, 0x00000000); /* all non-critical */
211 mtdcr (uic2pr
, 0xffffc8ff); /* polarity */
212 mtdcr (uic2tr
, 0x00ff0000); /* trigger edge vs level */
213 mtdcr (uic2vr
, 0x00000001); /* int31 highest, base=0x000 */
214 mtdcr (uic2sr
, 0xffffffff); /* clear all */
216 mtdcr (uic3sr
, 0xffffffff); /* clear all */
217 mtdcr (uic3er
, 0x00000000); /* disable all */
218 mtdcr (uic3cr
, 0x00000000); /* all non-critical */
219 mtdcr (uic3pr
, 0xffff83ff); /* polarity */
220 mtdcr (uic3tr
, 0x00ff8c0f); /* trigger edge vs level */
221 mtdcr (uic3vr
, 0x00000001); /* int31 highest, base=0x000 */
222 mtdcr (uic3sr
, 0xffffffff); /* clear all */
224 mtdcr (uic0sr
, 0xfc000000); /* clear all */
225 mtdcr (uic0er
, 0x00000000); /* disable all */
226 mtdcr (uic0cr
, 0x00000000); /* all non-critical */
227 mtdcr (uic0pr
, 0xfc000000);
228 mtdcr (uic0tr
, 0x00000000);
229 mtdcr (uic0vr
, 0x00000001);
236 /*************************************************************************
239 * Dump pertinent info to the console
240 ************************************************************************/
241 int checkboard (void)
244 unsigned char brd_rev
, brd_id
;
245 unsigned short sernum
;
246 unsigned char opto_rev
, opto_id
;
247 OPTO_FPGA_REGS_ST
*opto_ps
;
249 opto_ps
= (OPTO_FPGA_REGS_ST
*)CONFIG_SYS_FPGA_BASE
;
251 opto_rev
= (unsigned char)((opto_ps
->revision_ul
&
252 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK
)
253 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT
);
255 opto_id
= (unsigned char)((opto_ps
->revision_ul
&
256 SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK
)
257 >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT
);
259 brd_rev
= (unsigned char)((opto_ps
->boardinfo_ul
&
260 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK
)
261 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT
);
263 brd_id
= (unsigned char)((opto_ps
->boardinfo_ul
&
264 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK
)
265 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT
);
267 get_sys_info (&sysinfo
);
269 sernum
= sbcommon_get_serial_number();
270 printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum
);
271 printf ("%s\n", METROBOX_U_BOOT_REL_STR
);
273 printf ("Built %s %s by %s\n", __DATE__
, __TIME__
, BUILDUSER
);
274 if (sbcommon_get_master()) {
275 printf("Slot 0 - Master\nSlave board");
276 if (sbcommon_secondary_present())
277 printf(" present\n");
279 printf(" not detected\n");
281 printf("Slot 1 - Slave\n\n");
284 printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id
, opto_rev
);
285 printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev
, board_id_as
[brd_id
].name
);
287 /* Fix the ack in the bme 32 */
289 out32(CONFIG_SYS_BME32_BASE
+ 0x0000000C, 0x00000001);
296 /*************************************************************************
299 * Initialize I2C bus one to gain access to the fans
300 ************************************************************************/
301 int misc_init_f (void)
303 /* Turn on i2c bus 1 */
305 i2c1_init (CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
314 /*************************************************************************
318 ************************************************************************/
319 int misc_init_r (void)
321 unsigned short sernum
;
323 unsigned char opto_rev
;
324 OPTO_FPGA_REGS_ST
*opto_ps
;
326 opto_ps
= (OPTO_FPGA_REGS_ST
*)CONFIG_SYS_FPGA_BASE
;
328 if(NULL
!= getenv("secondserial")) {
329 puts("secondserial is set, switching to second serial port\n");
330 setenv("stderr", "serial1");
331 setenv("stdout", "serial1");
332 setenv("stdin", "serial1");
335 setenv("ubrelver", METROBOX_U_BOOT_REL_STR
);
337 memset(envstr
, 0, 255);
338 sprintf (envstr
, "Built %s %s by %s", __DATE__
, __TIME__
, BUILDUSER
);
339 setenv("bldstr", envstr
);
342 if( getenv("autorecover")) {
343 setenv("autorecover", NULL
);
345 sernum
= sbcommon_get_serial_number();
347 printf("\nSetting up environment for automatic filesystem recovery\n");
349 * Setup default bootargs
351 memset(envstr
, 0, 255);
352 sprintf(envstr
, "console=ttyS0,9600 root=/dev/ram0 "
353 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
355 setenv("bootargs", envstr
);
358 * Setup Default boot command
360 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
361 "fatload ide 0 8100000 pramdisk;"
362 "bootm 8000000 8100000");
364 printf("Done. Please type allow the system to continue to boot\n");
367 if( getenv("fakeled")) {
368 setenv("bootdelay", "-1");
370 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
371 opto_rev
= (unsigned char)((opto_ps
->revision_ul
&
372 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK
)
373 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT
);
375 if(0x12 <= opto_rev
) {
376 opto_ps
->control_ul
&= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK
;
383 /*************************************************************************
385 ************************************************************************/
386 #ifdef CONFIG_IDE_RESET
387 void ide_set_reset(int on
)
389 OPTO_FPGA_REGS_ST
*opto_ps
;
390 opto_ps
= (OPTO_FPGA_REGS_ST
*)CONFIG_SYS_FPGA_BASE
;
392 if (on
) { /* assert RESET */
393 opto_ps
->reset_ul
&= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK
;
394 } else { /* release RESET */
395 opto_ps
->reset_ul
|= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK
;
398 #endif /* CONFIG_IDE_RESET */
400 /*************************************************************************
402 ************************************************************************/
405 OPTO_FPGA_REGS_ST
*opto_ps
;
406 unsigned char opto_rev
;
409 /* Ensure we have power all around */
413 * Take appropriate hw bits out of reset
415 opto_ps
= (OPTO_FPGA_REGS_ST
*)CONFIG_SYS_FPGA_BASE
;
418 SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK
|
419 SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK
|
420 SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK
|
421 SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK
|
422 SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK
|
423 SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK
|
424 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK
|
425 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK
|
426 SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK
|
427 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK
|
428 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK
|
429 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK
|
430 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK
|
431 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK
|
432 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK
|
433 SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK
|
434 SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK
|
435 SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK
;
436 opto_ps
->reset_ul
= tmp
;
438 * Turn on the 'Slow Blink' for the System Error Led.
439 * Ensure FPGA rev is up to at least rev 0x12
441 opto_rev
= (unsigned char)((opto_ps
->revision_ul
&
442 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK
)
443 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT
);
444 if(0x12 <= opto_rev
) {
445 opto_ps
->control_ul
|= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT
;
453 int metroboxSetupVars(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
455 unsigned short sernum
;
458 sernum
= sbcommon_get_serial_number();
460 memset(envstr
, 0, 255);
462 * Setup our ip address
464 sprintf(envstr
, "10.100.60.%d", sernum
);
466 setenv("ipaddr", envstr
);
468 * Setup the host ip address
470 setenv("serverip", "10.100.17.10");
473 * Setup default bootargs
475 memset(envstr
, 0, 255);
477 sprintf(envstr
, "console=ttyS0,9600 root=/dev/nfs "
478 "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
479 "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
480 ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
481 sernum
, sernum
, sernum
);
483 setenv("bootargs_nfs", envstr
);
484 setenv("bootargs", envstr
);
489 memset(envstr
, 0, 255);
490 sprintf(envstr
, "console=ttyS0,9600 root=/dev/hda2 "
491 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
494 setenv("bootargs_cf", envstr
);
497 * Setup Default boot command
499 setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
500 setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
503 * Setup compact flash boot command
505 setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
513 int metroboxRecover(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
515 unsigned short sernum
;
518 sernum
= sbcommon_get_serial_number();
520 printf("\nSetting up environment for filesystem recovery\n");
522 * Setup default bootargs
524 memset(envstr
, 0, 255);
525 sprintf(envstr
, "console=ttyS0,9600 root=/dev/ram0 "
526 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
529 setenv("bootargs", envstr
);
532 * Setup Default boot command
534 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
535 "fatload ide 0 8100000 pramdisk;"
536 "bootm 8000000 8100000");
538 printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
539 " please type fsrecover.sh<cr>\n");
544 U_BOOT_CMD(mbsetup
, 1, 1, metroboxSetupVars
,
545 "mbsetup - Set environment to factory defaults\n", NULL
);
547 U_BOOT_CMD(mbrecover
, 1, 1, metroboxRecover
,
548 "mbrecover - Set environment to allow for fs recovery\n", NULL
);