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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / board / stxssa / stxssa.c
1 /*
2 * (C) Copyright 2005, Embedded Alley Solutions, Inc.
3 * Dan Malek, <dan@embeddedalley.com>
4 * Copied from STx GP3.
5 * Updates for Silicon Tx GP3 SSA
6 *
7 * (C) Copyright 2003,Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
9 *
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31
32 #include <common.h>
33 #include <pci.h>
34 #include <asm/processor.h>
35 #include <asm/mmu.h>
36 #include <asm/immap_85xx.h>
37 #include <asm/fsl_ddr_sdram.h>
38 #include <ioports.h>
39 #include <asm/io.h>
40 #include <spd_sdram.h>
41 #include <miiphy.h>
42 #include <netdev.h>
43
44 long int fixed_sdram (void);
45
46 /*
47 * I/O Port configuration table
48 *
49 * if conf is 1, then that port pin will be configured at boot time
50 * according to the five values podr/pdir/ppar/psor/pdat for that entry
51 */
52
53 const iop_conf_t iop_conf_tab[4][32] = {
54
55 /* Port A configuration */
56 { /* conf ppar psor pdir podr pdat */
57 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
58 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
59 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
60 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
61 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
62 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
63 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
64 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
65 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
66 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
67 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
68 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
69 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
70 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
71 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
72 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
73 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
74 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
75 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
76 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
77 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
78 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
79 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
80 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
81 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
82 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
83 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
84 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
85 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
86 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
87 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
88 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
89 },
90
91 /* Port B configuration */
92 { /* conf ppar psor pdir podr pdat */
93 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
94 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
95 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
96 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
97 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
98 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
99 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
100 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
101 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
102 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
103 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
104 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
105 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
106 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
107 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
108 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
109 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
110 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
111 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
112 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
113 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
114 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
115 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
116 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
117 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
118 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
119 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
120 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
121 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
122 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
123 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
124 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
125 },
126
127 /* Port C */
128 { /* conf ppar psor pdir podr pdat */
129 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
130 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
131 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
132 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
133 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
134 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
135 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
136 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
137 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
138 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
139 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
140 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
141 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
142 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
143 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
144 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
145 /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
146 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
147 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
148 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
149 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
150 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
151 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
152 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
153 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
154 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
155 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
156 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
157 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
158 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
159 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
160 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
161 },
162
163 /* Port D */
164 { /* conf ppar psor pdir podr pdat */
165 /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
166 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
167 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
168 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
169 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
170 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
171 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
172 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
173 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
174 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
175 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
176 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
177 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
178 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
179 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
180 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
181 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
182 /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
183 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
184 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
185 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
186 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
187 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
188 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
189 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
190 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
191 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
192 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
193 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
194 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
195 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
196 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
197 }
198 };
199
200 static uint64_t next_led_update;
201 static uint led_bit;
202
203 void
204 reset_phy(void)
205 {
206 volatile uint *blatch;
207 #if 0
208 int i;
209 #endif
210 blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
211
212 /* reset Giga bit Ethernet port if needed here */
213
214 #if 1
215 *blatch &= ~0x000000c0;
216 udelay(100);
217 #else
218 *blatch = 0;
219 asm("eieio");
220 for (i=0; i<1000; i++)
221 udelay(1000);
222 #endif
223 *blatch = 0x000000c1; /* Light one led, too */
224 udelay(1000);
225
226 #if 0 /* This is the port we really want to use for debugging. */
227 /* reset the CPM FEC port */
228 #if (CONFIG_ETHER_INDEX == 2)
229 bcsr->bcsr2 &= ~FETH2_RST;
230 udelay(2);
231 bcsr->bcsr2 |= FETH2_RST;
232 udelay(1000);
233 #elif (CONFIG_ETHER_INDEX == 3)
234 bcsr->bcsr3 &= ~FETH3_RST;
235 udelay(2);
236 bcsr->bcsr3 |= FETH3_RST;
237 udelay(1000);
238 #endif
239 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
240 /* reset PHY */
241 miiphy_reset("FCC1 ETHERNET", 0x0);
242
243 /* change PHY address to 0x02 */
244 bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
245
246 bb_miiphy_write(NULL, 0x02, PHY_BMCR,
247 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
248 #endif /* CONFIG_MII */
249 #endif
250 }
251
252 int
253 board_early_init_f(void)
254 {
255 #if defined(CONFIG_PCI)
256 volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
257
258 pci->peer &= 0xffffffdf; /* disable master abort */
259 #endif
260
261 /* Why is the phy reset done _after_ the ethernet
262 * initialization in lib_ppc/board.c?
263 * Do it here so it's done before the TSECs are used.
264 */
265 reset_phy();
266
267 return 0;
268 }
269
270 int
271 checkboard(void)
272 {
273 printf ("Board: Silicon Tx GPPP SSA Board\n");
274 return (0);
275 }
276
277 /* Blinkin' LEDS for Robert.
278 */
279 void
280 show_activity(int flag)
281 {
282 volatile uint *blatch;
283
284 if (next_led_update > get_ticks())
285 return;
286
287 blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
288
289 led_bit >>= 1;
290 if (led_bit == 0)
291 led_bit = 0x08;
292 *blatch = (0xc0 | led_bit);
293 eieio();
294 next_led_update += (get_tbclk() / 4);
295 }
296
297 phys_size_t
298 initdram (int board_type)
299 {
300 long dram_size = 0;
301
302 #if defined(CONFIG_DDR_DLL)
303 {
304 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
305 uint temp_ddrdll = 0;
306
307 /* Work around to stabilize DDR DLL */
308 temp_ddrdll = gur->ddrdllcr;
309 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
310 asm("sync;isync;msync");
311 }
312 #endif
313
314 dram_size = fsl_ddr_sdram();
315 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
316 dram_size *= 0x100000;
317
318 #if defined(CONFIG_DDR_ECC)
319 /* Initialize and enable DDR ECC.
320 */
321 ddr_enable_ecc(dram_size);
322 #endif
323
324 return dram_size;
325 }
326
327
328 #if defined(CONFIG_SYS_DRAM_TEST)
329 int testdram (void)
330 {
331 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
332 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
333 uint *p;
334
335 printf("SDRAM test phase 1:\n");
336 for (p = pstart; p < pend; p++)
337 *p = 0xaaaaaaaa;
338
339 for (p = pstart; p < pend; p++) {
340 if (*p != 0xaaaaaaaa) {
341 printf ("SDRAM test fails at: %08x\n", (uint) p);
342 return 1;
343 }
344 }
345
346 printf("SDRAM test phase 2:\n");
347 for (p = pstart; p < pend; p++)
348 *p = 0x55555555;
349
350 for (p = pstart; p < pend; p++) {
351 if (*p != 0x55555555) {
352 printf ("SDRAM test fails at: %08x\n", (uint) p);
353 return 1;
354 }
355 }
356
357 printf("SDRAM test passed.\n");
358 return 0;
359 }
360 #endif
361
362 #if defined(CONFIG_PCI)
363
364 /*
365 * Initialize PCI Devices, report devices found.
366 */
367
368 #ifndef CONFIG_PCI_PNP
369 static struct pci_config_table pci_stxgp3_config_table[] = {
370 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
371 PCI_IDSEL_NUMBER, PCI_ANY_ID,
372 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
373 PCI_ENET0_MEMADDR,
374 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
375 } },
376 { }
377 };
378 #endif
379
380
381 static struct pci_controller hose[] = {
382 #ifndef CONFIG_PCI_PNP
383 { config_table: pci_stxgp3_config_table,},
384 #else
385 {},
386 #endif
387 #ifdef CONFIG_MPC85XX_PCI2
388 {},
389 #endif
390 };
391
392 #endif /* CONFIG_PCI */
393
394
395 void
396 pci_init_board(void)
397 {
398 #ifdef CONFIG_PCI
399 extern void pci_mpc85xx_init(struct pci_controller *hose);
400
401 pci_mpc85xx_init(hose);
402 #endif /* CONFIG_PCI */
403 }
404
405 int board_eth_init(bd_t *bis)
406 {
407 cpu_eth_init(bis); /* Initialize TSECs first */
408 return pci_eth_init(bis);
409 }