4 * Board functions for TI AM335X based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h>
29 #include <power/tps65217.h>
30 #include <power/tps65910.h>
31 #include <environment.h>
35 DECLARE_GLOBAL_DATA_PTR
;
37 /* GPIO that controls power to DDR on EVM-SK */
38 #define GPIO_DDR_VTT_EN 7
40 static struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
43 * Read header information from EEPROM into global structure.
45 static int read_eeprom(struct am335x_baseboard_id
*header
)
47 /* Check if baseboard eeprom is available */
48 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR
)) {
49 puts("Could not probe the EEPROM; something fundamentally "
50 "wrong on the I2C bus.\n");
54 /* read the eeprom using i2c */
55 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR
, 0, 2, (uchar
*)header
,
56 sizeof(struct am335x_baseboard_id
))) {
57 puts("Could not read the EEPROM; something fundamentally"
58 " wrong on the I2C bus.\n");
62 if (header
->magic
!= 0xEE3355AA) {
64 * read the eeprom using i2c again,
65 * but use only a 1 byte address
67 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR
, 0, 1, (uchar
*)header
,
68 sizeof(struct am335x_baseboard_id
))) {
69 puts("Could not read the EEPROM; something "
70 "fundamentally wrong on the I2C bus.\n");
74 if (header
->magic
!= 0xEE3355AA) {
75 printf("Incorrect magic number (0x%x) in EEPROM\n",
84 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
85 static const struct ddr_data ddr2_data
= {
86 .datardsratio0
= ((MT47H128M16RT25E_RD_DQS
<<30) |
87 (MT47H128M16RT25E_RD_DQS
<<20) |
88 (MT47H128M16RT25E_RD_DQS
<<10) |
89 (MT47H128M16RT25E_RD_DQS
<<0)),
90 .datawdsratio0
= ((MT47H128M16RT25E_WR_DQS
<<30) |
91 (MT47H128M16RT25E_WR_DQS
<<20) |
92 (MT47H128M16RT25E_WR_DQS
<<10) |
93 (MT47H128M16RT25E_WR_DQS
<<0)),
94 .datawiratio0
= ((MT47H128M16RT25E_PHY_WRLVL
<<30) |
95 (MT47H128M16RT25E_PHY_WRLVL
<<20) |
96 (MT47H128M16RT25E_PHY_WRLVL
<<10) |
97 (MT47H128M16RT25E_PHY_WRLVL
<<0)),
98 .datagiratio0
= ((MT47H128M16RT25E_PHY_GATELVL
<<30) |
99 (MT47H128M16RT25E_PHY_GATELVL
<<20) |
100 (MT47H128M16RT25E_PHY_GATELVL
<<10) |
101 (MT47H128M16RT25E_PHY_GATELVL
<<0)),
102 .datafwsratio0
= ((MT47H128M16RT25E_PHY_FIFO_WE
<<30) |
103 (MT47H128M16RT25E_PHY_FIFO_WE
<<20) |
104 (MT47H128M16RT25E_PHY_FIFO_WE
<<10) |
105 (MT47H128M16RT25E_PHY_FIFO_WE
<<0)),
106 .datawrsratio0
= ((MT47H128M16RT25E_PHY_WR_DATA
<<30) |
107 (MT47H128M16RT25E_PHY_WR_DATA
<<20) |
108 (MT47H128M16RT25E_PHY_WR_DATA
<<10) |
109 (MT47H128M16RT25E_PHY_WR_DATA
<<0)),
110 .datauserank0delay
= MT47H128M16RT25E_PHY_RANK0_DELAY
,
111 .datadldiff0
= PHY_DLL_LOCK_DIFF
,
114 static const struct cmd_control ddr2_cmd_ctrl_data
= {
115 .cmd0csratio
= MT47H128M16RT25E_RATIO
,
116 .cmd0dldiff
= MT47H128M16RT25E_DLL_LOCK_DIFF
,
117 .cmd0iclkout
= MT47H128M16RT25E_INVERT_CLKOUT
,
119 .cmd1csratio
= MT47H128M16RT25E_RATIO
,
120 .cmd1dldiff
= MT47H128M16RT25E_DLL_LOCK_DIFF
,
121 .cmd1iclkout
= MT47H128M16RT25E_INVERT_CLKOUT
,
123 .cmd2csratio
= MT47H128M16RT25E_RATIO
,
124 .cmd2dldiff
= MT47H128M16RT25E_DLL_LOCK_DIFF
,
125 .cmd2iclkout
= MT47H128M16RT25E_INVERT_CLKOUT
,
128 static const struct emif_regs ddr2_emif_reg_data
= {
129 .sdram_config
= MT47H128M16RT25E_EMIF_SDCFG
,
130 .ref_ctrl
= MT47H128M16RT25E_EMIF_SDREF
,
131 .sdram_tim1
= MT47H128M16RT25E_EMIF_TIM1
,
132 .sdram_tim2
= MT47H128M16RT25E_EMIF_TIM2
,
133 .sdram_tim3
= MT47H128M16RT25E_EMIF_TIM3
,
134 .emif_ddr_phy_ctlr_1
= MT47H128M16RT25E_EMIF_READ_LATENCY
,
137 static const struct ddr_data ddr3_data
= {
138 .datardsratio0
= MT41J128MJT125_RD_DQS
,
139 .datawdsratio0
= MT41J128MJT125_WR_DQS
,
140 .datafwsratio0
= MT41J128MJT125_PHY_FIFO_WE
,
141 .datawrsratio0
= MT41J128MJT125_PHY_WR_DATA
,
142 .datadldiff0
= PHY_DLL_LOCK_DIFF
,
145 static const struct ddr_data ddr3_beagleblack_data
= {
146 .datardsratio0
= MT41K256M16HA125E_RD_DQS
,
147 .datawdsratio0
= MT41K256M16HA125E_WR_DQS
,
148 .datafwsratio0
= MT41K256M16HA125E_PHY_FIFO_WE
,
149 .datawrsratio0
= MT41K256M16HA125E_PHY_WR_DATA
,
150 .datadldiff0
= PHY_DLL_LOCK_DIFF
,
153 static const struct ddr_data ddr3_evm_data
= {
154 .datardsratio0
= MT41J512M8RH125_RD_DQS
,
155 .datawdsratio0
= MT41J512M8RH125_WR_DQS
,
156 .datafwsratio0
= MT41J512M8RH125_PHY_FIFO_WE
,
157 .datawrsratio0
= MT41J512M8RH125_PHY_WR_DATA
,
158 .datadldiff0
= PHY_DLL_LOCK_DIFF
,
161 static const struct cmd_control ddr3_cmd_ctrl_data
= {
162 .cmd0csratio
= MT41J128MJT125_RATIO
,
163 .cmd0dldiff
= MT41J128MJT125_DLL_LOCK_DIFF
,
164 .cmd0iclkout
= MT41J128MJT125_INVERT_CLKOUT
,
166 .cmd1csratio
= MT41J128MJT125_RATIO
,
167 .cmd1dldiff
= MT41J128MJT125_DLL_LOCK_DIFF
,
168 .cmd1iclkout
= MT41J128MJT125_INVERT_CLKOUT
,
170 .cmd2csratio
= MT41J128MJT125_RATIO
,
171 .cmd2dldiff
= MT41J128MJT125_DLL_LOCK_DIFF
,
172 .cmd2iclkout
= MT41J128MJT125_INVERT_CLKOUT
,
175 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data
= {
176 .cmd0csratio
= MT41K256M16HA125E_RATIO
,
177 .cmd0dldiff
= MT41K256M16HA125E_DLL_LOCK_DIFF
,
178 .cmd0iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
180 .cmd1csratio
= MT41K256M16HA125E_RATIO
,
181 .cmd1dldiff
= MT41K256M16HA125E_DLL_LOCK_DIFF
,
182 .cmd1iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
184 .cmd2csratio
= MT41K256M16HA125E_RATIO
,
185 .cmd2dldiff
= MT41K256M16HA125E_DLL_LOCK_DIFF
,
186 .cmd2iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
189 static const struct cmd_control ddr3_evm_cmd_ctrl_data
= {
190 .cmd0csratio
= MT41J512M8RH125_RATIO
,
191 .cmd0dldiff
= MT41J512M8RH125_DLL_LOCK_DIFF
,
192 .cmd0iclkout
= MT41J512M8RH125_INVERT_CLKOUT
,
194 .cmd1csratio
= MT41J512M8RH125_RATIO
,
195 .cmd1dldiff
= MT41J512M8RH125_DLL_LOCK_DIFF
,
196 .cmd1iclkout
= MT41J512M8RH125_INVERT_CLKOUT
,
198 .cmd2csratio
= MT41J512M8RH125_RATIO
,
199 .cmd2dldiff
= MT41J512M8RH125_DLL_LOCK_DIFF
,
200 .cmd2iclkout
= MT41J512M8RH125_INVERT_CLKOUT
,
203 static struct emif_regs ddr3_emif_reg_data
= {
204 .sdram_config
= MT41J128MJT125_EMIF_SDCFG
,
205 .ref_ctrl
= MT41J128MJT125_EMIF_SDREF
,
206 .sdram_tim1
= MT41J128MJT125_EMIF_TIM1
,
207 .sdram_tim2
= MT41J128MJT125_EMIF_TIM2
,
208 .sdram_tim3
= MT41J128MJT125_EMIF_TIM3
,
209 .zq_config
= MT41J128MJT125_ZQ_CFG
,
210 .emif_ddr_phy_ctlr_1
= MT41J128MJT125_EMIF_READ_LATENCY
|
214 static struct emif_regs ddr3_beagleblack_emif_reg_data
= {
215 .sdram_config
= MT41K256M16HA125E_EMIF_SDCFG
,
216 .ref_ctrl
= MT41K256M16HA125E_EMIF_SDREF
,
217 .sdram_tim1
= MT41K256M16HA125E_EMIF_TIM1
,
218 .sdram_tim2
= MT41K256M16HA125E_EMIF_TIM2
,
219 .sdram_tim3
= MT41K256M16HA125E_EMIF_TIM3
,
220 .zq_config
= MT41K256M16HA125E_ZQ_CFG
,
221 .emif_ddr_phy_ctlr_1
= MT41K256M16HA125E_EMIF_READ_LATENCY
,
224 static struct emif_regs ddr3_evm_emif_reg_data
= {
225 .sdram_config
= MT41J512M8RH125_EMIF_SDCFG
,
226 .ref_ctrl
= MT41J512M8RH125_EMIF_SDREF
,
227 .sdram_tim1
= MT41J512M8RH125_EMIF_TIM1
,
228 .sdram_tim2
= MT41J512M8RH125_EMIF_TIM2
,
229 .sdram_tim3
= MT41J512M8RH125_EMIF_TIM3
,
230 .zq_config
= MT41J512M8RH125_ZQ_CFG
,
231 .emif_ddr_phy_ctlr_1
= MT41J512M8RH125_EMIF_READ_LATENCY
|
235 #ifdef CONFIG_SPL_OS_BOOT
236 int spl_start_uboot(void)
238 /* break into full u-boot on 'c' */
239 return (serial_tstc() && serial_getc() == 'c');
243 #define OSC (V_OSCK/1000000)
244 const struct dpll_params dpll_ddr
= {
245 266, OSC
-1, 1, -1, -1, -1, -1};
246 const struct dpll_params dpll_ddr_evm_sk
= {
247 303, OSC
-1, 1, -1, -1, -1, -1};
248 const struct dpll_params dpll_ddr_bone_black
= {
249 400, OSC
-1, 1, -1, -1, -1, -1};
251 void am33xx_spl_board_init(void)
253 struct am335x_baseboard_id header
;
256 if (read_eeprom(&header
) < 0)
257 puts("Could not get board ID.\n");
259 /* Get the frequency */
260 dpll_mpu_opp100
.m
= am335x_get_efuse_mpu_max_freq(cdev
);
262 if (board_is_bone(&header
) || board_is_bone_lt(&header
)) {
263 /* BeagleBone PMIC Code */
267 * Only perform PMIC configurations if board rev > A1
268 * on Beaglebone White
270 if (board_is_bone(&header
) && !strncmp(header
.version
,
274 if (i2c_probe(TPS65217_CHIP_PM
))
278 * On Beaglebone White we need to ensure we have AC power
279 * before increasing the frequency.
281 if (board_is_bone(&header
)) {
282 uchar pmic_status_reg
;
283 if (tps65217_reg_read(TPS65217_STATUS
,
286 if (!(pmic_status_reg
& TPS65217_PWR_SRC_AC_BITMASK
)) {
287 puts("No AC power, disabling frequency switch\n");
293 * Override what we have detected since we know if we have
294 * a Beaglebone Black it supports 1GHz.
296 if (board_is_bone_lt(&header
))
297 dpll_mpu_opp100
.m
= MPUPLL_M_1000
;
300 * Increase USB current limit to 1300mA or 1800mA and set
301 * the MPU voltage controller as needed.
303 if (dpll_mpu_opp100
.m
== MPUPLL_M_1000
) {
304 usb_cur_lim
= TPS65217_USB_INPUT_CUR_LIMIT_1800MA
;
305 mpu_vdd
= TPS65217_DCDC_VOLT_SEL_1325MV
;
307 usb_cur_lim
= TPS65217_USB_INPUT_CUR_LIMIT_1300MA
;
308 mpu_vdd
= TPS65217_DCDC_VOLT_SEL_1275MV
;
311 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE
,
314 TPS65217_USB_INPUT_CUR_LIMIT_MASK
))
315 puts("tps65217_reg_write failure\n");
317 /* Set DCDC3 (CORE) voltage to 1.125V */
318 if (tps65217_voltage_update(TPS65217_DEFDCDC3
,
319 TPS65217_DCDC_VOLT_SEL_1125MV
)) {
320 puts("tps65217_voltage_update failure\n");
324 /* Set CORE Frequencies to OPP100 */
325 do_setup_dpll(&dpll_core_regs
, &dpll_core_opp100
);
327 /* Set DCDC2 (MPU) voltage */
328 if (tps65217_voltage_update(TPS65217_DEFDCDC2
, mpu_vdd
)) {
329 puts("tps65217_voltage_update failure\n");
334 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
335 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
337 if (board_is_bone(&header
)) {
338 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2
,
340 TPS65217_LDO_VOLTAGE_OUT_3_3
,
342 puts("tps65217_reg_write failure\n");
344 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2
,
346 TPS65217_LDO_VOLTAGE_OUT_1_8
,
348 puts("tps65217_reg_write failure\n");
351 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2
,
353 TPS65217_LDO_VOLTAGE_OUT_3_3
,
355 puts("tps65217_reg_write failure\n");
360 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
361 * MPU frequencies we support we use a CORE voltage of
362 * 1.1375V. For MPU voltage we need to switch based on
363 * the frequency we are running at.
365 if (i2c_probe(TPS65910_CTRL_I2C_ADDR
))
369 * Depending on MPU clock and PG we will need a different
370 * VDD to drive at that speed.
372 sil_rev
= readl(&cdev
->deviceid
) >> 28;
373 mpu_vdd
= am335x_get_tps65910_mpu_vdd(sil_rev
,
376 /* Tell the TPS65910 to use i2c */
377 tps65910_set_i2c_control();
379 /* First update MPU voltage. */
380 if (tps65910_voltage_update(MPU
, mpu_vdd
))
383 /* Second, update the CORE voltage. */
384 if (tps65910_voltage_update(CORE
, TPS65910_OP_REG_SEL_1_1_3
))
387 /* Set CORE Frequencies to OPP100 */
388 do_setup_dpll(&dpll_core_regs
, &dpll_core_opp100
);
391 /* Set MPU Frequency to what we detected now that voltages are set */
392 do_setup_dpll(&dpll_mpu_regs
, &dpll_mpu_opp100
);
395 const struct dpll_params
*get_dpll_ddr_params(void)
397 struct am335x_baseboard_id header
;
399 enable_i2c0_pin_mux();
400 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED
, CONFIG_SYS_OMAP24_I2C_SLAVE
);
401 if (read_eeprom(&header
) < 0)
402 puts("Could not get board ID.\n");
404 if (board_is_evm_sk(&header
))
405 return &dpll_ddr_evm_sk
;
406 else if (board_is_bone_lt(&header
))
407 return &dpll_ddr_bone_black
;
408 else if (board_is_evm_15_or_later(&header
))
409 return &dpll_ddr_evm_sk
;
414 void set_uart_mux_conf(void)
416 #ifdef CONFIG_SERIAL1
417 enable_uart0_pin_mux();
418 #endif /* CONFIG_SERIAL1 */
419 #ifdef CONFIG_SERIAL2
420 enable_uart1_pin_mux();
421 #endif /* CONFIG_SERIAL2 */
422 #ifdef CONFIG_SERIAL3
423 enable_uart2_pin_mux();
424 #endif /* CONFIG_SERIAL3 */
425 #ifdef CONFIG_SERIAL4
426 enable_uart3_pin_mux();
427 #endif /* CONFIG_SERIAL4 */
428 #ifdef CONFIG_SERIAL5
429 enable_uart4_pin_mux();
430 #endif /* CONFIG_SERIAL5 */
431 #ifdef CONFIG_SERIAL6
432 enable_uart5_pin_mux();
433 #endif /* CONFIG_SERIAL6 */
436 void set_mux_conf_regs(void)
438 __maybe_unused
struct am335x_baseboard_id header
;
440 if (read_eeprom(&header
) < 0)
441 puts("Could not get board ID.\n");
443 enable_board_pin_mux(&header
);
446 void sdram_init(void)
448 __maybe_unused
struct am335x_baseboard_id header
;
450 if (read_eeprom(&header
) < 0)
451 puts("Could not get board ID.\n");
453 if (board_is_evm_sk(&header
)) {
455 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
456 * This is safe enough to do on older revs.
458 gpio_request(GPIO_DDR_VTT_EN
, "ddr_vtt_en");
459 gpio_direction_output(GPIO_DDR_VTT_EN
, 1);
462 if (board_is_evm_sk(&header
))
463 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE
, &ddr3_data
,
464 &ddr3_cmd_ctrl_data
, &ddr3_emif_reg_data
, 0);
465 else if (board_is_bone_lt(&header
))
466 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE
,
467 &ddr3_beagleblack_data
,
468 &ddr3_beagleblack_cmd_ctrl_data
,
469 &ddr3_beagleblack_emif_reg_data
, 0);
470 else if (board_is_evm_15_or_later(&header
))
471 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE
, &ddr3_evm_data
,
472 &ddr3_evm_cmd_ctrl_data
, &ddr3_evm_emif_reg_data
, 0);
474 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE
, &ddr2_data
,
475 &ddr2_cmd_ctrl_data
, &ddr2_emif_reg_data
, 0);
480 * Basic board specific setup. Pinmux has been handled already.
485 const u32 gpmc_nor
[GPMC_MAX_REG
] = { STNOR_GPMC_CONFIG1
,
486 STNOR_GPMC_CONFIG2
, STNOR_GPMC_CONFIG3
, STNOR_GPMC_CONFIG4
,
487 STNOR_GPMC_CONFIG5
, STNOR_GPMC_CONFIG6
, STNOR_GPMC_CONFIG7
};
490 #if defined(CONFIG_HW_WATCHDOG)
494 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
499 /* Reconfigure CS0 for NOR instead of NAND. */
500 enable_gpmc_cs_config(gpmc_nor
, &gpmc_cfg
->cs
[0],
501 CONFIG_SYS_FLASH_BASE
, GPMC_SIZE_16M
);
507 #ifdef CONFIG_BOARD_LATE_INIT
508 int board_late_init(void)
510 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
511 char safe_string
[HDR_NAME_LEN
+ 1];
512 struct am335x_baseboard_id header
;
514 if (read_eeprom(&header
) < 0)
515 puts("Could not get board ID.\n");
517 /* Now set variables based on the header. */
518 strncpy(safe_string
, (char *)header
.name
, sizeof(header
.name
));
519 safe_string
[sizeof(header
.name
)] = 0;
520 setenv("board_name", safe_string
);
522 strncpy(safe_string
, (char *)header
.version
, sizeof(header
.version
));
523 safe_string
[sizeof(header
.version
)] = 0;
524 setenv("board_rev", safe_string
);
531 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
532 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
533 static void cpsw_control(int enabled
)
535 /* VTP can be added here */
540 static struct cpsw_slave_data cpsw_slaves
[] = {
542 .slave_reg_ofs
= 0x208,
543 .sliver_reg_ofs
= 0xd80,
547 .slave_reg_ofs
= 0x308,
548 .sliver_reg_ofs
= 0xdc0,
553 static struct cpsw_platform_data cpsw_data
= {
554 .mdio_base
= CPSW_MDIO_BASE
,
555 .cpsw_base
= CPSW_BASE
,
558 .cpdma_reg_ofs
= 0x800,
560 .slave_data
= cpsw_slaves
,
561 .ale_reg_ofs
= 0xd00,
563 .host_port_reg_ofs
= 0x108,
564 .hw_stats_reg_ofs
= 0x900,
565 .bd_ram_ofs
= 0x2000,
566 .mac_control
= (1 << 5),
567 .control
= cpsw_control
,
569 .version
= CPSW_CTRL_VERSION_2
,
573 #if defined(CONFIG_DRIVER_TI_CPSW) || \
574 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
575 int board_eth_init(bd_t
*bis
)
579 uint32_t mac_hi
, mac_lo
;
580 __maybe_unused
struct am335x_baseboard_id header
;
582 /* try reading mac address from efuse */
583 mac_lo
= readl(&cdev
->macid0l
);
584 mac_hi
= readl(&cdev
->macid0h
);
585 mac_addr
[0] = mac_hi
& 0xFF;
586 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
587 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
588 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
589 mac_addr
[4] = mac_lo
& 0xFF;
590 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
592 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
593 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
594 if (!getenv("ethaddr")) {
595 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
597 if (is_valid_ether_addr(mac_addr
))
598 eth_setenv_enetaddr("ethaddr", mac_addr
);
601 #ifdef CONFIG_DRIVER_TI_CPSW
602 if (read_eeprom(&header
) < 0)
603 puts("Could not get board ID.\n");
605 if (board_is_bone(&header
) || board_is_bone_lt(&header
) ||
606 board_is_idk(&header
)) {
607 writel(MII_MODE_ENABLE
, &cdev
->miisel
);
608 cpsw_slaves
[0].phy_if
= cpsw_slaves
[1].phy_if
=
609 PHY_INTERFACE_MODE_MII
;
611 writel((RGMII_MODE_ENABLE
| RGMII_INT_DELAY
), &cdev
->miisel
);
612 cpsw_slaves
[0].phy_if
= cpsw_slaves
[1].phy_if
=
613 PHY_INTERFACE_MODE_RGMII
;
616 rv
= cpsw_register(&cpsw_data
);
618 printf("Error %d registering CPSW switch\n", rv
);
625 * CPSW RGMII Internal Delay Mode is not supported in all PVT
626 * operating points. So we must set the TX clock delay feature
627 * in the AR8051 PHY. Since we only support a single ethernet
628 * device in U-Boot, we only do this for the first instance.
630 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
631 #define AR8051_PHY_DEBUG_DATA_REG 0x1e
632 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
633 #define AR8051_RGMII_TX_CLK_DLY 0x100
635 if (board_is_evm_sk(&header
) || board_is_gp_evm(&header
)) {
637 devname
= miiphy_get_current_dev();
639 miiphy_write(devname
, 0x0, AR8051_PHY_DEBUG_ADDR_REG
,
640 AR8051_DEBUG_RGMII_CLK_DLY_REG
);
641 miiphy_write(devname
, 0x0, AR8051_PHY_DEBUG_DATA_REG
,
642 AR8051_RGMII_TX_CLK_DLY
);
645 #if defined(CONFIG_USB_ETHER) && \
646 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
647 if (is_valid_ether_addr(mac_addr
))
648 eth_setenv_enetaddr("usbnet_devaddr", mac_addr
);
650 rv
= usb_eth_initialize(bis
);
652 printf("Error %d registering USB_ETHER\n", rv
);