board/w7o/w7o.c

   1 /*
   2  * (C) Copyright 2001
   3  * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include "w7o.h"
  27 #include <asm/processor.h>
  28
  29 #include "vpd.h"
  30 #include "errors.h"
  31 #include <watchdog.h>
  32
  33 unsigned long get_dram_size (void);
  34 void sdram_init(void);
  35
  36 /* ------------------------------------------------------------------------- */
  37
  38 int board_early_init_f (void)
  39 {
  40 #if defined(CONFIG_W7OLMG)
  41         /*
  42          * Setup GPIO pins - reset devices.
  43          */
  44         out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
  45         out32 (PPC405GP_GPIO0_OR, 0x3E000000);  /* set output pins to default */
  46         out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
  47
  48         /*
  49          * IRQ 0-15  405GP internally generated; active high; level sensitive
  50          * IRQ 16    405GP internally generated; active low; level sensitive
  51          * IRQ 17-24 RESERVED
  52          * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
  53          * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
  54          * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
  55          * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
  56          * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
  57          * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
  58          * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
  59          */
  60         mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
  61         mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
  62
  63         mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical */
  64         mtdcr (UIC0PR, 0xFFFFFF80);     /* set int polarities */
  65         mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
  66         mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,
  67                                            INT0 highest priority */
  68
  69         mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
  70
  71 #elif defined(CONFIG_W7OLMC)
  72         /*
  73          * Setup GPIO pins
  74          */
  75         out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
  76         out32 (PPC405GP_GPIO0_OR, 0x03800000);  /* set out pins to default */
  77         out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
  78
  79         /*
  80          * IRQ 0-15  405GP internally generated; active high; level sensitive
  81          * IRQ 16    405GP internally generated; active low; level sensitive
  82          * IRQ 17-24 RESERVED
  83          * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
  84          * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
  85          * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
  86          * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
  87          * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
  88          * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
  89          * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
  90          */
  91         mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
  92         mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
  93
  94         mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical */
  95         mtdcr (UIC0PR, 0xFFFFFF80);     /* set int polarities */
  96         mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
  97         mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,
  98                                            INT0 highest priority */
  99
 100         mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 101
 102 #else  /* Unknown */
 103 #    error "Unknown W7O board configuration"
 104 #endif
 105
 106         WATCHDOG_RESET ();      /* Reset the watchdog */
 107         temp_uart_init ();      /* init the uart for debug */
 108         WATCHDOG_RESET ();      /* Reset the watchdog */
 109         test_led ();            /* test the LEDs */
 110         test_sdram (get_dram_size ());  /* test the dram */
 111         log_stat (ERR_POST1);   /* log status,post1 complete */
 112         return 0;
 113 }
 114
 115
 116 /* ------------------------------------------------------------------------- */
 117
 118 /*
 119  * Check Board Identity:
 120  */
 121 int checkboard (void)
 122 {
 123         VPD vpd;
 124
 125         puts ("Board: ");
 126
 127         /* VPD data present in I2C EEPROM */
 128         if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) {
 129                 /*
 130                  * Known board type.
 131                  */
 132                 if (vpd.productId[0] &&
 133                     ((strncmp (vpd.productId, "GMM", 3) == 0) ||
 134                      (strncmp (vpd.productId, "CMM", 3) == 0))) {
 135
 136                         /* Output board information on startup */
 137                         printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
 138                         return (0);
 139                 }
 140         }
 141
 142         puts ("### Unknown HW ID - assuming NOTHING\n");
 143         return (0);
 144 }
 145
 146 /* ------------------------------------------------------------------------- */
 147
 148 phys_size_t initdram (int board_type)
 149 {
 150         /*
 151          * ToDo: Move the asm init routine sdram_init() to this C file,
 152          * or even better use some common ppc4xx code available
 153          * in arch/powerpc/cpu/ppc4xx
 154          */
 155         sdram_init();
 156
 157         return get_dram_size ();
 158 }
 159
 160 unsigned long get_dram_size (void)
 161 {
 162         int tmp, i, regs[4];
 163         int size = 0;
 164
 165         /* Get bank Size registers */
 166         mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);    /* get bank 0 config reg */
 167         regs[0] = mfdcr (SDRAM0_CFGDATA);
 168
 169         mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);    /* get bank 1 config reg */
 170         regs[1] = mfdcr (SDRAM0_CFGDATA);
 171
 172         mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);    /* get bank 2 config reg */
 173         regs[2] = mfdcr (SDRAM0_CFGDATA);
 174
 175         mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);    /* get bank 3 config reg */
 176         regs[3] = mfdcr (SDRAM0_CFGDATA);
 177
 178         /* compute the size, add each bank if enabled */
 179         for (i = 0; i < 4; i++) {
 180                 if (regs[i] & 0x0001) { /* if enabled, */
 181                         tmp = ((regs[i] >> (31 - 14)) & 0x7);   /* get size bits */
 182                         tmp = 0x400000 << tmp;  /* Size bits X 4MB = size */
 183                         size += tmp;
 184                 }
 185         }
 186
 187         return size;
 188 }
 189
 190 int misc_init_f (void)
 191 {
 192         return 0;
 193 }
 194
 195 static void w7o_env_init (VPD * vpd)
 196 {
 197         /*
 198          * Read VPD
 199          */
 200         if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0)
 201                 return;
 202
 203         /*
 204          * Known board type.
 205          */
 206         if (vpd->productId[0] &&
 207             ((strncmp (vpd->productId, "GMM", 3) == 0) ||
 208              (strncmp (vpd->productId, "CMM", 3) == 0))) {
 209                 char buf[30];
 210                 char *eth;
 211                 char *serial = getenv ("serial#");
 212                 char *ethaddr = getenv ("ethaddr");
 213
 214                 /* Set 'serial#' envvar if serial# isn't set */
 215                 if (!serial) {
 216                         sprintf (buf, "%s-%ld", vpd->productId,
 217                                  vpd->serialNum);
 218                         setenv ("serial#", buf);
 219                 }
 220
 221                 /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
 222                 eth = (char *)(vpd->ethAddrs[0]);
 223                 if (ethaddr
 224                     && (strcmp(ethaddr, __stringify(CONFIG_ETHADDR)) == 0)) {
 225                         /* Now setup ethaddr */
 226                         sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
 227                                  eth[0], eth[1], eth[2], eth[3], eth[4],
 228                                  eth[5]);
 229                         setenv ("ethaddr", buf);
 230                 }
 231         }
 232 }                               /* w7o_env_init() */
 233
 234
 235 int misc_init_r (void)
 236 {
 237         VPD vpd;                /* VPD information */
 238
 239 #if defined(CONFIG_W7OLMG)
 240         unsigned long greg;     /* GPIO Register */
 241
 242         greg = in32 (PPC405GP_GPIO0_OR);
 243
 244         /*
 245          * XXX - Unreset devices - this should be moved into VxWorks driver code
 246          */
 247         greg |= 0x41800000L;    /* SAM, PHY, Galileo */
 248
 249         out32 (PPC405GP_GPIO0_OR, greg);        /* set output pins to default */
 250 #endif /* CONFIG_W7OLMG */
 251
 252         /*
 253          * Initialize W7O environment variables
 254          */
 255         w7o_env_init (&vpd);
 256
 257         /*
 258          * Initialize the FPGA(s).
 259          */
 260         if (init_fpga () == 0)
 261                 test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);
 262
 263         /* More POST testing. */
 264         post2 ();
 265
 266         /* Done with hardware initialization and POST. */
 267         log_stat (ERR_POSTOK);
 268
 269         /* Call silly, fail safe boot init routine */
 270         init_fsboot ();
 271
 272         return (0);
 273 }