board/woodburn/woodburn.c

   1 /*
   2  * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
   3  *
   4  * Based on flea3.c and mx35pdk.c
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/errno.h>
  28 #include <asm/arch/imx-regs.h>
  29 #include <asm/arch/crm_regs.h>
  30 #include <asm/arch/clock.h>
  31 #include <asm/arch/mx35_pins.h>
  32 #include <asm/arch/iomux.h>
  33 #include <i2c.h>
  34 #include <pmic.h>
  35 #include <fsl_pmic.h>
  36 #include <mc13892.h>
  37 #include <mmc.h>
  38 #include <fsl_esdhc.h>
  39 #include <linux/types.h>
  40 #include <asm/gpio.h>
  41 #include <asm/arch/sys_proto.h>
  42 #include <netdev.h>
  43 #include <spl.h>
  44
  45 #define CCM_CCMR_CONFIG         0x003F4208
  46
  47 #define ESDCTL_DDR2_CONFIG      0x007FFC3F
  48
  49 /* For MMC */
  50 #define GPIO_MMC_CD     7
  51 #define GPIO_MMC_WP     8
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 int dram_init(void)
  56 {
  57         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
  58                 PHYS_SDRAM_1_SIZE);
  59
  60         return 0;
  61 }
  62
  63 static void board_setup_sdram(void)
  64 {
  65         struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
  66
  67         /* Initialize with default values both CSD0/1 */
  68         writel(0x2000, &esdc->esdctl0);
  69         writel(0x2000, &esdc->esdctl1);
  70
  71         mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
  72                  13, 10, 2, 0x8080);
  73 }
  74
  75 static void setup_iomux_fec(void)
  76 {
  77         /* setup pins for FEC */
  78         mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
  79         mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
  80         mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
  81         mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
  82         mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
  83         mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
  84         mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
  85         mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
  86         mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
  87         mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
  88         mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
  89         mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
  90         mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
  91         mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
  92         mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
  93         mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
  94         mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
  95         mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
  96 }
  97
  98 int woodburn_init(void)
  99 {
 100         struct ccm_regs *ccm =
 101                 (struct ccm_regs *)IMX_CCM_BASE;
 102
 103         /* initialize PLL and clock configuration */
 104         writel(CCM_CCMR_CONFIG, &ccm->ccmr);
 105
 106         /* Set-up RAM */
 107         board_setup_sdram();
 108
 109         /* enable clocks */
 110         writel(readl(&ccm->cgr0) |
 111                 MXC_CCM_CGR0_EMI_MASK |
 112                 MXC_CCM_CGR0_EDIO_MASK |
 113                 MXC_CCM_CGR0_EPIT1_MASK,
 114                 &ccm->cgr0);
 115
 116         writel(readl(&ccm->cgr1) |
 117                 MXC_CCM_CGR1_FEC_MASK |
 118                 MXC_CCM_CGR1_GPIO1_MASK |
 119                 MXC_CCM_CGR1_GPIO2_MASK |
 120                 MXC_CCM_CGR1_GPIO3_MASK |
 121                 MXC_CCM_CGR1_I2C1_MASK |
 122                 MXC_CCM_CGR1_I2C2_MASK |
 123                 MXC_CCM_CGR1_I2C3_MASK,
 124                 &ccm->cgr1);
 125
 126         /* Set-up NAND */
 127         __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
 128
 129         /* Set pinmux for the required peripherals */
 130         setup_iomux_fec();
 131
 132         /* setup GPIO1_4 FEC_ENABLE signal */
 133         mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5);
 134         gpio_direction_output(4, 1);
 135         mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5);
 136         gpio_direction_output(9, 0);
 137         gpio_set_value(9, 1);
 138
 139         return 0;
 140 }
 141
 142 #if defined(CONFIG_SPL_BUILD)
 143 void board_init_f(ulong dummy)
 144 {
 145         /* Set the stack pointer. */
 146         asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
 147
 148         /* Initialize MUX and SDRAM */
 149         woodburn_init();
 150
 151         /* Clear the BSS. */
 152         memset(__bss_start, 0, __bss_end__ - __bss_start);
 153
 154         /* Set global data pointer. */
 155         gd = &gdata;
 156
 157         preloader_console_init();
 158         timer_init();
 159
 160         board_init_r(NULL, 0);
 161 }
 162
 163 void spl_board_init(void)
 164 {
 165 }
 166
 167 #endif
 168
 169
 170 /* Booting from NOR in external mode */
 171 int board_early_init_f(void)
 172 {
 173         return woodburn_init();
 174 }
 175
 176
 177 int board_init(void)
 178 {
 179         struct pmic *p;
 180         u32 val;
 181
 182         /* address of boot parameters */
 183         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 184
 185         pmic_init();
 186         p = get_pmic();
 187
 188         /*
 189          * Set switchers in Auto in NORMAL mode & STANDBY mode
 190          * Setup the switcher mode for SW1 & SW2
 191          */
 192         pmic_reg_read(p, REG_SW_4, &val);
 193         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 194                 (SWMODE_MASK << SWMODE2_SHIFT)));
 195         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 196                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 197         /* Set SWILIMB */
 198         val |= (1 << 22);
 199         pmic_reg_write(p, REG_SW_4, val);
 200
 201         /* Setup the switcher mode for SW3 & SW4 */
 202         pmic_reg_read(p, REG_SW_5, &val);
 203         val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
 204                 (SWMODE_MASK << SWMODE3_SHIFT));
 205         val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
 206                 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
 207         pmic_reg_write(p, REG_SW_5, val);
 208
 209         /* Set VGEN1 to 3.15V */
 210         pmic_reg_read(p, REG_SETTING_0, &val);
 211         val &= ~(VGEN1_MASK);
 212         val |= VGEN1_3_15;
 213         pmic_reg_write(p, REG_SETTING_0, val);
 214
 215         pmic_reg_read(p, REG_MODE_0, &val);
 216         val |= VGEN1EN;
 217         pmic_reg_write(p, REG_MODE_0, val);
 218         udelay(2000);
 219
 220         return 0;
 221 }
 222
 223 #if defined(CONFIG_FSL_ESDHC)
 224 struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
 225
 226 int board_mmc_init(bd_t *bis)
 227 {
 228         /* configure pins for SDHC1 only */
 229         mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
 230         mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
 231         mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
 232         mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
 233         mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
 234         mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
 235
 236         /* MMC Card Detect on GPIO1_7 */
 237         mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_ALT5);
 238         mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1);
 239         gpio_direction_input(GPIO_MMC_CD);
 240
 241         mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5);
 242         mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1);
 243         gpio_direction_output(GPIO_MMC_WP, 0);
 244
 245         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 246
 247         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 248 }
 249
 250 int board_mmc_getcd(struct mmc *mmc)
 251 {
 252         return !gpio_get_value(GPIO_MMC_CD);
 253 }
 254 #endif
 255
 256 u32 get_board_rev(void)
 257 {
 258         int rev = 0;
 259
 260         return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
 261 }