2 * Copyright 2004 Freescale Semiconductor.
3 * Copyright (C) 2003 Motorola Inc.
4 * Xianghua Xiao (x.xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * PCI Configuration space access support for MPC85xx PCI Bridge
29 #include <asm/cpm_85xx.h>
32 #if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT)
34 static struct pci_controller
*pci_hose
;
37 pci_mpc85xx_init(struct pci_controller
*board_hose
)
42 volatile ccsr_pcix_t
*pcix
= (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR
);
43 #ifdef CONFIG_MPC85XX_PCI2
44 volatile ccsr_pcix_t
*pcix2
= (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR
);
46 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
47 struct pci_controller
* hose
;
49 pci_hose
= board_hose
;
53 hose
->first_busno
= 0;
54 hose
->last_busno
= 0xff;
56 pci_setup_indirect(hose
,
57 (CONFIG_SYS_IMMR
+0x8000),
58 (CONFIG_SYS_IMMR
+0x8004));
63 dev
= PCI_BDF(hose
->first_busno
, 0, 0);
64 pci_hose_read_config_word (hose
, dev
, PCI_COMMAND
, ®16
);
65 reg16
|= PCI_COMMAND_SERR
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
;
66 pci_hose_write_config_word(hose
, dev
, PCI_COMMAND
, reg16
);
69 * Clear non-reserved bits in status register.
71 pci_hose_write_config_word(hose
, dev
, PCI_STATUS
, 0xffff);
73 if (!(gur
->pordevsr
& PORDEVSR_PCI
)) {
75 if (CONFIG_SYS_CLK_FREQ
< 66000000)
76 printf("PCI-X will only work at 66 MHz\n");
78 reg16
= PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
79 | PCI_X_CMD_ERO
| PCI_X_CMD_DPERR_E
;
80 pci_hose_write_config_word(hose
, dev
, PCIX_COMMAND
, reg16
);
83 pcix
->potar1
= (CONFIG_SYS_PCI1_MEM_BASE
>> 12) & 0x000fffff;
84 pcix
->potear1
= 0x00000000;
85 pcix
->powbar1
= (CONFIG_SYS_PCI1_MEM_PHYS
>> 12) & 0x000fffff;
86 pcix
->powbear1
= 0x00000000;
87 pcix
->powar1
= (POWAR_EN
| POWAR_MEM_READ
|
88 POWAR_MEM_WRITE
| (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE
) - 1));
90 pcix
->potar2
= (CONFIG_SYS_PCI1_IO_BASE
>> 12) & 0x000fffff;
91 pcix
->potear2
= 0x00000000;
92 pcix
->powbar2
= (CONFIG_SYS_PCI1_IO_PHYS
>> 12) & 0x000fffff;
93 pcix
->powbear2
= 0x00000000;
94 pcix
->powar2
= (POWAR_EN
| POWAR_IO_READ
|
95 POWAR_IO_WRITE
| (__ilog2(CONFIG_SYS_PCI1_IO_SIZE
) - 1));
97 pcix
->pitar1
= 0x00000000;
98 pcix
->piwbar1
= 0x00000000;
99 pcix
->piwar1
= (PIWAR_EN
| PIWAR_PF
| PIWAR_LOCAL
|
100 PIWAR_READ_SNOOP
| PIWAR_WRITE_SNOOP
| PIWAR_MEM_2G
);
107 pci_set_region(hose
->regions
+ 0,
108 CONFIG_SYS_PCI1_MEM_BASE
,
109 CONFIG_SYS_PCI1_MEM_PHYS
,
110 CONFIG_SYS_PCI1_MEM_SIZE
,
113 pci_set_region(hose
->regions
+ 1,
114 CONFIG_SYS_PCI1_IO_BASE
,
115 CONFIG_SYS_PCI1_IO_PHYS
,
116 CONFIG_SYS_PCI1_IO_SIZE
,
119 hose
->region_count
= 2;
121 pci_register_hose(hose
);
123 #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
125 * This is a SW workaround for an apparent HW problem
126 * in the PCI controller on the MPC85555/41 CDS boards.
127 * The first config cycle must be to a valid, known
128 * device on the PCI bus in order to trick the PCI
129 * controller state machine into a known valid state.
130 * Without this, the first config cycle has the chance
131 * of hanging the controller permanently, just leaving
132 * it in a semi-working state, or leaving it working.
134 * Pick on the Tundra, Device 17, to get it right.
139 pci_hose_read_config_byte(hose
,
140 PCI_BDF(0,BRIDGE_ID
,0),
146 hose
->last_busno
= pci_hose_scan(hose
);
148 #ifdef CONFIG_MPC85XX_PCI2
151 hose
->first_busno
= pci_hose
[0].last_busno
+ 1;
152 hose
->last_busno
= 0xff;
154 pci_setup_indirect(hose
,
155 (CONFIG_SYS_IMMR
+0x9000),
156 (CONFIG_SYS_IMMR
+0x9004));
158 dev
= PCI_BDF(hose
->first_busno
, 0, 0);
159 pci_hose_read_config_word (hose
, dev
, PCI_COMMAND
, ®16
);
160 reg16
|= PCI_COMMAND_SERR
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
;
161 pci_hose_write_config_word(hose
, dev
, PCI_COMMAND
, reg16
);
164 * Clear non-reserved bits in status register.
166 pci_hose_write_config_word(hose
, dev
, PCI_STATUS
, 0xffff);
168 pcix2
->potar1
= (CONFIG_SYS_PCI2_MEM_BASE
>> 12) & 0x000fffff;
169 pcix2
->potear1
= 0x00000000;
170 pcix2
->powbar1
= (CONFIG_SYS_PCI2_MEM_PHYS
>> 12) & 0x000fffff;
171 pcix2
->powbear1
= 0x00000000;
172 pcix2
->powar1
= (POWAR_EN
| POWAR_MEM_READ
|
173 POWAR_MEM_WRITE
| (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE
) - 1));
175 pcix2
->potar2
= (CONFIG_SYS_PCI2_IO_BASE
>> 12) & 0x000fffff;
176 pcix2
->potear2
= 0x00000000;
177 pcix2
->powbar2
= (CONFIG_SYS_PCI2_IO_PHYS
>> 12) & 0x000fffff;
178 pcix2
->powbear2
= 0x00000000;
179 pcix2
->powar2
= (POWAR_EN
| POWAR_IO_READ
|
180 POWAR_IO_WRITE
| (__ilog2(CONFIG_SYS_PCI2_IO_SIZE
) - 1));
182 pcix2
->pitar1
= 0x00000000;
183 pcix2
->piwbar1
= 0x00000000;
184 pcix2
->piwar1
= (PIWAR_EN
| PIWAR_PF
| PIWAR_LOCAL
|
185 PIWAR_READ_SNOOP
| PIWAR_WRITE_SNOOP
| PIWAR_MEM_2G
);
192 pci_set_region(hose
->regions
+ 0,
193 CONFIG_SYS_PCI2_MEM_BASE
,
194 CONFIG_SYS_PCI2_MEM_PHYS
,
195 CONFIG_SYS_PCI2_MEM_SIZE
,
198 pci_set_region(hose
->regions
+ 1,
199 CONFIG_SYS_PCI2_IO_BASE
,
200 CONFIG_SYS_PCI2_IO_PHYS
,
201 CONFIG_SYS_PCI2_IO_SIZE
,
204 hose
->region_count
= 2;
209 pci_register_hose(hose
);
211 hose
->last_busno
= pci_hose_scan(hose
);
214 #endif /* CONFIG_PCI */