cpu/ppc4xx/ecc.c

   1 /*
   2  *    Copyright (c) 2008 Nuovation System Designs, LLC
   3  *      Grant Erickson <gerickson@nuovations.com>
   4  *
   5  *    (C) Copyright 2005-2007
   6  *    Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  *    (C) Copyright 2002
   9  *    Jun Gu, Artesyn Technology, jung@artesyncp.com
  10  *
  11  *    (C) Copyright 2001
  12  *    Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
  13  *
  14  *    See file CREDITS for list of people who contributed to this
  15  *    project.
  16  *
  17  *    This program is free software; you can redistribute it and/or
  18  *    modify it under the terms of the GNU General Public License as
  19  *    published by the Free Software Foundation; either version 2 of
  20  *    the License, or (at your option) any later version.
  21  *
  22  *    This program is distributed in the hope that it will abe useful,
  23  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25  *    GNU General Public License for more details.
  26  *
  27  *    You should have received a copy of the GNU General Public License
  28  *    along with this program; if not, write to the Free Software
  29  *    Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30  *    MA 02111-1307 USA
  31  *
  32  *    Description:
  33  *      This file implements generic DRAM ECC initialization for
  34  *      PowerPC processors using a SDRAM DDR/DDR2 controller,
  35  *      including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and
  36  *      460EX/GT.
  37  */
  38
  39 #include <common.h>
  40 #include <ppc4xx.h>
  41 #include <ppc_asm.tmpl>
  42 #include <ppc_defs.h>
  43 #include <asm/processor.h>
  44 #include <asm/io.h>
  45
  46 #include "ecc.h"
  47
  48 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \
  49     defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
  50 #if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
  51 /*
  52  *  void ecc_init()
  53  *
  54  *  Description:
  55  *    This routine initializes a range of DRAM ECC memory with known
  56  *    data and enables ECC checking.
  57  *
  58  *  TO DO:
  59  *    - Improve performance by utilizing cache.
  60  *    - Further generalize to make usable by other 4xx variants (e.g.
  61  *      440EPx, et al).
  62  *
  63  *  Input(s):
  64  *    start - A pointer to the start of memory covered by ECC requiring
  65  *            initialization.
  66  *    size  - The size, in bytes, of the memory covered by ECC requiring
  67  *            initialization.
  68  *
  69  *  Output(s):
  70  *    start - A pointer to the start of memory covered by ECC with
  71  *            CONFIG_SYS_ECC_PATTERN written to all locations and ECC data
  72  *            primed.
  73  *
  74  *  Returns:
  75  *    N/A
  76  */
  77 void ecc_init(unsigned long * const start, unsigned long size)
  78 {
  79         const unsigned long pattern = CONFIG_SYS_ECC_PATTERN;
  80         unsigned long * const end = (unsigned long * const)((long)start + size);
  81         unsigned long * current = start;
  82         unsigned long mcopt1;
  83         long increment;
  84
  85         if (start >= end)
  86                 return;
  87
  88         mfsdram(SDRAM_ECC_CFG, mcopt1);
  89
  90         /* Enable ECC generation without checking or reporting */
  91
  92         mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) |
  93                                 SDRAM_ECC_CFG_MCHK_GEN));
  94
  95         increment = sizeof(u32);
  96
  97 #if defined(CONFIG_440)
  98         /*
  99          * Look at the geometry of SDRAM (data width) to determine whether we
 100          * can skip words when writing.
 101          */
 102
 103         if ((mcopt1 & SDRAM_ECC_CFG_DMWD_MASK) != SDRAM_ECC_CFG_DMWD_32)
 104                 increment = sizeof(u64);
 105 #endif /* defined(CONFIG_440) */
 106
 107         while (current < end) {
 108                 *current = pattern;
 109                  current = (unsigned long *)((long)current + increment);
 110         }
 111
 112         /* Wait until the writes are finished. */
 113
 114         sync();
 115
 116         /* Enable ECC generation with checking and no reporting */
 117
 118         mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) |
 119                                 SDRAM_ECC_CFG_MCHK_CHK));
 120 }
 121 #endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
 122 #endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */