2 * (C) Copyright 2015 Google, Inc
3 * (C) 2017 Theobroma Systems Design und Consulting GmbH
5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cru_rk3399.h>
18 #include <asm/arch/hardware.h>
20 #include <dt-bindings/clock/rk3399-cru.h>
22 DECLARE_GLOBAL_DATA_PTR
;
24 #if CONFIG_IS_ENABLED(OF_PLATDATA)
25 struct rk3399_clk_plat
{
26 struct dtd_rockchip_rk3399_cru dtd
;
29 struct rk3399_pmuclk_plat
{
30 struct dtd_rockchip_rk3399_pmucru dtd
;
42 #define RATE_TO_DIV(input_rate, output_rate) \
43 ((input_rate) / (output_rate) - 1);
44 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
46 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
48 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
49 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
51 #if defined(CONFIG_SPL_BUILD)
52 static const struct pll_div gpll_init_cfg
= PLL_DIVISORS(GPLL_HZ
, 2, 2, 1);
53 static const struct pll_div cpll_init_cfg
= PLL_DIVISORS(CPLL_HZ
, 1, 2, 2);
55 static const struct pll_div ppll_init_cfg
= PLL_DIVISORS(PPLL_HZ
, 2, 2, 1);
58 static const struct pll_div apll_l_1600_cfg
= PLL_DIVISORS(1600*MHz
, 3, 1, 1);
59 static const struct pll_div apll_l_600_cfg
= PLL_DIVISORS(600*MHz
, 1, 2, 1);
61 static const struct pll_div
*apll_l_cfgs
[] = {
62 [APLL_L_1600_MHZ
] = &apll_l_1600_cfg
,
63 [APLL_L_600_MHZ
] = &apll_l_600_cfg
,
68 PLL_FBDIV_MASK
= 0xfff,
72 PLL_POSTDIV2_SHIFT
= 12,
73 PLL_POSTDIV2_MASK
= 0x7 << PLL_POSTDIV2_SHIFT
,
74 PLL_POSTDIV1_SHIFT
= 8,
75 PLL_POSTDIV1_MASK
= 0x7 << PLL_POSTDIV1_SHIFT
,
76 PLL_REFDIV_MASK
= 0x3f,
80 PLL_LOCK_STATUS_SHIFT
= 31,
81 PLL_LOCK_STATUS_MASK
= 1 << PLL_LOCK_STATUS_SHIFT
,
82 PLL_FRACDIV_MASK
= 0xffffff,
83 PLL_FRACDIV_SHIFT
= 0,
87 PLL_MODE_MASK
= 3 << PLL_MODE_SHIFT
,
92 PLL_DSMPD_MASK
= 1 << PLL_DSMPD_SHIFT
,
95 /* PMUCRU_CLKSEL_CON0 */
96 PMU_PCLK_DIV_CON_MASK
= 0x1f,
97 PMU_PCLK_DIV_CON_SHIFT
= 0,
99 /* PMUCRU_CLKSEL_CON1 */
100 SPI3_PLL_SEL_SHIFT
= 7,
101 SPI3_PLL_SEL_MASK
= 1 << SPI3_PLL_SEL_SHIFT
,
102 SPI3_PLL_SEL_24M
= 0,
103 SPI3_PLL_SEL_PPLL
= 1,
104 SPI3_DIV_CON_SHIFT
= 0x0,
105 SPI3_DIV_CON_MASK
= 0x7f,
107 /* PMUCRU_CLKSEL_CON2 */
108 I2C_DIV_CON_MASK
= 0x7f,
109 CLK_I2C8_DIV_CON_SHIFT
= 8,
110 CLK_I2C0_DIV_CON_SHIFT
= 0,
112 /* PMUCRU_CLKSEL_CON3 */
113 CLK_I2C4_DIV_CON_SHIFT
= 0,
116 ACLKM_CORE_L_DIV_CON_SHIFT
= 8,
117 ACLKM_CORE_L_DIV_CON_MASK
= 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT
,
118 CLK_CORE_L_PLL_SEL_SHIFT
= 6,
119 CLK_CORE_L_PLL_SEL_MASK
= 3 << CLK_CORE_L_PLL_SEL_SHIFT
,
120 CLK_CORE_L_PLL_SEL_ALPLL
= 0x0,
121 CLK_CORE_L_PLL_SEL_ABPLL
= 0x1,
122 CLK_CORE_L_PLL_SEL_DPLL
= 0x10,
123 CLK_CORE_L_PLL_SEL_GPLL
= 0x11,
124 CLK_CORE_L_DIV_MASK
= 0x1f,
125 CLK_CORE_L_DIV_SHIFT
= 0,
128 PCLK_DBG_L_DIV_SHIFT
= 0x8,
129 PCLK_DBG_L_DIV_MASK
= 0x1f << PCLK_DBG_L_DIV_SHIFT
,
130 ATCLK_CORE_L_DIV_SHIFT
= 0,
131 ATCLK_CORE_L_DIV_MASK
= 0x1f << ATCLK_CORE_L_DIV_SHIFT
,
134 PCLK_PERIHP_DIV_CON_SHIFT
= 12,
135 PCLK_PERIHP_DIV_CON_MASK
= 0x7 << PCLK_PERIHP_DIV_CON_SHIFT
,
136 HCLK_PERIHP_DIV_CON_SHIFT
= 8,
137 HCLK_PERIHP_DIV_CON_MASK
= 3 << HCLK_PERIHP_DIV_CON_SHIFT
,
138 ACLK_PERIHP_PLL_SEL_SHIFT
= 7,
139 ACLK_PERIHP_PLL_SEL_MASK
= 1 << ACLK_PERIHP_PLL_SEL_SHIFT
,
140 ACLK_PERIHP_PLL_SEL_CPLL
= 0,
141 ACLK_PERIHP_PLL_SEL_GPLL
= 1,
142 ACLK_PERIHP_DIV_CON_SHIFT
= 0,
143 ACLK_PERIHP_DIV_CON_MASK
= 0x1f,
146 ACLK_EMMC_PLL_SEL_SHIFT
= 7,
147 ACLK_EMMC_PLL_SEL_MASK
= 0x1 << ACLK_EMMC_PLL_SEL_SHIFT
,
148 ACLK_EMMC_PLL_SEL_GPLL
= 0x1,
149 ACLK_EMMC_DIV_CON_SHIFT
= 0,
150 ACLK_EMMC_DIV_CON_MASK
= 0x1f,
153 CLK_EMMC_PLL_SHIFT
= 8,
154 CLK_EMMC_PLL_MASK
= 0x7 << CLK_EMMC_PLL_SHIFT
,
155 CLK_EMMC_PLL_SEL_GPLL
= 0x1,
156 CLK_EMMC_PLL_SEL_24M
= 0x5,
157 CLK_EMMC_DIV_CON_SHIFT
= 0,
158 CLK_EMMC_DIV_CON_MASK
= 0x7f << CLK_EMMC_DIV_CON_SHIFT
,
161 PCLK_PERILP0_DIV_CON_SHIFT
= 12,
162 PCLK_PERILP0_DIV_CON_MASK
= 0x7 << PCLK_PERILP0_DIV_CON_SHIFT
,
163 HCLK_PERILP0_DIV_CON_SHIFT
= 8,
164 HCLK_PERILP0_DIV_CON_MASK
= 3 << HCLK_PERILP0_DIV_CON_SHIFT
,
165 ACLK_PERILP0_PLL_SEL_SHIFT
= 7,
166 ACLK_PERILP0_PLL_SEL_MASK
= 1 << ACLK_PERILP0_PLL_SEL_SHIFT
,
167 ACLK_PERILP0_PLL_SEL_CPLL
= 0,
168 ACLK_PERILP0_PLL_SEL_GPLL
= 1,
169 ACLK_PERILP0_DIV_CON_SHIFT
= 0,
170 ACLK_PERILP0_DIV_CON_MASK
= 0x1f,
173 PCLK_PERILP1_DIV_CON_SHIFT
= 8,
174 PCLK_PERILP1_DIV_CON_MASK
= 0x7 << PCLK_PERILP1_DIV_CON_SHIFT
,
175 HCLK_PERILP1_PLL_SEL_SHIFT
= 7,
176 HCLK_PERILP1_PLL_SEL_MASK
= 1 << HCLK_PERILP1_PLL_SEL_SHIFT
,
177 HCLK_PERILP1_PLL_SEL_CPLL
= 0,
178 HCLK_PERILP1_PLL_SEL_GPLL
= 1,
179 HCLK_PERILP1_DIV_CON_SHIFT
= 0,
180 HCLK_PERILP1_DIV_CON_MASK
= 0x1f,
183 CLK_SARADC_DIV_CON_SHIFT
= 8,
184 CLK_SARADC_DIV_CON_MASK
= 0xff << CLK_SARADC_DIV_CON_SHIFT
,
187 CLK_TSADC_SEL_X24M
= 0x0,
188 CLK_TSADC_SEL_SHIFT
= 15,
189 CLK_TSADC_SEL_MASK
= 1 << CLK_TSADC_SEL_SHIFT
,
190 CLK_TSADC_DIV_CON_SHIFT
= 0,
191 CLK_TSADC_DIV_CON_MASK
= 0x3ff,
193 /* CLKSEL_CON47 & CLKSEL_CON48 */
194 ACLK_VOP_PLL_SEL_SHIFT
= 6,
195 ACLK_VOP_PLL_SEL_MASK
= 0x3 << ACLK_VOP_PLL_SEL_SHIFT
,
196 ACLK_VOP_PLL_SEL_CPLL
= 0x1,
197 ACLK_VOP_DIV_CON_SHIFT
= 0,
198 ACLK_VOP_DIV_CON_MASK
= 0x1f << ACLK_VOP_DIV_CON_SHIFT
,
200 /* CLKSEL_CON49 & CLKSEL_CON50 */
201 DCLK_VOP_DCLK_SEL_SHIFT
= 11,
202 DCLK_VOP_DCLK_SEL_MASK
= 1 << DCLK_VOP_DCLK_SEL_SHIFT
,
203 DCLK_VOP_DCLK_SEL_DIVOUT
= 0,
204 DCLK_VOP_PLL_SEL_SHIFT
= 8,
205 DCLK_VOP_PLL_SEL_MASK
= 3 << DCLK_VOP_PLL_SEL_SHIFT
,
206 DCLK_VOP_PLL_SEL_VPLL
= 0,
207 DCLK_VOP_DIV_CON_MASK
= 0xff,
208 DCLK_VOP_DIV_CON_SHIFT
= 0,
211 CLK_SPI_PLL_SEL_WIDTH
= 1,
212 CLK_SPI_PLL_SEL_MASK
= ((1 < CLK_SPI_PLL_SEL_WIDTH
) - 1),
213 CLK_SPI_PLL_SEL_CPLL
= 0,
214 CLK_SPI_PLL_SEL_GPLL
= 1,
215 CLK_SPI_PLL_DIV_CON_WIDTH
= 7,
216 CLK_SPI_PLL_DIV_CON_MASK
= ((1 << CLK_SPI_PLL_DIV_CON_WIDTH
) - 1),
218 CLK_SPI5_PLL_DIV_CON_SHIFT
= 8,
219 CLK_SPI5_PLL_SEL_SHIFT
= 15,
222 CLK_SPI1_PLL_SEL_SHIFT
= 15,
223 CLK_SPI1_PLL_DIV_CON_SHIFT
= 8,
224 CLK_SPI0_PLL_SEL_SHIFT
= 7,
225 CLK_SPI0_PLL_DIV_CON_SHIFT
= 0,
228 CLK_SPI4_PLL_SEL_SHIFT
= 15,
229 CLK_SPI4_PLL_DIV_CON_SHIFT
= 8,
230 CLK_SPI2_PLL_SEL_SHIFT
= 7,
231 CLK_SPI2_PLL_DIV_CON_SHIFT
= 0,
234 CLK_I2C_PLL_SEL_MASK
= 1,
235 CLK_I2C_PLL_SEL_CPLL
= 0,
236 CLK_I2C_PLL_SEL_GPLL
= 1,
237 CLK_I2C5_PLL_SEL_SHIFT
= 15,
238 CLK_I2C5_DIV_CON_SHIFT
= 8,
239 CLK_I2C1_PLL_SEL_SHIFT
= 7,
240 CLK_I2C1_DIV_CON_SHIFT
= 0,
243 CLK_I2C6_PLL_SEL_SHIFT
= 15,
244 CLK_I2C6_DIV_CON_SHIFT
= 8,
245 CLK_I2C2_PLL_SEL_SHIFT
= 7,
246 CLK_I2C2_DIV_CON_SHIFT
= 0,
249 CLK_I2C7_PLL_SEL_SHIFT
= 15,
250 CLK_I2C7_DIV_CON_SHIFT
= 8,
251 CLK_I2C3_PLL_SEL_SHIFT
= 7,
252 CLK_I2C3_DIV_CON_SHIFT
= 0,
254 /* CRU_SOFTRST_CON4 */
255 RESETN_DDR0_REQ_SHIFT
= 8,
256 RESETN_DDR0_REQ_MASK
= 1 << RESETN_DDR0_REQ_SHIFT
,
257 RESETN_DDRPHY0_REQ_SHIFT
= 9,
258 RESETN_DDRPHY0_REQ_MASK
= 1 << RESETN_DDRPHY0_REQ_SHIFT
,
259 RESETN_DDR1_REQ_SHIFT
= 12,
260 RESETN_DDR1_REQ_MASK
= 1 << RESETN_DDR1_REQ_SHIFT
,
261 RESETN_DDRPHY1_REQ_SHIFT
= 13,
262 RESETN_DDRPHY1_REQ_MASK
= 1 << RESETN_DDRPHY1_REQ_SHIFT
,
265 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
266 #define VCO_MIN_KHZ (800 * (MHz / KHz))
267 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
268 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
271 * the div restructions of pll in integer mode, these are defined in
272 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
274 #define PLL_DIV_MIN 16
275 #define PLL_DIV_MAX 3200
278 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
279 * Formulas also embedded within the Fractional PLL Verilog model:
280 * If DSMPD = 1 (DSM is disabled, "integer mode")
281 * FOUTVCO = FREF / REFDIV * FBDIV
282 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
284 * FOUTVCO = Fractional PLL non-divided output frequency
285 * FOUTPOSTDIV = Fractional PLL divided output frequency
286 * (output of second post divider)
287 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
288 * REFDIV = Fractional PLL input reference clock divider
289 * FBDIV = Integer value programmed into feedback divide
292 static void rkclk_set_pll(u32
*pll_con
, const struct pll_div
*div
)
294 /* All 8 PLLs have same VCO and output frequency range restrictions. */
295 u32 vco_khz
= OSC_HZ
/ 1000 * div
->fbdiv
/ div
->refdiv
;
296 u32 output_khz
= vco_khz
/ div
->postdiv1
/ div
->postdiv2
;
298 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
299 "postdiv2=%d, vco=%u khz, output=%u khz\n",
300 pll_con
, div
->fbdiv
, div
->refdiv
, div
->postdiv1
,
301 div
->postdiv2
, vco_khz
, output_khz
);
302 assert(vco_khz
>= VCO_MIN_KHZ
&& vco_khz
<= VCO_MAX_KHZ
&&
303 output_khz
>= OUTPUT_MIN_KHZ
&& output_khz
<= OUTPUT_MAX_KHZ
&&
304 div
->fbdiv
>= PLL_DIV_MIN
&& div
->fbdiv
<= PLL_DIV_MAX
);
307 * When power on or changing PLL setting,
308 * we must force PLL into slow mode to ensure output stable clock.
310 rk_clrsetreg(&pll_con
[3], PLL_MODE_MASK
,
311 PLL_MODE_SLOW
<< PLL_MODE_SHIFT
);
313 /* use integer mode */
314 rk_clrsetreg(&pll_con
[3], PLL_DSMPD_MASK
,
315 PLL_INTEGER_MODE
<< PLL_DSMPD_SHIFT
);
317 rk_clrsetreg(&pll_con
[0], PLL_FBDIV_MASK
,
318 div
->fbdiv
<< PLL_FBDIV_SHIFT
);
319 rk_clrsetreg(&pll_con
[1],
320 PLL_POSTDIV2_MASK
| PLL_POSTDIV1_MASK
|
321 PLL_REFDIV_MASK
| PLL_REFDIV_SHIFT
,
322 (div
->postdiv2
<< PLL_POSTDIV2_SHIFT
) |
323 (div
->postdiv1
<< PLL_POSTDIV1_SHIFT
) |
324 (div
->refdiv
<< PLL_REFDIV_SHIFT
));
326 /* waiting for pll lock */
327 while (!(readl(&pll_con
[2]) & (1 << PLL_LOCK_STATUS_SHIFT
)))
330 /* pll enter normal mode */
331 rk_clrsetreg(&pll_con
[3], PLL_MODE_MASK
,
332 PLL_MODE_NORM
<< PLL_MODE_SHIFT
);
335 static int pll_para_config(u32 freq_hz
, struct pll_div
*div
)
337 u32 ref_khz
= OSC_HZ
/ KHz
, refdiv
, fbdiv
= 0;
338 u32 postdiv1
, postdiv2
= 1;
340 u32 diff_khz
, best_diff_khz
;
341 const u32 max_refdiv
= 63, max_fbdiv
= 3200, min_fbdiv
= 16;
342 const u32 max_postdiv1
= 7, max_postdiv2
= 7;
344 u32 freq_khz
= freq_hz
/ KHz
;
347 printf("%s: the frequency can't be 0 Hz\n", __func__
);
351 postdiv1
= DIV_ROUND_UP(VCO_MIN_KHZ
, freq_khz
);
352 if (postdiv1
> max_postdiv1
) {
353 postdiv2
= DIV_ROUND_UP(postdiv1
, max_postdiv1
);
354 postdiv1
= DIV_ROUND_UP(postdiv1
, postdiv2
);
357 vco_khz
= freq_khz
* postdiv1
* postdiv2
;
359 if (vco_khz
< VCO_MIN_KHZ
|| vco_khz
> VCO_MAX_KHZ
||
360 postdiv2
> max_postdiv2
) {
361 printf("%s: Cannot find out a supported VCO"
362 " for Frequency (%uHz).\n", __func__
, freq_hz
);
366 div
->postdiv1
= postdiv1
;
367 div
->postdiv2
= postdiv2
;
369 best_diff_khz
= vco_khz
;
370 for (refdiv
= 1; refdiv
< max_refdiv
&& best_diff_khz
; refdiv
++) {
371 fref_khz
= ref_khz
/ refdiv
;
373 fbdiv
= vco_khz
/ fref_khz
;
374 if ((fbdiv
>= max_fbdiv
) || (fbdiv
<= min_fbdiv
))
376 diff_khz
= vco_khz
- fbdiv
* fref_khz
;
377 if (fbdiv
+ 1 < max_fbdiv
&& diff_khz
> fref_khz
/ 2) {
379 diff_khz
= fref_khz
- diff_khz
;
382 if (diff_khz
>= best_diff_khz
)
385 best_diff_khz
= diff_khz
;
386 div
->refdiv
= refdiv
;
390 if (best_diff_khz
> 4 * (MHz
/KHz
)) {
391 printf("%s: Failed to match output frequency %u, "
392 "difference is %u Hz,exceed 4MHZ\n", __func__
, freq_hz
,
393 best_diff_khz
* KHz
);
399 #ifdef CONFIG_SPL_BUILD
400 static void rkclk_init(struct rk3399_cru
*cru
)
407 * some cru registers changed by bootrom, we'd better reset them to
408 * reset/default values described in TRM to avoid confusion in kernel.
409 * Please consider these three lines as a fix of bootrom bug.
411 rk_clrsetreg(&cru
->clksel_con
[12], 0xffff, 0x4101);
412 rk_clrsetreg(&cru
->clksel_con
[19], 0xffff, 0x033f);
413 rk_clrsetreg(&cru
->clksel_con
[56], 0x0003, 0x0003);
415 /* configure gpll cpll */
416 rkclk_set_pll(&cru
->gpll_con
[0], &gpll_init_cfg
);
417 rkclk_set_pll(&cru
->cpll_con
[0], &cpll_init_cfg
);
419 /* configure perihp aclk, hclk, pclk */
420 aclk_div
= GPLL_HZ
/ PERIHP_ACLK_HZ
- 1;
421 assert((aclk_div
+ 1) * PERIHP_ACLK_HZ
== GPLL_HZ
&& aclk_div
< 0x1f);
423 hclk_div
= PERIHP_ACLK_HZ
/ PERIHP_HCLK_HZ
- 1;
424 assert((hclk_div
+ 1) * PERIHP_HCLK_HZ
==
425 PERIHP_ACLK_HZ
&& (hclk_div
< 0x4));
427 pclk_div
= PERIHP_ACLK_HZ
/ PERIHP_PCLK_HZ
- 1;
428 assert((pclk_div
+ 1) * PERIHP_PCLK_HZ
==
429 PERIHP_ACLK_HZ
&& (pclk_div
< 0x7));
431 rk_clrsetreg(&cru
->clksel_con
[14],
432 PCLK_PERIHP_DIV_CON_MASK
| HCLK_PERIHP_DIV_CON_MASK
|
433 ACLK_PERIHP_PLL_SEL_MASK
| ACLK_PERIHP_DIV_CON_MASK
,
434 pclk_div
<< PCLK_PERIHP_DIV_CON_SHIFT
|
435 hclk_div
<< HCLK_PERIHP_DIV_CON_SHIFT
|
436 ACLK_PERIHP_PLL_SEL_GPLL
<< ACLK_PERIHP_PLL_SEL_SHIFT
|
437 aclk_div
<< ACLK_PERIHP_DIV_CON_SHIFT
);
439 /* configure perilp0 aclk, hclk, pclk */
440 aclk_div
= GPLL_HZ
/ PERILP0_ACLK_HZ
- 1;
441 assert((aclk_div
+ 1) * PERILP0_ACLK_HZ
== GPLL_HZ
&& aclk_div
< 0x1f);
443 hclk_div
= PERILP0_ACLK_HZ
/ PERILP0_HCLK_HZ
- 1;
444 assert((hclk_div
+ 1) * PERILP0_HCLK_HZ
==
445 PERILP0_ACLK_HZ
&& (hclk_div
< 0x4));
447 pclk_div
= PERILP0_ACLK_HZ
/ PERILP0_PCLK_HZ
- 1;
448 assert((pclk_div
+ 1) * PERILP0_PCLK_HZ
==
449 PERILP0_ACLK_HZ
&& (pclk_div
< 0x7));
451 rk_clrsetreg(&cru
->clksel_con
[23],
452 PCLK_PERILP0_DIV_CON_MASK
| HCLK_PERILP0_DIV_CON_MASK
|
453 ACLK_PERILP0_PLL_SEL_MASK
| ACLK_PERILP0_DIV_CON_MASK
,
454 pclk_div
<< PCLK_PERILP0_DIV_CON_SHIFT
|
455 hclk_div
<< HCLK_PERILP0_DIV_CON_SHIFT
|
456 ACLK_PERILP0_PLL_SEL_GPLL
<< ACLK_PERILP0_PLL_SEL_SHIFT
|
457 aclk_div
<< ACLK_PERILP0_DIV_CON_SHIFT
);
459 /* perilp1 hclk select gpll as source */
460 hclk_div
= GPLL_HZ
/ PERILP1_HCLK_HZ
- 1;
461 assert((hclk_div
+ 1) * PERILP1_HCLK_HZ
==
462 GPLL_HZ
&& (hclk_div
< 0x1f));
464 pclk_div
= PERILP1_HCLK_HZ
/ PERILP1_HCLK_HZ
- 1;
465 assert((pclk_div
+ 1) * PERILP1_HCLK_HZ
==
466 PERILP1_HCLK_HZ
&& (hclk_div
< 0x7));
468 rk_clrsetreg(&cru
->clksel_con
[25],
469 PCLK_PERILP1_DIV_CON_MASK
| HCLK_PERILP1_DIV_CON_MASK
|
470 HCLK_PERILP1_PLL_SEL_MASK
,
471 pclk_div
<< PCLK_PERILP1_DIV_CON_SHIFT
|
472 hclk_div
<< HCLK_PERILP1_DIV_CON_SHIFT
|
473 HCLK_PERILP1_PLL_SEL_GPLL
<< HCLK_PERILP1_PLL_SEL_SHIFT
);
477 void rk3399_configure_cpu(struct rk3399_cru
*cru
,
478 enum apll_l_frequencies apll_l_freq
)
484 rkclk_set_pll(&cru
->apll_l_con
[0], apll_l_cfgs
[apll_l_freq
]);
486 aclkm_div
= APLL_HZ
/ ACLKM_CORE_HZ
- 1;
487 assert((aclkm_div
+ 1) * ACLKM_CORE_HZ
== APLL_HZ
&&
490 pclk_dbg_div
= APLL_HZ
/ PCLK_DBG_HZ
- 1;
491 assert((pclk_dbg_div
+ 1) * PCLK_DBG_HZ
== APLL_HZ
&&
492 pclk_dbg_div
< 0x1f);
494 atclk_div
= APLL_HZ
/ ATCLK_CORE_HZ
- 1;
495 assert((atclk_div
+ 1) * ATCLK_CORE_HZ
== APLL_HZ
&&
498 rk_clrsetreg(&cru
->clksel_con
[0],
499 ACLKM_CORE_L_DIV_CON_MASK
| CLK_CORE_L_PLL_SEL_MASK
|
501 aclkm_div
<< ACLKM_CORE_L_DIV_CON_SHIFT
|
502 CLK_CORE_L_PLL_SEL_ALPLL
<< CLK_CORE_L_PLL_SEL_SHIFT
|
503 0 << CLK_CORE_L_DIV_SHIFT
);
505 rk_clrsetreg(&cru
->clksel_con
[1],
506 PCLK_DBG_L_DIV_MASK
| ATCLK_CORE_L_DIV_MASK
,
507 pclk_dbg_div
<< PCLK_DBG_L_DIV_SHIFT
|
508 atclk_div
<< ATCLK_CORE_L_DIV_SHIFT
);
510 #define I2C_CLK_REG_MASK(bus) \
511 (I2C_DIV_CON_MASK << \
512 CLK_I2C ##bus## _DIV_CON_SHIFT | \
513 CLK_I2C_PLL_SEL_MASK << \
514 CLK_I2C ##bus## _PLL_SEL_SHIFT)
516 #define I2C_CLK_REG_VALUE(bus, clk_div) \
518 CLK_I2C ##bus## _DIV_CON_SHIFT | \
519 CLK_I2C_PLL_SEL_GPLL << \
520 CLK_I2C ##bus## _PLL_SEL_SHIFT)
522 #define I2C_CLK_DIV_VALUE(con, bus) \
523 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
526 #define I2C_PMUCLK_REG_MASK(bus) \
527 (I2C_DIV_CON_MASK << \
528 CLK_I2C ##bus## _DIV_CON_SHIFT)
530 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
532 CLK_I2C ##bus## _DIV_CON_SHIFT)
534 static ulong
rk3399_i2c_get_clk(struct rk3399_cru
*cru
, ulong clk_id
)
540 con
= readl(&cru
->clksel_con
[61]);
541 div
= I2C_CLK_DIV_VALUE(con
, 1);
544 con
= readl(&cru
->clksel_con
[62]);
545 div
= I2C_CLK_DIV_VALUE(con
, 2);
548 con
= readl(&cru
->clksel_con
[63]);
549 div
= I2C_CLK_DIV_VALUE(con
, 3);
552 con
= readl(&cru
->clksel_con
[61]);
553 div
= I2C_CLK_DIV_VALUE(con
, 5);
556 con
= readl(&cru
->clksel_con
[62]);
557 div
= I2C_CLK_DIV_VALUE(con
, 6);
560 con
= readl(&cru
->clksel_con
[63]);
561 div
= I2C_CLK_DIV_VALUE(con
, 7);
564 printf("do not support this i2c bus\n");
568 return DIV_TO_RATE(GPLL_HZ
, div
);
571 static ulong
rk3399_i2c_set_clk(struct rk3399_cru
*cru
, ulong clk_id
, uint hz
)
575 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
576 src_clk_div
= GPLL_HZ
/ hz
;
577 assert(src_clk_div
- 1 < 127);
581 rk_clrsetreg(&cru
->clksel_con
[61], I2C_CLK_REG_MASK(1),
582 I2C_CLK_REG_VALUE(1, src_clk_div
));
585 rk_clrsetreg(&cru
->clksel_con
[62], I2C_CLK_REG_MASK(2),
586 I2C_CLK_REG_VALUE(2, src_clk_div
));
589 rk_clrsetreg(&cru
->clksel_con
[63], I2C_CLK_REG_MASK(3),
590 I2C_CLK_REG_VALUE(3, src_clk_div
));
593 rk_clrsetreg(&cru
->clksel_con
[61], I2C_CLK_REG_MASK(5),
594 I2C_CLK_REG_VALUE(5, src_clk_div
));
597 rk_clrsetreg(&cru
->clksel_con
[62], I2C_CLK_REG_MASK(6),
598 I2C_CLK_REG_VALUE(6, src_clk_div
));
601 rk_clrsetreg(&cru
->clksel_con
[63], I2C_CLK_REG_MASK(7),
602 I2C_CLK_REG_VALUE(7, src_clk_div
));
605 printf("do not support this i2c bus\n");
609 return rk3399_i2c_get_clk(cru
, clk_id
);
613 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
614 * to select either CPLL or GPLL as the clock-parent. The location within
615 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
619 uint8_t reg
; /* CLKSEL_CON[reg] register in CRU */
625 * The entries are numbered relative to their offset from SCLK_SPI0.
627 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
628 * logic is not supported).
630 static const struct spi_clkreg spi_clkregs
[] = {
632 .div_shift
= CLK_SPI0_PLL_DIV_CON_SHIFT
,
633 .sel_shift
= CLK_SPI0_PLL_SEL_SHIFT
, },
635 .div_shift
= CLK_SPI1_PLL_DIV_CON_SHIFT
,
636 .sel_shift
= CLK_SPI1_PLL_SEL_SHIFT
, },
638 .div_shift
= CLK_SPI2_PLL_DIV_CON_SHIFT
,
639 .sel_shift
= CLK_SPI2_PLL_SEL_SHIFT
, },
641 .div_shift
= CLK_SPI4_PLL_DIV_CON_SHIFT
,
642 .sel_shift
= CLK_SPI4_PLL_SEL_SHIFT
, },
644 .div_shift
= CLK_SPI5_PLL_DIV_CON_SHIFT
,
645 .sel_shift
= CLK_SPI5_PLL_SEL_SHIFT
, },
648 static inline u32
extract_bits(u32 val
, unsigned width
, unsigned shift
)
650 return (val
>> shift
) & ((1 << width
) - 1);
653 static ulong
rk3399_spi_get_clk(struct rk3399_cru
*cru
, ulong clk_id
)
655 const struct spi_clkreg
*spiclk
= NULL
;
659 case SCLK_SPI0
... SCLK_SPI5
:
660 spiclk
= &spi_clkregs
[clk_id
- SCLK_SPI0
];
664 error("%s: SPI clk-id %ld not supported\n", __func__
, clk_id
);
668 val
= readl(&cru
->clksel_con
[spiclk
->reg
]);
669 div
= extract_bits(val
, CLK_SPI_PLL_DIV_CON_WIDTH
, spiclk
->div_shift
);
671 return DIV_TO_RATE(GPLL_HZ
, div
);
674 static ulong
rk3399_spi_set_clk(struct rk3399_cru
*cru
, ulong clk_id
, uint hz
)
676 const struct spi_clkreg
*spiclk
= NULL
;
679 src_clk_div
= DIV_ROUND_UP(GPLL_HZ
, hz
) - 1;
680 assert(src_clk_div
< 128);
683 case SCLK_SPI1
... SCLK_SPI5
:
684 spiclk
= &spi_clkregs
[clk_id
- SCLK_SPI0
];
688 error("%s: SPI clk-id %ld not supported\n", __func__
, clk_id
);
692 rk_clrsetreg(&cru
->clksel_con
[spiclk
->reg
],
693 ((CLK_SPI_PLL_DIV_CON_MASK
<< spiclk
->div_shift
) |
694 (CLK_SPI_PLL_SEL_GPLL
<< spiclk
->sel_shift
)),
695 ((src_clk_div
<< spiclk
->div_shift
) |
696 (CLK_SPI_PLL_SEL_GPLL
<< spiclk
->sel_shift
)));
698 return rk3399_spi_get_clk(cru
, clk_id
);
701 static ulong
rk3399_vop_set_clk(struct rk3399_cru
*cru
, ulong clk_id
, u32 hz
)
703 struct pll_div vpll_config
= {0};
704 int aclk_vop
= 198*MHz
;
705 void *aclkreg_addr
, *dclkreg_addr
;
710 aclkreg_addr
= &cru
->clksel_con
[47];
711 dclkreg_addr
= &cru
->clksel_con
[49];
714 aclkreg_addr
= &cru
->clksel_con
[48];
715 dclkreg_addr
= &cru
->clksel_con
[50];
720 /* vop aclk source clk: cpll */
721 div
= CPLL_HZ
/ aclk_vop
;
722 assert(div
- 1 < 32);
724 rk_clrsetreg(aclkreg_addr
,
725 ACLK_VOP_PLL_SEL_MASK
| ACLK_VOP_DIV_CON_MASK
,
726 ACLK_VOP_PLL_SEL_CPLL
<< ACLK_VOP_PLL_SEL_SHIFT
|
727 (div
- 1) << ACLK_VOP_DIV_CON_SHIFT
);
729 /* vop dclk source from vpll, and equals to vpll(means div == 1) */
730 if (pll_para_config(hz
, &vpll_config
))
733 rkclk_set_pll(&cru
->vpll_con
[0], &vpll_config
);
735 rk_clrsetreg(dclkreg_addr
,
736 DCLK_VOP_DCLK_SEL_MASK
| DCLK_VOP_PLL_SEL_MASK
|
737 DCLK_VOP_DIV_CON_MASK
,
738 DCLK_VOP_DCLK_SEL_DIVOUT
<< DCLK_VOP_DCLK_SEL_SHIFT
|
739 DCLK_VOP_PLL_SEL_VPLL
<< DCLK_VOP_PLL_SEL_SHIFT
|
740 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT
);
745 static ulong
rk3399_mmc_get_clk(struct rk3399_cru
*cru
, uint clk_id
)
752 con
= readl(&cru
->clksel_con
[16]);
753 /* dwmmc controller have internal div 2 */
757 con
= readl(&cru
->clksel_con
[21]);
764 div
*= (con
& CLK_EMMC_DIV_CON_MASK
) >> CLK_EMMC_DIV_CON_SHIFT
;
765 if ((con
& CLK_EMMC_PLL_MASK
) >> CLK_EMMC_PLL_SHIFT
766 == CLK_EMMC_PLL_SEL_24M
)
767 return DIV_TO_RATE(OSC_HZ
, div
);
769 return DIV_TO_RATE(GPLL_HZ
, div
);
772 static ulong
rk3399_mmc_set_clk(struct rk3399_cru
*cru
,
773 ulong clk_id
, ulong set_rate
)
776 int aclk_emmc
= 198*MHz
;
781 /* Select clk_sdmmc source from GPLL by default */
782 /* mmc clock defaulg div 2 internal, provide double in cru */
783 src_clk_div
= DIV_ROUND_UP(GPLL_HZ
/ 2, set_rate
);
785 if (src_clk_div
> 128) {
786 /* use 24MHz source for 400KHz clock */
787 src_clk_div
= DIV_ROUND_UP(OSC_HZ
/ 2, set_rate
);
788 assert(src_clk_div
- 1 < 128);
789 rk_clrsetreg(&cru
->clksel_con
[16],
790 CLK_EMMC_PLL_MASK
| CLK_EMMC_DIV_CON_MASK
,
791 CLK_EMMC_PLL_SEL_24M
<< CLK_EMMC_PLL_SHIFT
|
792 (src_clk_div
- 1) << CLK_EMMC_DIV_CON_SHIFT
);
794 rk_clrsetreg(&cru
->clksel_con
[16],
795 CLK_EMMC_PLL_MASK
| CLK_EMMC_DIV_CON_MASK
,
796 CLK_EMMC_PLL_SEL_GPLL
<< CLK_EMMC_PLL_SHIFT
|
797 (src_clk_div
- 1) << CLK_EMMC_DIV_CON_SHIFT
);
801 /* Select aclk_emmc source from GPLL */
802 src_clk_div
= DIV_ROUND_UP(GPLL_HZ
, aclk_emmc
);
803 assert(src_clk_div
- 1 < 32);
805 rk_clrsetreg(&cru
->clksel_con
[21],
806 ACLK_EMMC_PLL_SEL_MASK
| ACLK_EMMC_DIV_CON_MASK
,
807 ACLK_EMMC_PLL_SEL_GPLL
<< ACLK_EMMC_PLL_SEL_SHIFT
|
808 (src_clk_div
- 1) << ACLK_EMMC_DIV_CON_SHIFT
);
810 /* Select clk_emmc source from GPLL too */
811 src_clk_div
= DIV_ROUND_UP(GPLL_HZ
, set_rate
);
812 assert(src_clk_div
- 1 < 128);
814 rk_clrsetreg(&cru
->clksel_con
[22],
815 CLK_EMMC_PLL_MASK
| CLK_EMMC_DIV_CON_MASK
,
816 CLK_EMMC_PLL_SEL_GPLL
<< CLK_EMMC_PLL_SHIFT
|
817 (src_clk_div
- 1) << CLK_EMMC_DIV_CON_SHIFT
);
822 return rk3399_mmc_get_clk(cru
, clk_id
);
825 #define PMUSGRF_DDR_RGN_CON16 0xff330040
826 static ulong
rk3399_ddr_set_clk(struct rk3399_cru
*cru
,
829 struct pll_div dpll_cfg
;
831 /* IC ECO bug, need to set this register */
832 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16
);
834 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
837 dpll_cfg
= (struct pll_div
)
838 {.refdiv
= 1, .fbdiv
= 50, .postdiv1
= 6, .postdiv2
= 1};
841 dpll_cfg
= (struct pll_div
)
842 {.refdiv
= 2, .fbdiv
= 100, .postdiv1
= 4, .postdiv2
= 1};
845 dpll_cfg
= (struct pll_div
)
846 {.refdiv
= 2, .fbdiv
= 111, .postdiv1
= 2, .postdiv2
= 1};
849 dpll_cfg
= (struct pll_div
)
850 {.refdiv
= 1, .fbdiv
= 100, .postdiv1
= 3, .postdiv2
= 1};
853 dpll_cfg
= (struct pll_div
)
854 {.refdiv
= 1, .fbdiv
= 116, .postdiv1
= 3, .postdiv2
= 1};
857 error("Unsupported SDRAM frequency!,%ld\n", set_rate
);
859 rkclk_set_pll(&cru
->dpll_con
[0], &dpll_cfg
);
863 static ulong
rk3399_clk_get_rate(struct clk
*clk
)
865 struct rk3399_clk_priv
*priv
= dev_get_priv(clk
->dev
);
874 rate
= rk3399_mmc_get_clk(priv
->cru
, clk
->id
);
882 rate
= rk3399_i2c_get_clk(priv
->cru
, clk
->id
);
884 case SCLK_SPI0
...SCLK_SPI5
:
885 rate
= rk3399_spi_get_clk(priv
->cru
, clk
->id
);
896 case PCLK_EFUSE1024NS
:
905 static ulong
rk3399_clk_set_rate(struct clk
*clk
, ulong rate
)
907 struct rk3399_clk_priv
*priv
= dev_get_priv(clk
->dev
);
916 ret
= rk3399_mmc_set_clk(priv
->cru
, clk
->id
, rate
);
919 /* nothing to do, as this is an external clock */
928 ret
= rk3399_i2c_set_clk(priv
->cru
, clk
->id
, rate
);
930 case SCLK_SPI0
...SCLK_SPI5
:
931 ret
= rk3399_spi_set_clk(priv
->cru
, clk
->id
, rate
);
935 /* the PCLK gates for video are enabled by default */
939 ret
= rk3399_vop_set_clk(priv
->cru
, clk
->id
, rate
);
942 ret
= rk3399_ddr_set_clk(priv
->cru
, rate
);
944 case PCLK_EFUSE1024NS
:
953 static int rk3399_clk_enable(struct clk
*clk
)
963 debug("%s: unsupported clk %ld\n", __func__
, clk
->id
);
967 static struct clk_ops rk3399_clk_ops
= {
968 .get_rate
= rk3399_clk_get_rate
,
969 .set_rate
= rk3399_clk_set_rate
,
970 .enable
= rk3399_clk_enable
,
973 static int rk3399_clk_probe(struct udevice
*dev
)
975 #ifdef CONFIG_SPL_BUILD
976 struct rk3399_clk_priv
*priv
= dev_get_priv(dev
);
978 #if CONFIG_IS_ENABLED(OF_PLATDATA)
979 struct rk3399_clk_plat
*plat
= dev_get_platdata(dev
);
981 priv
->cru
= map_sysmem(plat
->dtd
.reg
[0], plat
->dtd
.reg
[1]);
983 rkclk_init(priv
->cru
);
988 static int rk3399_clk_ofdata_to_platdata(struct udevice
*dev
)
990 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
991 struct rk3399_clk_priv
*priv
= dev_get_priv(dev
);
993 priv
->cru
= dev_read_addr_ptr(dev
);
998 static int rk3399_clk_bind(struct udevice
*dev
)
1002 /* The reset driver does not have a device node, so bind it here */
1003 ret
= device_bind_driver(gd
->dm_root
, "rk3399_sysreset", "reset", &dev
);
1005 printf("Warning: No RK3399 reset driver: ret=%d\n", ret
);
1010 static const struct udevice_id rk3399_clk_ids
[] = {
1011 { .compatible
= "rockchip,rk3399-cru" },
1015 U_BOOT_DRIVER(clk_rk3399
) = {
1016 .name
= "rockchip_rk3399_cru",
1018 .of_match
= rk3399_clk_ids
,
1019 .priv_auto_alloc_size
= sizeof(struct rk3399_clk_priv
),
1020 .ofdata_to_platdata
= rk3399_clk_ofdata_to_platdata
,
1021 .ops
= &rk3399_clk_ops
,
1022 .bind
= rk3399_clk_bind
,
1023 .probe
= rk3399_clk_probe
,
1024 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1025 .platdata_auto_alloc_size
= sizeof(struct rk3399_clk_plat
),
1029 static ulong
rk3399_i2c_get_pmuclk(struct rk3399_pmucru
*pmucru
, ulong clk_id
)
1035 con
= readl(&pmucru
->pmucru_clksel
[2]);
1036 div
= I2C_CLK_DIV_VALUE(con
, 0);
1039 con
= readl(&pmucru
->pmucru_clksel
[3]);
1040 div
= I2C_CLK_DIV_VALUE(con
, 4);
1043 con
= readl(&pmucru
->pmucru_clksel
[2]);
1044 div
= I2C_CLK_DIV_VALUE(con
, 8);
1047 printf("do not support this i2c bus\n");
1051 return DIV_TO_RATE(PPLL_HZ
, div
);
1054 static ulong
rk3399_i2c_set_pmuclk(struct rk3399_pmucru
*pmucru
, ulong clk_id
,
1059 src_clk_div
= PPLL_HZ
/ hz
;
1060 assert(src_clk_div
- 1 < 127);
1064 rk_clrsetreg(&pmucru
->pmucru_clksel
[2], I2C_PMUCLK_REG_MASK(0),
1065 I2C_PMUCLK_REG_VALUE(0, src_clk_div
));
1068 rk_clrsetreg(&pmucru
->pmucru_clksel
[3], I2C_PMUCLK_REG_MASK(4),
1069 I2C_PMUCLK_REG_VALUE(4, src_clk_div
));
1072 rk_clrsetreg(&pmucru
->pmucru_clksel
[2], I2C_PMUCLK_REG_MASK(8),
1073 I2C_PMUCLK_REG_VALUE(8, src_clk_div
));
1076 printf("do not support this i2c bus\n");
1080 return DIV_TO_RATE(PPLL_HZ
, src_clk_div
);
1083 static ulong
rk3399_pwm_get_clk(struct rk3399_pmucru
*pmucru
)
1087 /* PWM closk rate is same as pclk_pmu */
1088 con
= readl(&pmucru
->pmucru_clksel
[0]);
1089 div
= con
& PMU_PCLK_DIV_CON_MASK
;
1091 return DIV_TO_RATE(PPLL_HZ
, div
);
1094 static ulong
rk3399_pmuclk_get_rate(struct clk
*clk
)
1096 struct rk3399_pmuclk_priv
*priv
= dev_get_priv(clk
->dev
);
1100 case PCLK_RKPWM_PMU
:
1101 rate
= rk3399_pwm_get_clk(priv
->pmucru
);
1106 rate
= rk3399_i2c_get_pmuclk(priv
->pmucru
, clk
->id
);
1115 static ulong
rk3399_pmuclk_set_rate(struct clk
*clk
, ulong rate
)
1117 struct rk3399_pmuclk_priv
*priv
= dev_get_priv(clk
->dev
);
1124 ret
= rk3399_i2c_set_pmuclk(priv
->pmucru
, clk
->id
, rate
);
1133 static struct clk_ops rk3399_pmuclk_ops
= {
1134 .get_rate
= rk3399_pmuclk_get_rate
,
1135 .set_rate
= rk3399_pmuclk_set_rate
,
1138 #ifndef CONFIG_SPL_BUILD
1139 static void pmuclk_init(struct rk3399_pmucru
*pmucru
)
1143 /* configure pmu pll(ppll) */
1144 rkclk_set_pll(&pmucru
->ppll_con
[0], &ppll_init_cfg
);
1146 /* configure pmu pclk */
1147 pclk_div
= PPLL_HZ
/ PMU_PCLK_HZ
- 1;
1148 rk_clrsetreg(&pmucru
->pmucru_clksel
[0],
1149 PMU_PCLK_DIV_CON_MASK
,
1150 pclk_div
<< PMU_PCLK_DIV_CON_SHIFT
);
1154 static int rk3399_pmuclk_probe(struct udevice
*dev
)
1156 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
1157 struct rk3399_pmuclk_priv
*priv
= dev_get_priv(dev
);
1160 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1161 struct rk3399_pmuclk_plat
*plat
= dev_get_platdata(dev
);
1163 priv
->pmucru
= map_sysmem(plat
->dtd
.reg
[0], plat
->dtd
.reg
[1]);
1166 #ifndef CONFIG_SPL_BUILD
1167 pmuclk_init(priv
->pmucru
);
1172 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice
*dev
)
1174 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1175 struct rk3399_pmuclk_priv
*priv
= dev_get_priv(dev
);
1177 priv
->pmucru
= dev_read_addr_ptr(dev
);
1182 static const struct udevice_id rk3399_pmuclk_ids
[] = {
1183 { .compatible
= "rockchip,rk3399-pmucru" },
1187 U_BOOT_DRIVER(rockchip_rk3399_pmuclk
) = {
1188 .name
= "rockchip_rk3399_pmucru",
1190 .of_match
= rk3399_pmuclk_ids
,
1191 .priv_auto_alloc_size
= sizeof(struct rk3399_pmuclk_priv
),
1192 .ofdata_to_platdata
= rk3399_pmuclk_ofdata_to_platdata
,
1193 .ops
= &rk3399_pmuclk_ops
,
1194 .probe
= rk3399_pmuclk_probe
,
1195 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1196 .platdata_auto_alloc_size
= sizeof(struct rk3399_pmuclk_plat
),