]> git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/ddr/fsl/ctrl_regs.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Various, unrelated tree-wide typo fixes.
[people/ms/u-boot.git] / drivers / ddr / fsl / ctrl_regs.c
1 /*
2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /*
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
11 */
12
13 #include <common.h>
14 #include <fsl_ddr_sdram.h>
15
16 #include <fsl_ddr.h>
17 #include <fsl_immap.h>
18 #include <asm/io.h>
19
20 /*
21 * Determine Rtt value.
22 *
23 * This should likely be either board or controller specific.
24 *
25 * Rtt(nominal) - DDR2:
26 * 0 = Rtt disabled
27 * 1 = 75 ohm
28 * 2 = 150 ohm
29 * 3 = 50 ohm
30 * Rtt(nominal) - DDR3:
31 * 0 = Rtt disabled
32 * 1 = 60 ohm
33 * 2 = 120 ohm
34 * 3 = 40 ohm
35 * 4 = 20 ohm
36 * 5 = 30 ohm
37 *
38 * FIXME: Apparently 8641 needs a value of 2
39 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
40 *
41 * FIXME: There was some effort down this line earlier:
42 *
43 * unsigned int i;
44 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
45 * if (popts->dimmslot[i].num_valid_cs
46 * && (popts->cs_local_opts[2*i].odt_rd_cfg
47 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
48 * rtt = 2;
49 * break;
50 * }
51 * }
52 */
53 static inline int fsl_ddr_get_rtt(void)
54 {
55 int rtt;
56
57 #if defined(CONFIG_SYS_FSL_DDR1)
58 rtt = 0;
59 #elif defined(CONFIG_SYS_FSL_DDR2)
60 rtt = 3;
61 #else
62 rtt = 0;
63 #endif
64
65 return rtt;
66 }
67
68 #ifdef CONFIG_SYS_FSL_DDR4
69 /*
70 * compute CAS write latency according to DDR4 spec
71 * CWL = 9 for <= 1600MT/s
72 * 10 for <= 1866MT/s
73 * 11 for <= 2133MT/s
74 * 12 for <= 2400MT/s
75 * 14 for <= 2667MT/s
76 * 16 for <= 2933MT/s
77 * 18 for higher
78 */
79 static inline unsigned int compute_cas_write_latency(
80 const unsigned int ctrl_num)
81 {
82 unsigned int cwl;
83 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
84 if (mclk_ps >= 1250)
85 cwl = 9;
86 else if (mclk_ps >= 1070)
87 cwl = 10;
88 else if (mclk_ps >= 935)
89 cwl = 11;
90 else if (mclk_ps >= 833)
91 cwl = 12;
92 else if (mclk_ps >= 750)
93 cwl = 14;
94 else if (mclk_ps >= 681)
95 cwl = 16;
96 else
97 cwl = 18;
98
99 return cwl;
100 }
101 #else
102 /*
103 * compute the CAS write latency according to DDR3 spec
104 * CWL = 5 if tCK >= 2.5ns
105 * 6 if 2.5ns > tCK >= 1.875ns
106 * 7 if 1.875ns > tCK >= 1.5ns
107 * 8 if 1.5ns > tCK >= 1.25ns
108 * 9 if 1.25ns > tCK >= 1.07ns
109 * 10 if 1.07ns > tCK >= 0.935ns
110 * 11 if 0.935ns > tCK >= 0.833ns
111 * 12 if 0.833ns > tCK >= 0.75ns
112 */
113 static inline unsigned int compute_cas_write_latency(
114 const unsigned int ctrl_num)
115 {
116 unsigned int cwl;
117 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
118
119 if (mclk_ps >= 2500)
120 cwl = 5;
121 else if (mclk_ps >= 1875)
122 cwl = 6;
123 else if (mclk_ps >= 1500)
124 cwl = 7;
125 else if (mclk_ps >= 1250)
126 cwl = 8;
127 else if (mclk_ps >= 1070)
128 cwl = 9;
129 else if (mclk_ps >= 935)
130 cwl = 10;
131 else if (mclk_ps >= 833)
132 cwl = 11;
133 else if (mclk_ps >= 750)
134 cwl = 12;
135 else {
136 cwl = 12;
137 printf("Warning: CWL is out of range\n");
138 }
139 return cwl;
140 }
141 #endif
142
143 /* Chip Select Configuration (CSn_CONFIG) */
144 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
145 const memctl_options_t *popts,
146 const dimm_params_t *dimm_params)
147 {
148 unsigned int cs_n_en = 0; /* Chip Select enable */
149 unsigned int intlv_en = 0; /* Memory controller interleave enable */
150 unsigned int intlv_ctl = 0; /* Interleaving control */
151 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
152 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
153 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
154 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
155 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
156 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
157 int go_config = 0;
158 #ifdef CONFIG_SYS_FSL_DDR4
159 unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
160 #else
161 unsigned int n_banks_per_sdram_device;
162 #endif
163
164 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
165 switch (i) {
166 case 0:
167 if (dimm_params[dimm_number].n_ranks > 0) {
168 go_config = 1;
169 /* These fields only available in CS0_CONFIG */
170 if (!popts->memctl_interleaving)
171 break;
172 switch (popts->memctl_interleaving_mode) {
173 case FSL_DDR_256B_INTERLEAVING:
174 case FSL_DDR_CACHE_LINE_INTERLEAVING:
175 case FSL_DDR_PAGE_INTERLEAVING:
176 case FSL_DDR_BANK_INTERLEAVING:
177 case FSL_DDR_SUPERBANK_INTERLEAVING:
178 intlv_en = popts->memctl_interleaving;
179 intlv_ctl = popts->memctl_interleaving_mode;
180 break;
181 default:
182 break;
183 }
184 }
185 break;
186 case 1:
187 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
188 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
189 go_config = 1;
190 break;
191 case 2:
192 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
193 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
194 go_config = 1;
195 break;
196 case 3:
197 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
198 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
199 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
200 go_config = 1;
201 break;
202 default:
203 break;
204 }
205 if (go_config) {
206 cs_n_en = 1;
207 ap_n_en = popts->cs_local_opts[i].auto_precharge;
208 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
209 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
210 #ifdef CONFIG_SYS_FSL_DDR4
211 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
212 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
213 #else
214 n_banks_per_sdram_device
215 = dimm_params[dimm_number].n_banks_per_sdram_device;
216 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
217 #endif
218 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
219 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
220 }
221 ddr->cs[i].config = (0
222 | ((cs_n_en & 0x1) << 31)
223 | ((intlv_en & 0x3) << 29)
224 | ((intlv_ctl & 0xf) << 24)
225 | ((ap_n_en & 0x1) << 23)
226
227 /* XXX: some implementation only have 1 bit starting at left */
228 | ((odt_rd_cfg & 0x7) << 20)
229
230 /* XXX: Some implementation only have 1 bit starting at left */
231 | ((odt_wr_cfg & 0x7) << 16)
232
233 | ((ba_bits_cs_n & 0x3) << 14)
234 | ((row_bits_cs_n & 0x7) << 8)
235 #ifdef CONFIG_SYS_FSL_DDR4
236 | ((bg_bits_cs_n & 0x3) << 4)
237 #endif
238 | ((col_bits_cs_n & 0x7) << 0)
239 );
240 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
241 }
242
243 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
244 /* FIXME: 8572 */
245 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
246 {
247 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
248
249 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
250 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
251 }
252
253 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
254
255 #if !defined(CONFIG_SYS_FSL_DDR1)
256 /*
257 * Check DIMM configuration, return 2 if quad-rank or two dual-rank
258 * Return 1 if other two slots configuration. Return 0 if single slot.
259 */
260 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
261 {
262 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
263 if (dimm_params[0].n_ranks == 4)
264 return 2;
265 #endif
266
267 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
268 if ((dimm_params[0].n_ranks == 2) &&
269 (dimm_params[1].n_ranks == 2))
270 return 2;
271
272 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
273 if (dimm_params[0].n_ranks == 4)
274 return 2;
275 #endif
276
277 if ((dimm_params[0].n_ranks != 0) &&
278 (dimm_params[2].n_ranks != 0))
279 return 1;
280 #endif
281 return 0;
282 }
283
284 /*
285 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
286 *
287 * Avoid writing for DDR I. The new PQ38 DDR controller
288 * dreams up non-zero default values to be backwards compatible.
289 */
290 static void set_timing_cfg_0(const unsigned int ctrl_num,
291 fsl_ddr_cfg_regs_t *ddr,
292 const memctl_options_t *popts,
293 const dimm_params_t *dimm_params)
294 {
295 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
296 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
297 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
298 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
299 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
300
301 /* Active powerdown exit timing (tXARD and tXARDS). */
302 unsigned char act_pd_exit_mclk;
303 /* Precharge powerdown exit timing (tXP). */
304 unsigned char pre_pd_exit_mclk;
305 /* ODT powerdown exit timing (tAXPD). */
306 unsigned char taxpd_mclk = 0;
307 /* Mode register set cycle time (tMRD). */
308 unsigned char tmrd_mclk;
309 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
310 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
311 #endif
312
313 #ifdef CONFIG_SYS_FSL_DDR4
314 /* tXP=max(4nCK, 6ns) */
315 int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
316 unsigned int data_rate = get_ddr_freq(ctrl_num);
317
318 /* for faster clock, need more time for data setup */
319 trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
320
321 /*
322 * for single quad-rank DIMM and two-slot DIMMs
323 * to avoid ODT overlap
324 */
325 switch (avoid_odt_overlap(dimm_params)) {
326 case 2:
327 twrt_mclk = 2;
328 twwt_mclk = 2;
329 trrt_mclk = 2;
330 break;
331 default:
332 twrt_mclk = 1;
333 twwt_mclk = 1;
334 trrt_mclk = 0;
335 break;
336 }
337
338 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
339 pre_pd_exit_mclk = act_pd_exit_mclk;
340 /*
341 * MRS_CYC = max(tMRD, tMOD)
342 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
343 */
344 tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
345 #elif defined(CONFIG_SYS_FSL_DDR3)
346 unsigned int data_rate = get_ddr_freq(ctrl_num);
347 int txp;
348 unsigned int ip_rev;
349 int odt_overlap;
350 /*
351 * (tXARD and tXARDS). Empirical?
352 * The DDR3 spec has not tXARD,
353 * we use the tXP instead of it.
354 * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
355 * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
356 * spec has not the tAXPD, we use
357 * tAXPD=1, need design to confirm.
358 */
359 txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
360
361 ip_rev = fsl_ddr_get_version(ctrl_num);
362 if (ip_rev >= 0x40700) {
363 /*
364 * MRS_CYC = max(tMRD, tMOD)
365 * tMRD = 4nCK (8nCK for RDIMM)
366 * tMOD = max(12nCK, 15ns)
367 */
368 tmrd_mclk = max((unsigned int)12,
369 picos_to_mclk(ctrl_num, 15000));
370 } else {
371 /*
372 * MRS_CYC = tMRD
373 * tMRD = 4nCK (8nCK for RDIMM)
374 */
375 if (popts->registered_dimm_en)
376 tmrd_mclk = 8;
377 else
378 tmrd_mclk = 4;
379 }
380
381 /* set the turnaround time */
382
383 /*
384 * for single quad-rank DIMM and two-slot DIMMs
385 * to avoid ODT overlap
386 */
387 odt_overlap = avoid_odt_overlap(dimm_params);
388 switch (odt_overlap) {
389 case 2:
390 twwt_mclk = 2;
391 trrt_mclk = 1;
392 break;
393 case 1:
394 twwt_mclk = 1;
395 trrt_mclk = 0;
396 break;
397 default:
398 break;
399 }
400
401 /* for faster clock, need more time for data setup */
402 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
403
404 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
405 twrt_mclk = 1;
406
407 if (popts->dynamic_power == 0) { /* powerdown is not used */
408 act_pd_exit_mclk = 1;
409 pre_pd_exit_mclk = 1;
410 taxpd_mclk = 1;
411 } else {
412 /* act_pd_exit_mclk = tXARD, see above */
413 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
414 /* Mode register MR0[A12] is '1' - fast exit */
415 pre_pd_exit_mclk = act_pd_exit_mclk;
416 taxpd_mclk = 1;
417 }
418 #else /* CONFIG_SYS_FSL_DDR2 */
419 /*
420 * (tXARD and tXARDS). Empirical?
421 * tXARD = 2 for DDR2
422 * tXP=2
423 * tAXPD=8
424 */
425 act_pd_exit_mclk = 2;
426 pre_pd_exit_mclk = 2;
427 taxpd_mclk = 8;
428 tmrd_mclk = 2;
429 #endif
430
431 if (popts->trwt_override)
432 trwt_mclk = popts->trwt;
433
434 ddr->timing_cfg_0 = (0
435 | ((trwt_mclk & 0x3) << 30) /* RWT */
436 | ((twrt_mclk & 0x3) << 28) /* WRT */
437 | ((trrt_mclk & 0x3) << 26) /* RRT */
438 | ((twwt_mclk & 0x3) << 24) /* WWT */
439 | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
440 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
441 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
442 | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
443 );
444 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
445 }
446 #endif /* !defined(CONFIG_SYS_FSL_DDR1) */
447
448 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
449 static void set_timing_cfg_3(const unsigned int ctrl_num,
450 fsl_ddr_cfg_regs_t *ddr,
451 const memctl_options_t *popts,
452 const common_timing_params_t *common_dimm,
453 unsigned int cas_latency,
454 unsigned int additive_latency)
455 {
456 /* Extended precharge to activate interval (tRP) */
457 unsigned int ext_pretoact = 0;
458 /* Extended Activate to precharge interval (tRAS) */
459 unsigned int ext_acttopre = 0;
460 /* Extended activate to read/write interval (tRCD) */
461 unsigned int ext_acttorw = 0;
462 /* Extended refresh recovery time (tRFC) */
463 unsigned int ext_refrec;
464 /* Extended MCAS latency from READ cmd */
465 unsigned int ext_caslat = 0;
466 /* Extended additive latency */
467 unsigned int ext_add_lat = 0;
468 /* Extended last data to precharge interval (tWR) */
469 unsigned int ext_wrrec = 0;
470 /* Control Adjust */
471 unsigned int cntl_adj = 0;
472
473 ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
474 ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
475 ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
476 ext_caslat = (2 * cas_latency - 1) >> 4;
477 ext_add_lat = additive_latency >> 4;
478 #ifdef CONFIG_SYS_FSL_DDR4
479 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
480 #else
481 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
482 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
483 #endif
484 ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
485 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
486
487 ddr->timing_cfg_3 = (0
488 | ((ext_pretoact & 0x1) << 28)
489 | ((ext_acttopre & 0x3) << 24)
490 | ((ext_acttorw & 0x1) << 22)
491 | ((ext_refrec & 0x1F) << 16)
492 | ((ext_caslat & 0x3) << 12)
493 | ((ext_add_lat & 0x1) << 10)
494 | ((ext_wrrec & 0x1) << 8)
495 | ((cntl_adj & 0x7) << 0)
496 );
497 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
498 }
499
500 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
501 static void set_timing_cfg_1(const unsigned int ctrl_num,
502 fsl_ddr_cfg_regs_t *ddr,
503 const memctl_options_t *popts,
504 const common_timing_params_t *common_dimm,
505 unsigned int cas_latency)
506 {
507 /* Precharge-to-activate interval (tRP) */
508 unsigned char pretoact_mclk;
509 /* Activate to precharge interval (tRAS) */
510 unsigned char acttopre_mclk;
511 /* Activate to read/write interval (tRCD) */
512 unsigned char acttorw_mclk;
513 /* CASLAT */
514 unsigned char caslat_ctrl;
515 /* Refresh recovery time (tRFC) ; trfc_low */
516 unsigned char refrec_ctrl;
517 /* Last data to precharge minimum interval (tWR) */
518 unsigned char wrrec_mclk;
519 /* Activate-to-activate interval (tRRD) */
520 unsigned char acttoact_mclk;
521 /* Last write data pair to read command issue interval (tWTR) */
522 unsigned char wrtord_mclk;
523 #ifdef CONFIG_SYS_FSL_DDR4
524 /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
525 static const u8 wrrec_table[] = {
526 10, 10, 10, 10, 10,
527 10, 10, 10, 10, 10,
528 12, 12, 14, 14, 16,
529 16, 18, 18, 20, 20,
530 24, 24, 24, 24};
531 #else
532 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
533 static const u8 wrrec_table[] = {
534 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
535 #endif
536
537 pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
538 acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
539 acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
540
541 /*
542 * Translate CAS Latency to a DDR controller field value:
543 *
544 * CAS Lat DDR I DDR II Ctrl
545 * Clocks SPD Bit SPD Bit Value
546 * ------- ------- ------- -----
547 * 1.0 0 0001
548 * 1.5 1 0010
549 * 2.0 2 2 0011
550 * 2.5 3 0100
551 * 3.0 4 3 0101
552 * 3.5 5 0110
553 * 4.0 4 0111
554 * 4.5 1000
555 * 5.0 5 1001
556 */
557 #if defined(CONFIG_SYS_FSL_DDR1)
558 caslat_ctrl = (cas_latency + 1) & 0x07;
559 #elif defined(CONFIG_SYS_FSL_DDR2)
560 caslat_ctrl = 2 * cas_latency - 1;
561 #else
562 /*
563 * if the CAS latency more than 8 cycle,
564 * we need set extend bit for it at
565 * TIMING_CFG_3[EXT_CASLAT]
566 */
567 if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
568 caslat_ctrl = 2 * cas_latency - 1;
569 else
570 caslat_ctrl = (cas_latency - 1) << 1;
571 #endif
572
573 #ifdef CONFIG_SYS_FSL_DDR4
574 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
575 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
576 acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
577 wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
578 if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
579 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
580 else
581 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
582 #else
583 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
584 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
585 acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
586 wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
587 if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
588 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
589 else
590 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
591 #endif
592 if (popts->otf_burst_chop_en)
593 wrrec_mclk += 2;
594
595 /*
596 * JEDEC has min requirement for tRRD
597 */
598 #if defined(CONFIG_SYS_FSL_DDR3)
599 if (acttoact_mclk < 4)
600 acttoact_mclk = 4;
601 #endif
602 /*
603 * JEDEC has some min requirements for tWTR
604 */
605 #if defined(CONFIG_SYS_FSL_DDR2)
606 if (wrtord_mclk < 2)
607 wrtord_mclk = 2;
608 #elif defined(CONFIG_SYS_FSL_DDR3)
609 if (wrtord_mclk < 4)
610 wrtord_mclk = 4;
611 #endif
612 if (popts->otf_burst_chop_en)
613 wrtord_mclk += 2;
614
615 ddr->timing_cfg_1 = (0
616 | ((pretoact_mclk & 0x0F) << 28)
617 | ((acttopre_mclk & 0x0F) << 24)
618 | ((acttorw_mclk & 0xF) << 20)
619 | ((caslat_ctrl & 0xF) << 16)
620 | ((refrec_ctrl & 0xF) << 12)
621 | ((wrrec_mclk & 0x0F) << 8)
622 | ((acttoact_mclk & 0x0F) << 4)
623 | ((wrtord_mclk & 0x0F) << 0)
624 );
625 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
626 }
627
628 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
629 static void set_timing_cfg_2(const unsigned int ctrl_num,
630 fsl_ddr_cfg_regs_t *ddr,
631 const memctl_options_t *popts,
632 const common_timing_params_t *common_dimm,
633 unsigned int cas_latency,
634 unsigned int additive_latency)
635 {
636 /* Additive latency */
637 unsigned char add_lat_mclk;
638 /* CAS-to-preamble override */
639 unsigned short cpo;
640 /* Write latency */
641 unsigned char wr_lat;
642 /* Read to precharge (tRTP) */
643 unsigned char rd_to_pre;
644 /* Write command to write data strobe timing adjustment */
645 unsigned char wr_data_delay;
646 /* Minimum CKE pulse width (tCKE) */
647 unsigned char cke_pls;
648 /* Window for four activates (tFAW) */
649 unsigned short four_act;
650 #ifdef CONFIG_SYS_FSL_DDR3
651 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
652 #endif
653
654 /* FIXME add check that this must be less than acttorw_mclk */
655 add_lat_mclk = additive_latency;
656 cpo = popts->cpo_override;
657
658 #if defined(CONFIG_SYS_FSL_DDR1)
659 /*
660 * This is a lie. It should really be 1, but if it is
661 * set to 1, bits overlap into the old controller's
662 * otherwise unused ACSM field. If we leave it 0, then
663 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
664 */
665 wr_lat = 0;
666 #elif defined(CONFIG_SYS_FSL_DDR2)
667 wr_lat = cas_latency - 1;
668 #else
669 wr_lat = compute_cas_write_latency(ctrl_num);
670 #endif
671
672 #ifdef CONFIG_SYS_FSL_DDR4
673 rd_to_pre = picos_to_mclk(ctrl_num, 7500);
674 #else
675 rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
676 #endif
677 /*
678 * JEDEC has some min requirements for tRTP
679 */
680 #if defined(CONFIG_SYS_FSL_DDR2)
681 if (rd_to_pre < 2)
682 rd_to_pre = 2;
683 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
684 if (rd_to_pre < 4)
685 rd_to_pre = 4;
686 #endif
687 if (popts->otf_burst_chop_en)
688 rd_to_pre += 2; /* according to UM */
689
690 wr_data_delay = popts->write_data_delay;
691 #ifdef CONFIG_SYS_FSL_DDR4
692 cpo = 0;
693 cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
694 #elif defined(CONFIG_SYS_FSL_DDR3)
695 /*
696 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
697 * max(3nCK, 5.625ns) for DDR3-1066, 1333
698 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133
699 */
700 cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
701 (mclk_ps > 1245 ? 5625 : 5000)));
702 #else
703 cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
704 #endif
705 four_act = picos_to_mclk(ctrl_num,
706 popts->tfaw_window_four_activates_ps);
707
708 ddr->timing_cfg_2 = (0
709 | ((add_lat_mclk & 0xf) << 28)
710 | ((cpo & 0x1f) << 23)
711 | ((wr_lat & 0xf) << 19)
712 | ((wr_lat & 0x10) << 18)
713 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
714 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
715 | ((cke_pls & 0x7) << 6)
716 | ((four_act & 0x3f) << 0)
717 );
718 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
719 }
720
721 /* DDR SDRAM Register Control Word */
722 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
723 const memctl_options_t *popts,
724 const common_timing_params_t *common_dimm)
725 {
726 if (common_dimm->all_dimms_registered &&
727 !common_dimm->all_dimms_unbuffered) {
728 if (popts->rcw_override) {
729 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
730 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
731 } else {
732 ddr->ddr_sdram_rcw_1 =
733 common_dimm->rcw[0] << 28 | \
734 common_dimm->rcw[1] << 24 | \
735 common_dimm->rcw[2] << 20 | \
736 common_dimm->rcw[3] << 16 | \
737 common_dimm->rcw[4] << 12 | \
738 common_dimm->rcw[5] << 8 | \
739 common_dimm->rcw[6] << 4 | \
740 common_dimm->rcw[7];
741 ddr->ddr_sdram_rcw_2 =
742 common_dimm->rcw[8] << 28 | \
743 common_dimm->rcw[9] << 24 | \
744 common_dimm->rcw[10] << 20 | \
745 common_dimm->rcw[11] << 16 | \
746 common_dimm->rcw[12] << 12 | \
747 common_dimm->rcw[13] << 8 | \
748 common_dimm->rcw[14] << 4 | \
749 common_dimm->rcw[15];
750 }
751 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
752 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
753 }
754 }
755
756 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
757 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
758 const memctl_options_t *popts,
759 const common_timing_params_t *common_dimm)
760 {
761 unsigned int mem_en; /* DDR SDRAM interface logic enable */
762 unsigned int sren; /* Self refresh enable (during sleep) */
763 unsigned int ecc_en; /* ECC enable. */
764 unsigned int rd_en; /* Registered DIMM enable */
765 unsigned int sdram_type; /* Type of SDRAM */
766 unsigned int dyn_pwr; /* Dynamic power management mode */
767 unsigned int dbw; /* DRAM dta bus width */
768 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
769 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
770 unsigned int threet_en; /* Enable 3T timing */
771 unsigned int twot_en; /* Enable 2T timing */
772 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
773 unsigned int x32_en = 0; /* x32 enable */
774 unsigned int pchb8 = 0; /* precharge bit 8 enable */
775 unsigned int hse; /* Global half strength override */
776 unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */
777 unsigned int mem_halt = 0; /* memory controller halt */
778 unsigned int bi = 0; /* Bypass initialization */
779
780 mem_en = 1;
781 sren = popts->self_refresh_in_sleep;
782 if (common_dimm->all_dimms_ecc_capable) {
783 /* Allow setting of ECC only if all DIMMs are ECC. */
784 ecc_en = popts->ecc_mode;
785 } else {
786 ecc_en = 0;
787 }
788
789 if (common_dimm->all_dimms_registered &&
790 !common_dimm->all_dimms_unbuffered) {
791 rd_en = 1;
792 twot_en = 0;
793 } else {
794 rd_en = 0;
795 twot_en = popts->twot_en;
796 }
797
798 sdram_type = CONFIG_FSL_SDRAM_TYPE;
799
800 dyn_pwr = popts->dynamic_power;
801 dbw = popts->data_bus_width;
802 /* 8-beat burst enable DDR-III case
803 * we must clear it when use the on-the-fly mode,
804 * must set it when use the 32-bits bus mode.
805 */
806 if ((sdram_type == SDRAM_TYPE_DDR3) ||
807 (sdram_type == SDRAM_TYPE_DDR4)) {
808 if (popts->burst_length == DDR_BL8)
809 eight_be = 1;
810 if (popts->burst_length == DDR_OTF)
811 eight_be = 0;
812 if (dbw == 0x1)
813 eight_be = 1;
814 }
815
816 threet_en = popts->threet_en;
817 ba_intlv_ctl = popts->ba_intlv_ctl;
818 hse = popts->half_strength_driver_enable;
819
820 /* set when ddr bus width < 64 */
821 acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
822
823 ddr->ddr_sdram_cfg = (0
824 | ((mem_en & 0x1) << 31)
825 | ((sren & 0x1) << 30)
826 | ((ecc_en & 0x1) << 29)
827 | ((rd_en & 0x1) << 28)
828 | ((sdram_type & 0x7) << 24)
829 | ((dyn_pwr & 0x1) << 21)
830 | ((dbw & 0x3) << 19)
831 | ((eight_be & 0x1) << 18)
832 | ((ncap & 0x1) << 17)
833 | ((threet_en & 0x1) << 16)
834 | ((twot_en & 0x1) << 15)
835 | ((ba_intlv_ctl & 0x7F) << 8)
836 | ((x32_en & 0x1) << 5)
837 | ((pchb8 & 0x1) << 4)
838 | ((hse & 0x1) << 3)
839 | ((acc_ecc_en & 0x1) << 2)
840 | ((mem_halt & 0x1) << 1)
841 | ((bi & 0x1) << 0)
842 );
843 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
844 }
845
846 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
847 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
848 fsl_ddr_cfg_regs_t *ddr,
849 const memctl_options_t *popts,
850 const unsigned int unq_mrs_en)
851 {
852 unsigned int frc_sr = 0; /* Force self refresh */
853 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
854 unsigned int odt_cfg = 0; /* ODT configuration */
855 unsigned int num_pr; /* Number of posted refreshes */
856 unsigned int slow = 0; /* DDR will be run less than 1250 */
857 unsigned int x4_en = 0; /* x4 DRAM enable */
858 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
859 unsigned int ap_en; /* Address Parity Enable */
860 unsigned int d_init; /* DRAM data initialization */
861 unsigned int rcw_en = 0; /* Register Control Word Enable */
862 unsigned int md_en = 0; /* Mirrored DIMM Enable */
863 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
864 int i;
865 #ifndef CONFIG_SYS_FSL_DDR4
866 unsigned int dll_rst_dis = 1; /* DLL reset disable */
867 unsigned int dqs_cfg; /* DQS configuration */
868
869 dqs_cfg = popts->dqs_config;
870 #endif
871 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
872 if (popts->cs_local_opts[i].odt_rd_cfg
873 || popts->cs_local_opts[i].odt_wr_cfg) {
874 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
875 break;
876 }
877 }
878 sr_ie = popts->self_refresh_interrupt_en;
879 num_pr = 1; /* Make this configurable */
880
881 /*
882 * 8572 manual says
883 * {TIMING_CFG_1[PRETOACT]
884 * + [DDR_SDRAM_CFG_2[NUM_PR]
885 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
886 * << DDR_SDRAM_INTERVAL[REFINT]
887 */
888 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
889 obc_cfg = popts->otf_burst_chop_en;
890 #else
891 obc_cfg = 0;
892 #endif
893
894 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
895 slow = get_ddr_freq(ctrl_num) < 1249000000;
896 #endif
897
898 if (popts->registered_dimm_en)
899 rcw_en = 1;
900
901 /* DDR4 can have address parity for UDIMM and discrete */
902 if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
903 (!popts->registered_dimm_en)) {
904 ap_en = 0;
905 } else {
906 ap_en = popts->ap_en;
907 }
908
909 x4_en = popts->x4_en ? 1 : 0;
910
911 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
912 /* Use the DDR controller to auto initialize memory. */
913 d_init = popts->ecc_init_using_memctl;
914 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
915 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
916 #else
917 /* Memory will be initialized via DMA, or not at all. */
918 d_init = 0;
919 #endif
920
921 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
922 md_en = popts->mirrored_dimm;
923 #endif
924 qd_en = popts->quad_rank_present ? 1 : 0;
925 ddr->ddr_sdram_cfg_2 = (0
926 | ((frc_sr & 0x1) << 31)
927 | ((sr_ie & 0x1) << 30)
928 #ifndef CONFIG_SYS_FSL_DDR4
929 | ((dll_rst_dis & 0x1) << 29)
930 | ((dqs_cfg & 0x3) << 26)
931 #endif
932 | ((odt_cfg & 0x3) << 21)
933 | ((num_pr & 0xf) << 12)
934 | ((slow & 1) << 11)
935 | (x4_en << 10)
936 | (qd_en << 9)
937 | (unq_mrs_en << 8)
938 | ((obc_cfg & 0x1) << 6)
939 | ((ap_en & 0x1) << 5)
940 | ((d_init & 0x1) << 4)
941 | ((rcw_en & 0x1) << 2)
942 | ((md_en & 0x1) << 0)
943 );
944 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
945 }
946
947 #ifdef CONFIG_SYS_FSL_DDR4
948 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
949 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
950 fsl_ddr_cfg_regs_t *ddr,
951 const memctl_options_t *popts,
952 const common_timing_params_t *common_dimm,
953 const unsigned int unq_mrs_en)
954 {
955 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
956 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
957 int i;
958 unsigned int wr_crc = 0; /* Disable */
959 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
960 unsigned int srt = 0; /* self-refresh temerature, normal range */
961 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
962 unsigned int mpr = 0; /* serial */
963 unsigned int wc_lat;
964 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
965
966 if (popts->rtt_override)
967 rtt_wr = popts->rtt_wr_override_value;
968 else
969 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
970
971 if (common_dimm->extended_op_srt)
972 srt = common_dimm->extended_op_srt;
973
974 esdmode2 = (0
975 | ((wr_crc & 0x1) << 12)
976 | ((rtt_wr & 0x3) << 9)
977 | ((srt & 0x3) << 6)
978 | ((cwl & 0x7) << 3));
979
980 if (mclk_ps >= 1250)
981 wc_lat = 0;
982 else if (mclk_ps >= 833)
983 wc_lat = 1;
984 else
985 wc_lat = 2;
986
987 esdmode3 = (0
988 | ((mpr & 0x3) << 11)
989 | ((wc_lat & 0x3) << 9));
990
991 ddr->ddr_sdram_mode_2 = (0
992 | ((esdmode2 & 0xFFFF) << 16)
993 | ((esdmode3 & 0xFFFF) << 0)
994 );
995 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
996
997 if (unq_mrs_en) { /* unique mode registers are supported */
998 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
999 if (popts->rtt_override)
1000 rtt_wr = popts->rtt_wr_override_value;
1001 else
1002 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1003
1004 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1005 esdmode2 |= (rtt_wr & 0x3) << 9;
1006 switch (i) {
1007 case 1:
1008 ddr->ddr_sdram_mode_4 = (0
1009 | ((esdmode2 & 0xFFFF) << 16)
1010 | ((esdmode3 & 0xFFFF) << 0)
1011 );
1012 break;
1013 case 2:
1014 ddr->ddr_sdram_mode_6 = (0
1015 | ((esdmode2 & 0xFFFF) << 16)
1016 | ((esdmode3 & 0xFFFF) << 0)
1017 );
1018 break;
1019 case 3:
1020 ddr->ddr_sdram_mode_8 = (0
1021 | ((esdmode2 & 0xFFFF) << 16)
1022 | ((esdmode3 & 0xFFFF) << 0)
1023 );
1024 break;
1025 }
1026 }
1027 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1028 ddr->ddr_sdram_mode_4);
1029 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1030 ddr->ddr_sdram_mode_6);
1031 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1032 ddr->ddr_sdram_mode_8);
1033 }
1034 }
1035 #elif defined(CONFIG_SYS_FSL_DDR3)
1036 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1037 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1038 fsl_ddr_cfg_regs_t *ddr,
1039 const memctl_options_t *popts,
1040 const common_timing_params_t *common_dimm,
1041 const unsigned int unq_mrs_en)
1042 {
1043 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1044 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1045 int i;
1046 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
1047 unsigned int srt = 0; /* self-refresh temerature, normal range */
1048 unsigned int asr = 0; /* auto self-refresh disable */
1049 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
1050 unsigned int pasr = 0; /* partial array self refresh disable */
1051
1052 if (popts->rtt_override)
1053 rtt_wr = popts->rtt_wr_override_value;
1054 else
1055 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1056
1057 if (common_dimm->extended_op_srt)
1058 srt = common_dimm->extended_op_srt;
1059
1060 esdmode2 = (0
1061 | ((rtt_wr & 0x3) << 9)
1062 | ((srt & 0x1) << 7)
1063 | ((asr & 0x1) << 6)
1064 | ((cwl & 0x7) << 3)
1065 | ((pasr & 0x7) << 0));
1066 ddr->ddr_sdram_mode_2 = (0
1067 | ((esdmode2 & 0xFFFF) << 16)
1068 | ((esdmode3 & 0xFFFF) << 0)
1069 );
1070 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1071
1072 if (unq_mrs_en) { /* unique mode registers are supported */
1073 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1074 if (popts->rtt_override)
1075 rtt_wr = popts->rtt_wr_override_value;
1076 else
1077 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1078
1079 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1080 esdmode2 |= (rtt_wr & 0x3) << 9;
1081 switch (i) {
1082 case 1:
1083 ddr->ddr_sdram_mode_4 = (0
1084 | ((esdmode2 & 0xFFFF) << 16)
1085 | ((esdmode3 & 0xFFFF) << 0)
1086 );
1087 break;
1088 case 2:
1089 ddr->ddr_sdram_mode_6 = (0
1090 | ((esdmode2 & 0xFFFF) << 16)
1091 | ((esdmode3 & 0xFFFF) << 0)
1092 );
1093 break;
1094 case 3:
1095 ddr->ddr_sdram_mode_8 = (0
1096 | ((esdmode2 & 0xFFFF) << 16)
1097 | ((esdmode3 & 0xFFFF) << 0)
1098 );
1099 break;
1100 }
1101 }
1102 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1103 ddr->ddr_sdram_mode_4);
1104 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1105 ddr->ddr_sdram_mode_6);
1106 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1107 ddr->ddr_sdram_mode_8);
1108 }
1109 }
1110
1111 #else /* for DDR2 and DDR1 */
1112 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1113 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1114 fsl_ddr_cfg_regs_t *ddr,
1115 const memctl_options_t *popts,
1116 const common_timing_params_t *common_dimm,
1117 const unsigned int unq_mrs_en)
1118 {
1119 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1120 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1121
1122 ddr->ddr_sdram_mode_2 = (0
1123 | ((esdmode2 & 0xFFFF) << 16)
1124 | ((esdmode3 & 0xFFFF) << 0)
1125 );
1126 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1127 }
1128 #endif
1129
1130 #ifdef CONFIG_SYS_FSL_DDR4
1131 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1132 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1133 const memctl_options_t *popts,
1134 const common_timing_params_t *common_dimm,
1135 const unsigned int unq_mrs_en)
1136 {
1137 int i;
1138 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
1139 unsigned short esdmode5; /* Extended SDRAM mode 5 */
1140 int rtt_park = 0;
1141 bool four_cs = false;
1142 const unsigned int mclk_ps = get_memory_clk_period_ps(0);
1143
1144 #if CONFIG_CHIP_SELECTS_PER_CTRL == 4
1145 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
1146 (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
1147 (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
1148 (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
1149 four_cs = true;
1150 #endif
1151 if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
1152 esdmode5 = 0x00000500; /* Data mask enable, RTT_PARK CS0 */
1153 rtt_park = four_cs ? 0 : 1;
1154 } else {
1155 esdmode5 = 0x00000400; /* Data mask enabled */
1156 }
1157
1158 /* set command/address parity latency */
1159 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
1160 if (mclk_ps >= 935) {
1161 /* for DDR4-1600/1866/2133 */
1162 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1163 } else if (mclk_ps >= 833) {
1164 /* for DDR4-2400 */
1165 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1166 } else {
1167 printf("parity: mclk_ps = %d not supported\n", mclk_ps);
1168 }
1169 }
1170
1171 ddr->ddr_sdram_mode_9 = (0
1172 | ((esdmode4 & 0xffff) << 16)
1173 | ((esdmode5 & 0xffff) << 0)
1174 );
1175
1176 /* Normally only the first enabled CS use 0x500, others use 0x400
1177 * But when four chip-selects are all enabled, all mode registers
1178 * need 0x500 to park.
1179 */
1180
1181 debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1182 if (unq_mrs_en) { /* unique mode registers are supported */
1183 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1184 if (!rtt_park &&
1185 (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
1186 esdmode5 |= 0x00000500; /* RTT_PARK */
1187 rtt_park = four_cs ? 0 : 1;
1188 } else {
1189 esdmode5 = 0x00000400;
1190 }
1191
1192 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
1193 if (mclk_ps >= 935) {
1194 /* for DDR4-1600/1866/2133 */
1195 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1196 } else if (mclk_ps >= 833) {
1197 /* for DDR4-2400 */
1198 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1199 } else {
1200 printf("parity: mclk_ps = %d not supported\n",
1201 mclk_ps);
1202 }
1203 }
1204
1205 switch (i) {
1206 case 1:
1207 ddr->ddr_sdram_mode_11 = (0
1208 | ((esdmode4 & 0xFFFF) << 16)
1209 | ((esdmode5 & 0xFFFF) << 0)
1210 );
1211 break;
1212 case 2:
1213 ddr->ddr_sdram_mode_13 = (0
1214 | ((esdmode4 & 0xFFFF) << 16)
1215 | ((esdmode5 & 0xFFFF) << 0)
1216 );
1217 break;
1218 case 3:
1219 ddr->ddr_sdram_mode_15 = (0
1220 | ((esdmode4 & 0xFFFF) << 16)
1221 | ((esdmode5 & 0xFFFF) << 0)
1222 );
1223 break;
1224 }
1225 }
1226 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1227 ddr->ddr_sdram_mode_11);
1228 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1229 ddr->ddr_sdram_mode_13);
1230 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1231 ddr->ddr_sdram_mode_15);
1232 }
1233 }
1234
1235 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1236 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1237 fsl_ddr_cfg_regs_t *ddr,
1238 const memctl_options_t *popts,
1239 const common_timing_params_t *common_dimm,
1240 const unsigned int unq_mrs_en)
1241 {
1242 int i;
1243 unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
1244 unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
1245 unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1246
1247 esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1248
1249 if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
1250 esdmode6 |= 1 << 6; /* Range 2 */
1251
1252 ddr->ddr_sdram_mode_10 = (0
1253 | ((esdmode6 & 0xffff) << 16)
1254 | ((esdmode7 & 0xffff) << 0)
1255 );
1256 debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
1257 if (unq_mrs_en) { /* unique mode registers are supported */
1258 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1259 switch (i) {
1260 case 1:
1261 ddr->ddr_sdram_mode_12 = (0
1262 | ((esdmode6 & 0xFFFF) << 16)
1263 | ((esdmode7 & 0xFFFF) << 0)
1264 );
1265 break;
1266 case 2:
1267 ddr->ddr_sdram_mode_14 = (0
1268 | ((esdmode6 & 0xFFFF) << 16)
1269 | ((esdmode7 & 0xFFFF) << 0)
1270 );
1271 break;
1272 case 3:
1273 ddr->ddr_sdram_mode_16 = (0
1274 | ((esdmode6 & 0xFFFF) << 16)
1275 | ((esdmode7 & 0xFFFF) << 0)
1276 );
1277 break;
1278 }
1279 }
1280 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1281 ddr->ddr_sdram_mode_12);
1282 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1283 ddr->ddr_sdram_mode_14);
1284 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1285 ddr->ddr_sdram_mode_16);
1286 }
1287 }
1288
1289 #endif
1290
1291 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1292 static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1293 fsl_ddr_cfg_regs_t *ddr,
1294 const memctl_options_t *popts,
1295 const common_timing_params_t *common_dimm)
1296 {
1297 unsigned int refint; /* Refresh interval */
1298 unsigned int bstopre; /* Precharge interval */
1299
1300 refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
1301
1302 bstopre = popts->bstopre;
1303
1304 /* refint field used 0x3FFF in earlier controllers */
1305 ddr->ddr_sdram_interval = (0
1306 | ((refint & 0xFFFF) << 16)
1307 | ((bstopre & 0x3FFF) << 0)
1308 );
1309 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1310 }
1311
1312 #ifdef CONFIG_SYS_FSL_DDR4
1313 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1314 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1315 fsl_ddr_cfg_regs_t *ddr,
1316 const memctl_options_t *popts,
1317 const common_timing_params_t *common_dimm,
1318 unsigned int cas_latency,
1319 unsigned int additive_latency,
1320 const unsigned int unq_mrs_en)
1321 {
1322 int i;
1323 unsigned short esdmode; /* Extended SDRAM mode */
1324 unsigned short sdmode; /* SDRAM mode */
1325
1326 /* Mode Register - MR1 */
1327 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1328 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1329 unsigned int rtt;
1330 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1331 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1332 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1333 unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
1334 0=Disable (Test/Debug) */
1335
1336 /* Mode Register - MR0 */
1337 unsigned int wr = 0; /* Write Recovery */
1338 unsigned int dll_rst; /* DLL Reset */
1339 unsigned int mode; /* Normal=0 or Test=1 */
1340 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1341 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1342 unsigned int bt;
1343 unsigned int bl; /* BL: Burst Length */
1344
1345 unsigned int wr_mclk;
1346 /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1347 static const u8 wr_table[] = {
1348 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1349 /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1350 static const u8 cas_latency_table[] = {
1351 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1352 9, 9, 10, 10, 11, 11};
1353
1354 if (popts->rtt_override)
1355 rtt = popts->rtt_override_value;
1356 else
1357 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1358
1359 if (additive_latency == (cas_latency - 1))
1360 al = 1;
1361 if (additive_latency == (cas_latency - 2))
1362 al = 2;
1363
1364 if (popts->quad_rank_present)
1365 dic = 1; /* output driver impedance 240/7 ohm */
1366
1367 /*
1368 * The esdmode value will also be used for writing
1369 * MR1 during write leveling for DDR3, although the
1370 * bits specifically related to the write leveling
1371 * scheme will be handled automatically by the DDR
1372 * controller. so we set the wrlvl_en = 0 here.
1373 */
1374 esdmode = (0
1375 | ((qoff & 0x1) << 12)
1376 | ((tdqs_en & 0x1) << 11)
1377 | ((rtt & 0x7) << 8)
1378 | ((wrlvl_en & 0x1) << 7)
1379 | ((al & 0x3) << 3)
1380 | ((dic & 0x3) << 1) /* DIC field is split */
1381 | ((dll_en & 0x1) << 0)
1382 );
1383
1384 /*
1385 * DLL control for precharge PD
1386 * 0=slow exit DLL off (tXPDLL)
1387 * 1=fast exit DLL on (tXP)
1388 */
1389
1390 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1391 if (wr_mclk <= 24) {
1392 wr = wr_table[wr_mclk - 10];
1393 } else {
1394 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1395 wr_mclk);
1396 }
1397
1398 dll_rst = 0; /* dll no reset */
1399 mode = 0; /* normal mode */
1400
1401 /* look up table to get the cas latency bits */
1402 if (cas_latency >= 9 && cas_latency <= 24)
1403 caslat = cas_latency_table[cas_latency - 9];
1404 else
1405 printf("Error: unsupported cas latency for mode register\n");
1406
1407 bt = 0; /* Nibble sequential */
1408
1409 switch (popts->burst_length) {
1410 case DDR_BL8:
1411 bl = 0;
1412 break;
1413 case DDR_OTF:
1414 bl = 1;
1415 break;
1416 case DDR_BC4:
1417 bl = 2;
1418 break;
1419 default:
1420 printf("Error: invalid burst length of %u specified. ",
1421 popts->burst_length);
1422 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1423 bl = 1;
1424 break;
1425 }
1426
1427 sdmode = (0
1428 | ((wr & 0x7) << 9)
1429 | ((dll_rst & 0x1) << 8)
1430 | ((mode & 0x1) << 7)
1431 | (((caslat >> 1) & 0x7) << 4)
1432 | ((bt & 0x1) << 3)
1433 | ((caslat & 1) << 2)
1434 | ((bl & 0x3) << 0)
1435 );
1436
1437 ddr->ddr_sdram_mode = (0
1438 | ((esdmode & 0xFFFF) << 16)
1439 | ((sdmode & 0xFFFF) << 0)
1440 );
1441
1442 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1443
1444 if (unq_mrs_en) { /* unique mode registers are supported */
1445 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1446 if (popts->rtt_override)
1447 rtt = popts->rtt_override_value;
1448 else
1449 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1450
1451 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
1452 esdmode |= (rtt & 0x7) << 8;
1453 switch (i) {
1454 case 1:
1455 ddr->ddr_sdram_mode_3 = (0
1456 | ((esdmode & 0xFFFF) << 16)
1457 | ((sdmode & 0xFFFF) << 0)
1458 );
1459 break;
1460 case 2:
1461 ddr->ddr_sdram_mode_5 = (0
1462 | ((esdmode & 0xFFFF) << 16)
1463 | ((sdmode & 0xFFFF) << 0)
1464 );
1465 break;
1466 case 3:
1467 ddr->ddr_sdram_mode_7 = (0
1468 | ((esdmode & 0xFFFF) << 16)
1469 | ((sdmode & 0xFFFF) << 0)
1470 );
1471 break;
1472 }
1473 }
1474 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1475 ddr->ddr_sdram_mode_3);
1476 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1477 ddr->ddr_sdram_mode_5);
1478 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1479 ddr->ddr_sdram_mode_5);
1480 }
1481 }
1482
1483 #elif defined(CONFIG_SYS_FSL_DDR3)
1484 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1485 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1486 fsl_ddr_cfg_regs_t *ddr,
1487 const memctl_options_t *popts,
1488 const common_timing_params_t *common_dimm,
1489 unsigned int cas_latency,
1490 unsigned int additive_latency,
1491 const unsigned int unq_mrs_en)
1492 {
1493 int i;
1494 unsigned short esdmode; /* Extended SDRAM mode */
1495 unsigned short sdmode; /* SDRAM mode */
1496
1497 /* Mode Register - MR1 */
1498 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1499 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1500 unsigned int rtt;
1501 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1502 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1503 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1504 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1505 1=Disable (Test/Debug) */
1506
1507 /* Mode Register - MR0 */
1508 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
1509 unsigned int wr = 0; /* Write Recovery */
1510 unsigned int dll_rst; /* DLL Reset */
1511 unsigned int mode; /* Normal=0 or Test=1 */
1512 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1513 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1514 unsigned int bt;
1515 unsigned int bl; /* BL: Burst Length */
1516
1517 unsigned int wr_mclk;
1518 /*
1519 * DDR_SDRAM_MODE doesn't support 9,11,13,15
1520 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1521 * for this table
1522 */
1523 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1524
1525 if (popts->rtt_override)
1526 rtt = popts->rtt_override_value;
1527 else
1528 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1529
1530 if (additive_latency == (cas_latency - 1))
1531 al = 1;
1532 if (additive_latency == (cas_latency - 2))
1533 al = 2;
1534
1535 if (popts->quad_rank_present)
1536 dic = 1; /* output driver impedance 240/7 ohm */
1537
1538 /*
1539 * The esdmode value will also be used for writing
1540 * MR1 during write leveling for DDR3, although the
1541 * bits specifically related to the write leveling
1542 * scheme will be handled automatically by the DDR
1543 * controller. so we set the wrlvl_en = 0 here.
1544 */
1545 esdmode = (0
1546 | ((qoff & 0x1) << 12)
1547 | ((tdqs_en & 0x1) << 11)
1548 | ((rtt & 0x4) << 7) /* rtt field is split */
1549 | ((wrlvl_en & 0x1) << 7)
1550 | ((rtt & 0x2) << 5) /* rtt field is split */
1551 | ((dic & 0x2) << 4) /* DIC field is split */
1552 | ((al & 0x3) << 3)
1553 | ((rtt & 0x1) << 2) /* rtt field is split */
1554 | ((dic & 0x1) << 1) /* DIC field is split */
1555 | ((dll_en & 0x1) << 0)
1556 );
1557
1558 /*
1559 * DLL control for precharge PD
1560 * 0=slow exit DLL off (tXPDLL)
1561 * 1=fast exit DLL on (tXP)
1562 */
1563 dll_on = 1;
1564
1565 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1566 if (wr_mclk <= 16) {
1567 wr = wr_table[wr_mclk - 5];
1568 } else {
1569 printf("Error: unsupported write recovery for mode register "
1570 "wr_mclk = %d\n", wr_mclk);
1571 }
1572
1573 dll_rst = 0; /* dll no reset */
1574 mode = 0; /* normal mode */
1575
1576 /* look up table to get the cas latency bits */
1577 if (cas_latency >= 5 && cas_latency <= 16) {
1578 unsigned char cas_latency_table[] = {
1579 0x2, /* 5 clocks */
1580 0x4, /* 6 clocks */
1581 0x6, /* 7 clocks */
1582 0x8, /* 8 clocks */
1583 0xa, /* 9 clocks */
1584 0xc, /* 10 clocks */
1585 0xe, /* 11 clocks */
1586 0x1, /* 12 clocks */
1587 0x3, /* 13 clocks */
1588 0x5, /* 14 clocks */
1589 0x7, /* 15 clocks */
1590 0x9, /* 16 clocks */
1591 };
1592 caslat = cas_latency_table[cas_latency - 5];
1593 } else {
1594 printf("Error: unsupported cas latency for mode register\n");
1595 }
1596
1597 bt = 0; /* Nibble sequential */
1598
1599 switch (popts->burst_length) {
1600 case DDR_BL8:
1601 bl = 0;
1602 break;
1603 case DDR_OTF:
1604 bl = 1;
1605 break;
1606 case DDR_BC4:
1607 bl = 2;
1608 break;
1609 default:
1610 printf("Error: invalid burst length of %u specified. "
1611 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1612 popts->burst_length);
1613 bl = 1;
1614 break;
1615 }
1616
1617 sdmode = (0
1618 | ((dll_on & 0x1) << 12)
1619 | ((wr & 0x7) << 9)
1620 | ((dll_rst & 0x1) << 8)
1621 | ((mode & 0x1) << 7)
1622 | (((caslat >> 1) & 0x7) << 4)
1623 | ((bt & 0x1) << 3)
1624 | ((caslat & 1) << 2)
1625 | ((bl & 0x3) << 0)
1626 );
1627
1628 ddr->ddr_sdram_mode = (0
1629 | ((esdmode & 0xFFFF) << 16)
1630 | ((sdmode & 0xFFFF) << 0)
1631 );
1632
1633 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1634
1635 if (unq_mrs_en) { /* unique mode registers are supported */
1636 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1637 if (popts->rtt_override)
1638 rtt = popts->rtt_override_value;
1639 else
1640 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1641
1642 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1643 esdmode |= (0
1644 | ((rtt & 0x4) << 7) /* rtt field is split */
1645 | ((rtt & 0x2) << 5) /* rtt field is split */
1646 | ((rtt & 0x1) << 2) /* rtt field is split */
1647 );
1648 switch (i) {
1649 case 1:
1650 ddr->ddr_sdram_mode_3 = (0
1651 | ((esdmode & 0xFFFF) << 16)
1652 | ((sdmode & 0xFFFF) << 0)
1653 );
1654 break;
1655 case 2:
1656 ddr->ddr_sdram_mode_5 = (0
1657 | ((esdmode & 0xFFFF) << 16)
1658 | ((sdmode & 0xFFFF) << 0)
1659 );
1660 break;
1661 case 3:
1662 ddr->ddr_sdram_mode_7 = (0
1663 | ((esdmode & 0xFFFF) << 16)
1664 | ((sdmode & 0xFFFF) << 0)
1665 );
1666 break;
1667 }
1668 }
1669 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1670 ddr->ddr_sdram_mode_3);
1671 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1672 ddr->ddr_sdram_mode_5);
1673 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1674 ddr->ddr_sdram_mode_5);
1675 }
1676 }
1677
1678 #else /* !CONFIG_SYS_FSL_DDR3 */
1679
1680 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1681 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1682 fsl_ddr_cfg_regs_t *ddr,
1683 const memctl_options_t *popts,
1684 const common_timing_params_t *common_dimm,
1685 unsigned int cas_latency,
1686 unsigned int additive_latency,
1687 const unsigned int unq_mrs_en)
1688 {
1689 unsigned short esdmode; /* Extended SDRAM mode */
1690 unsigned short sdmode; /* SDRAM mode */
1691
1692 /*
1693 * FIXME: This ought to be pre-calculated in a
1694 * technology-specific routine,
1695 * e.g. compute_DDR2_mode_register(), and then the
1696 * sdmode and esdmode passed in as part of common_dimm.
1697 */
1698
1699 /* Extended Mode Register */
1700 unsigned int mrs = 0; /* Mode Register Set */
1701 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1702 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1703 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1704 unsigned int ocd = 0; /* 0x0=OCD not supported,
1705 0x7=OCD default state */
1706 unsigned int rtt;
1707 unsigned int al; /* Posted CAS# additive latency (AL) */
1708 unsigned int ods = 0; /* Output Drive Strength:
1709 0 = Full strength (18ohm)
1710 1 = Reduced strength (4ohm) */
1711 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1712 1=Disable (Test/Debug) */
1713
1714 /* Mode Register (MR) */
1715 unsigned int mr; /* Mode Register Definition */
1716 unsigned int pd; /* Power-Down Mode */
1717 unsigned int wr; /* Write Recovery */
1718 unsigned int dll_res; /* DLL Reset */
1719 unsigned int mode; /* Normal=0 or Test=1 */
1720 unsigned int caslat = 0;/* CAS# latency */
1721 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1722 unsigned int bt;
1723 unsigned int bl; /* BL: Burst Length */
1724
1725 dqs_en = !popts->dqs_config;
1726 rtt = fsl_ddr_get_rtt();
1727
1728 al = additive_latency;
1729
1730 esdmode = (0
1731 | ((mrs & 0x3) << 14)
1732 | ((outputs & 0x1) << 12)
1733 | ((rdqs_en & 0x1) << 11)
1734 | ((dqs_en & 0x1) << 10)
1735 | ((ocd & 0x7) << 7)
1736 | ((rtt & 0x2) << 5) /* rtt field is split */
1737 | ((al & 0x7) << 3)
1738 | ((rtt & 0x1) << 2) /* rtt field is split */
1739 | ((ods & 0x1) << 1)
1740 | ((dll_en & 0x1) << 0)
1741 );
1742
1743 mr = 0; /* FIXME: CHECKME */
1744
1745 /*
1746 * 0 = Fast Exit (Normal)
1747 * 1 = Slow Exit (Low Power)
1748 */
1749 pd = 0;
1750
1751 #if defined(CONFIG_SYS_FSL_DDR1)
1752 wr = 0; /* Historical */
1753 #elif defined(CONFIG_SYS_FSL_DDR2)
1754 wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1755 #endif
1756 dll_res = 0;
1757 mode = 0;
1758
1759 #if defined(CONFIG_SYS_FSL_DDR1)
1760 if (1 <= cas_latency && cas_latency <= 4) {
1761 unsigned char mode_caslat_table[4] = {
1762 0x5, /* 1.5 clocks */
1763 0x2, /* 2.0 clocks */
1764 0x6, /* 2.5 clocks */
1765 0x3 /* 3.0 clocks */
1766 };
1767 caslat = mode_caslat_table[cas_latency - 1];
1768 } else {
1769 printf("Warning: unknown cas_latency %d\n", cas_latency);
1770 }
1771 #elif defined(CONFIG_SYS_FSL_DDR2)
1772 caslat = cas_latency;
1773 #endif
1774 bt = 0;
1775
1776 switch (popts->burst_length) {
1777 case DDR_BL4:
1778 bl = 2;
1779 break;
1780 case DDR_BL8:
1781 bl = 3;
1782 break;
1783 default:
1784 printf("Error: invalid burst length of %u specified. "
1785 " Defaulting to 4 beats.\n",
1786 popts->burst_length);
1787 bl = 2;
1788 break;
1789 }
1790
1791 sdmode = (0
1792 | ((mr & 0x3) << 14)
1793 | ((pd & 0x1) << 12)
1794 | ((wr & 0x7) << 9)
1795 | ((dll_res & 0x1) << 8)
1796 | ((mode & 0x1) << 7)
1797 | ((caslat & 0x7) << 4)
1798 | ((bt & 0x1) << 3)
1799 | ((bl & 0x7) << 0)
1800 );
1801
1802 ddr->ddr_sdram_mode = (0
1803 | ((esdmode & 0xFFFF) << 16)
1804 | ((sdmode & 0xFFFF) << 0)
1805 );
1806 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1807 }
1808 #endif
1809
1810 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1811 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1812 {
1813 unsigned int init_value; /* Initialization value */
1814
1815 #ifdef CONFIG_MEM_INIT_VALUE
1816 init_value = CONFIG_MEM_INIT_VALUE;
1817 #else
1818 init_value = 0xDEADBEEF;
1819 #endif
1820 ddr->ddr_data_init = init_value;
1821 }
1822
1823 /*
1824 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1825 * The old controller on the 8540/60 doesn't have this register.
1826 * Hope it's OK to set it (to 0) anyway.
1827 */
1828 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1829 const memctl_options_t *popts)
1830 {
1831 unsigned int clk_adjust; /* Clock adjust */
1832 unsigned int ss_en = 0; /* Source synchronous enable */
1833
1834 #if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
1835 /* Per FSL Application Note: AN2805 */
1836 ss_en = 1;
1837 #endif
1838 if (fsl_ddr_get_version(0) >= 0x40701) {
1839 /* clk_adjust in 5-bits on T-series and LS-series */
1840 clk_adjust = (popts->clk_adjust & 0x1F) << 22;
1841 } else {
1842 /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
1843 clk_adjust = (popts->clk_adjust & 0xF) << 23;
1844 }
1845
1846 ddr->ddr_sdram_clk_cntl = (0
1847 | ((ss_en & 0x1) << 31)
1848 | clk_adjust
1849 );
1850 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1851 }
1852
1853 /* DDR Initialization Address (DDR_INIT_ADDR) */
1854 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1855 {
1856 unsigned int init_addr = 0; /* Initialization address */
1857
1858 ddr->ddr_init_addr = init_addr;
1859 }
1860
1861 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1862 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1863 {
1864 unsigned int uia = 0; /* Use initialization address */
1865 unsigned int init_ext_addr = 0; /* Initialization address */
1866
1867 ddr->ddr_init_ext_addr = (0
1868 | ((uia & 0x1) << 31)
1869 | (init_ext_addr & 0xF)
1870 );
1871 }
1872
1873 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1874 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1875 const memctl_options_t *popts)
1876 {
1877 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1878 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1879 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1880 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1881 unsigned int trwt_mclk = 0; /* ext_rwt */
1882 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1883
1884 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1885 if (popts->burst_length == DDR_BL8) {
1886 /* We set BL/2 for fixed BL8 */
1887 rrt = 0; /* BL/2 clocks */
1888 wwt = 0; /* BL/2 clocks */
1889 } else {
1890 /* We need to set BL/2 + 2 to BC4 and OTF */
1891 rrt = 2; /* BL/2 + 2 clocks */
1892 wwt = 2; /* BL/2 + 2 clocks */
1893 }
1894 #endif
1895 #ifdef CONFIG_SYS_FSL_DDR4
1896 dll_lock = 2; /* tDLLK = 1024 clocks */
1897 #elif defined(CONFIG_SYS_FSL_DDR3)
1898 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1899 #endif
1900
1901 if (popts->trwt_override)
1902 trwt_mclk = popts->trwt;
1903
1904 ddr->timing_cfg_4 = (0
1905 | ((rwt & 0xf) << 28)
1906 | ((wrt & 0xf) << 24)
1907 | ((rrt & 0xf) << 20)
1908 | ((wwt & 0xf) << 16)
1909 | ((trwt_mclk & 0xc) << 12)
1910 | (dll_lock & 0x3)
1911 );
1912 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1913 }
1914
1915 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1916 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1917 {
1918 unsigned int rodt_on = 0; /* Read to ODT on */
1919 unsigned int rodt_off = 0; /* Read to ODT off */
1920 unsigned int wodt_on = 0; /* Write to ODT on */
1921 unsigned int wodt_off = 0; /* Write to ODT off */
1922
1923 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1924 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1925 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1926 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1927 if (cas_latency >= wr_lat)
1928 rodt_on = cas_latency - wr_lat + 1;
1929 rodt_off = 4; /* 4 clocks */
1930 wodt_on = 1; /* 1 clocks */
1931 wodt_off = 4; /* 4 clocks */
1932 #endif
1933
1934 ddr->timing_cfg_5 = (0
1935 | ((rodt_on & 0x1f) << 24)
1936 | ((rodt_off & 0x7) << 20)
1937 | ((wodt_on & 0x1f) << 12)
1938 | ((wodt_off & 0x7) << 8)
1939 );
1940 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1941 }
1942
1943 #ifdef CONFIG_SYS_FSL_DDR4
1944 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1945 {
1946 unsigned int hs_caslat = 0;
1947 unsigned int hs_wrlat = 0;
1948 unsigned int hs_wrrec = 0;
1949 unsigned int hs_clkadj = 0;
1950 unsigned int hs_wrlvl_start = 0;
1951
1952 ddr->timing_cfg_6 = (0
1953 | ((hs_caslat & 0x1f) << 24)
1954 | ((hs_wrlat & 0x1f) << 19)
1955 | ((hs_wrrec & 0x1f) << 12)
1956 | ((hs_clkadj & 0x1f) << 6)
1957 | ((hs_wrlvl_start & 0x1f) << 0)
1958 );
1959 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1960 }
1961
1962 static void set_timing_cfg_7(const unsigned int ctrl_num,
1963 fsl_ddr_cfg_regs_t *ddr,
1964 const common_timing_params_t *common_dimm)
1965 {
1966 unsigned int txpr, tcksre, tcksrx;
1967 unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd;
1968 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
1969
1970 txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
1971 tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
1972 tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
1973
1974 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
1975 if (mclk_ps >= 935) {
1976 /* parity latency 4 clocks in case of 1600/1866/2133 */
1977 par_lat = 4;
1978 } else if (mclk_ps >= 833) {
1979 /* parity latency 5 clocks for DDR4-2400 */
1980 par_lat = 5;
1981 } else {
1982 printf("parity: mclk_ps = %d not supported\n", mclk_ps);
1983 }
1984 }
1985
1986 cs_to_cmd = 0;
1987
1988 if (txpr <= 200)
1989 cke_rst = 0;
1990 else if (txpr <= 256)
1991 cke_rst = 1;
1992 else if (txpr <= 512)
1993 cke_rst = 2;
1994 else
1995 cke_rst = 3;
1996
1997 if (tcksre <= 19)
1998 cksre = tcksre - 5;
1999 else
2000 cksre = 15;
2001
2002 if (tcksrx <= 19)
2003 cksrx = tcksrx - 5;
2004 else
2005 cksrx = 15;
2006
2007 ddr->timing_cfg_7 = (0
2008 | ((cke_rst & 0x3) << 28)
2009 | ((cksre & 0xf) << 24)
2010 | ((cksrx & 0xf) << 20)
2011 | ((par_lat & 0xf) << 16)
2012 | ((cs_to_cmd & 0xf) << 4)
2013 );
2014 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
2015 }
2016
2017 static void set_timing_cfg_8(const unsigned int ctrl_num,
2018 fsl_ddr_cfg_regs_t *ddr,
2019 const memctl_options_t *popts,
2020 const common_timing_params_t *common_dimm,
2021 unsigned int cas_latency)
2022 {
2023 unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
2024 unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
2025 unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
2026 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
2027 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
2028
2029 rwt_bg = cas_latency + 2 + 4 - wr_lat;
2030 if (rwt_bg < tccdl)
2031 rwt_bg = tccdl - rwt_bg;
2032 else
2033 rwt_bg = 0;
2034
2035 wrt_bg = wr_lat + 4 + 1 - cas_latency;
2036 if (wrt_bg < tccdl)
2037 wrt_bg = tccdl - wrt_bg;
2038 else
2039 wrt_bg = 0;
2040
2041 if (popts->burst_length == DDR_BL8) {
2042 rrt_bg = tccdl - 4;
2043 wwt_bg = tccdl - 4;
2044 } else {
2045 rrt_bg = tccdl - 2;
2046 wwt_bg = tccdl - 2;
2047 }
2048
2049 acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
2050 wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
2051 if (popts->otf_burst_chop_en)
2052 wrtord_bg += 2;
2053
2054 pre_all_rec = 0;
2055
2056 ddr->timing_cfg_8 = (0
2057 | ((rwt_bg & 0xf) << 28)
2058 | ((wrt_bg & 0xf) << 24)
2059 | ((rrt_bg & 0xf) << 20)
2060 | ((wwt_bg & 0xf) << 16)
2061 | ((acttoact_bg & 0xf) << 12)
2062 | ((wrtord_bg & 0xf) << 8)
2063 | ((pre_all_rec & 0x1f) << 0)
2064 );
2065
2066 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
2067 }
2068
2069 static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
2070 {
2071 ddr->timing_cfg_9 = 0;
2072 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
2073 }
2074
2075 /* This function needs to be called after set_ddr_sdram_cfg() is called */
2076 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
2077 const dimm_params_t *dimm_params)
2078 {
2079 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
2080 int i;
2081
2082 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
2083 if (dimm_params[i].n_ranks)
2084 break;
2085 }
2086 if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
2087 puts("DDR error: no DIMM found!\n");
2088 return;
2089 }
2090
2091 ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
2092 ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
2093 ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
2094 ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
2095 ((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
2096
2097 ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
2098 ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
2099 ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
2100 ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
2101 ((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
2102
2103 ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
2104 ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
2105 ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
2106 ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
2107 ((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
2108
2109 /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
2110 ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
2111 ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
2112 (acc_ecc_en ? 0 :
2113 (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
2114 dimm_params[i].dq_mapping_ors;
2115
2116 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
2117 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
2118 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
2119 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
2120 }
2121 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
2122 const memctl_options_t *popts)
2123 {
2124 int rd_pre;
2125
2126 rd_pre = popts->quad_rank_present ? 1 : 0;
2127
2128 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
2129
2130 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2131 }
2132 #endif /* CONFIG_SYS_FSL_DDR4 */
2133
2134 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
2135 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
2136 {
2137 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2138 /* Normal Operation Full Calibration Time (tZQoper) */
2139 unsigned int zqoper = 0;
2140 /* Normal Operation Short Calibration Time (tZQCS) */
2141 unsigned int zqcs = 0;
2142 #ifdef CONFIG_SYS_FSL_DDR4
2143 unsigned int zqcs_init;
2144 #endif
2145
2146 if (zq_en) {
2147 #ifdef CONFIG_SYS_FSL_DDR4
2148 zqinit = 10; /* 1024 clocks */
2149 zqoper = 9; /* 512 clocks */
2150 zqcs = 7; /* 128 clocks */
2151 zqcs_init = 5; /* 1024 refresh sequences */
2152 #else
2153 zqinit = 9; /* 512 clocks */
2154 zqoper = 8; /* 256 clocks */
2155 zqcs = 6; /* 64 clocks */
2156 #endif
2157 }
2158
2159 ddr->ddr_zq_cntl = (0
2160 | ((zq_en & 0x1) << 31)
2161 | ((zqinit & 0xF) << 24)
2162 | ((zqoper & 0xF) << 16)
2163 | ((zqcs & 0xF) << 8)
2164 #ifdef CONFIG_SYS_FSL_DDR4
2165 | ((zqcs_init & 0xF) << 0)
2166 #endif
2167 );
2168 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
2169 }
2170
2171 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
2172 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2173 const memctl_options_t *popts)
2174 {
2175 /*
2176 * First DQS pulse rising edge after margining mode
2177 * is programmed (tWL_MRD)
2178 */
2179 unsigned int wrlvl_mrd = 0;
2180 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2181 unsigned int wrlvl_odten = 0;
2182 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2183 unsigned int wrlvl_dqsen = 0;
2184 /* WRLVL_SMPL: Write leveling sample time */
2185 unsigned int wrlvl_smpl = 0;
2186 /* WRLVL_WLR: Write leveling repeition time */
2187 unsigned int wrlvl_wlr = 0;
2188 /* WRLVL_START: Write leveling start time */
2189 unsigned int wrlvl_start = 0;
2190
2191 /* suggest enable write leveling for DDR3 due to fly-by topology */
2192 if (wrlvl_en) {
2193 /* tWL_MRD min = 40 nCK, we set it 64 */
2194 wrlvl_mrd = 0x6;
2195 /* tWL_ODTEN 128 */
2196 wrlvl_odten = 0x7;
2197 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2198 wrlvl_dqsen = 0x5;
2199 /*
2200 * Write leveling sample time at least need 6 clocks
2201 * higher than tWLO to allow enough time for progagation
2202 * delay and sampling the prime data bits.
2203 */
2204 wrlvl_smpl = 0xf;
2205 /*
2206 * Write leveling repetition time
2207 * at least tWLO + 6 clocks clocks
2208 * we set it 64
2209 */
2210 wrlvl_wlr = 0x6;
2211 /*
2212 * Write leveling start time
2213 * The value use for the DQS_ADJUST for the first sample
2214 * when write leveling is enabled. It probably needs to be
2215 * overridden per platform.
2216 */
2217 wrlvl_start = 0x8;
2218 /*
2219 * Override the write leveling sample and start time
2220 * according to specific board
2221 */
2222 if (popts->wrlvl_override) {
2223 wrlvl_smpl = popts->wrlvl_sample;
2224 wrlvl_start = popts->wrlvl_start;
2225 }
2226 }
2227
2228 ddr->ddr_wrlvl_cntl = (0
2229 | ((wrlvl_en & 0x1) << 31)
2230 | ((wrlvl_mrd & 0x7) << 24)
2231 | ((wrlvl_odten & 0x7) << 20)
2232 | ((wrlvl_dqsen & 0x7) << 16)
2233 | ((wrlvl_smpl & 0xf) << 12)
2234 | ((wrlvl_wlr & 0x7) << 8)
2235 | ((wrlvl_start & 0x1F) << 0)
2236 );
2237 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2238 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2239 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2240 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2241 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2242
2243 }
2244
2245 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
2246 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2247 {
2248 /* Self Refresh Idle Threshold */
2249 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2250 }
2251
2252 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2253 {
2254 if (popts->addr_hash) {
2255 ddr->ddr_eor = 0x40000000; /* address hash enable */
2256 puts("Address hashing enabled.\n");
2257 }
2258 }
2259
2260 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2261 {
2262 ddr->ddr_cdr1 = popts->ddr_cdr1;
2263 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2264 }
2265
2266 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2267 {
2268 ddr->ddr_cdr2 = popts->ddr_cdr2;
2269 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2270 }
2271
2272 unsigned int
2273 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2274 {
2275 unsigned int res = 0;
2276
2277 /*
2278 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2279 * not set at the same time.
2280 */
2281 if (ddr->ddr_sdram_cfg & 0x10000000
2282 && ddr->ddr_sdram_cfg & 0x00008000) {
2283 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2284 " should not be set at the same time.\n");
2285 res++;
2286 }
2287
2288 return res;
2289 }
2290
2291 unsigned int
2292 compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2293 const memctl_options_t *popts,
2294 fsl_ddr_cfg_regs_t *ddr,
2295 const common_timing_params_t *common_dimm,
2296 const dimm_params_t *dimm_params,
2297 unsigned int dbw_cap_adj,
2298 unsigned int size_only)
2299 {
2300 unsigned int i;
2301 unsigned int cas_latency;
2302 unsigned int additive_latency;
2303 unsigned int sr_it;
2304 unsigned int zq_en;
2305 unsigned int wrlvl_en;
2306 unsigned int ip_rev = 0;
2307 unsigned int unq_mrs_en = 0;
2308 int cs_en = 1;
2309
2310 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2311
2312 if (common_dimm == NULL) {
2313 printf("Error: subset DIMM params struct null pointer\n");
2314 return 1;
2315 }
2316
2317 /*
2318 * Process overrides first.
2319 *
2320 * FIXME: somehow add dereated caslat to this
2321 */
2322 cas_latency = (popts->cas_latency_override)
2323 ? popts->cas_latency_override_value
2324 : common_dimm->lowest_common_spd_caslat;
2325
2326 additive_latency = (popts->additive_latency_override)
2327 ? popts->additive_latency_override_value
2328 : common_dimm->additive_latency;
2329
2330 sr_it = (popts->auto_self_refresh_en)
2331 ? popts->sr_it
2332 : 0;
2333 /* ZQ calibration */
2334 zq_en = (popts->zq_en) ? 1 : 0;
2335 /* write leveling */
2336 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2337
2338 /* Chip Select Memory Bounds (CSn_BNDS) */
2339 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2340 unsigned long long ea, sa;
2341 unsigned int cs_per_dimm
2342 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2343 unsigned int dimm_number
2344 = i / cs_per_dimm;
2345 unsigned long long rank_density
2346 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2347
2348 if (dimm_params[dimm_number].n_ranks == 0) {
2349 debug("Skipping setup of CS%u "
2350 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2351 continue;
2352 }
2353 if (popts->memctl_interleaving) {
2354 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2355 case FSL_DDR_CS0_CS1_CS2_CS3:
2356 break;
2357 case FSL_DDR_CS0_CS1:
2358 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2359 if (i > 1)
2360 cs_en = 0;
2361 break;
2362 case FSL_DDR_CS2_CS3:
2363 default:
2364 if (i > 0)
2365 cs_en = 0;
2366 break;
2367 }
2368 sa = common_dimm->base_address;
2369 ea = sa + common_dimm->total_mem - 1;
2370 } else if (!popts->memctl_interleaving) {
2371 /*
2372 * If memory interleaving between controllers is NOT
2373 * enabled, the starting address for each memory
2374 * controller is distinct. However, because rank
2375 * interleaving is enabled, the starting and ending
2376 * addresses of the total memory on that memory
2377 * controller needs to be programmed into its
2378 * respective CS0_BNDS.
2379 */
2380 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2381 case FSL_DDR_CS0_CS1_CS2_CS3:
2382 sa = common_dimm->base_address;
2383 ea = sa + common_dimm->total_mem - 1;
2384 break;
2385 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2386 if ((i >= 2) && (dimm_number == 0)) {
2387 sa = dimm_params[dimm_number].base_address +
2388 2 * rank_density;
2389 ea = sa + 2 * rank_density - 1;
2390 } else {
2391 sa = dimm_params[dimm_number].base_address;
2392 ea = sa + 2 * rank_density - 1;
2393 }
2394 break;
2395 case FSL_DDR_CS0_CS1:
2396 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2397 sa = dimm_params[dimm_number].base_address;
2398 ea = sa + rank_density - 1;
2399 if (i != 1)
2400 sa += (i % cs_per_dimm) * rank_density;
2401 ea += (i % cs_per_dimm) * rank_density;
2402 } else {
2403 sa = 0;
2404 ea = 0;
2405 }
2406 if (i == 0)
2407 ea += rank_density;
2408 break;
2409 case FSL_DDR_CS2_CS3:
2410 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2411 sa = dimm_params[dimm_number].base_address;
2412 ea = sa + rank_density - 1;
2413 if (i != 3)
2414 sa += (i % cs_per_dimm) * rank_density;
2415 ea += (i % cs_per_dimm) * rank_density;
2416 } else {
2417 sa = 0;
2418 ea = 0;
2419 }
2420 if (i == 2)
2421 ea += (rank_density >> dbw_cap_adj);
2422 break;
2423 default: /* No bank(chip-select) interleaving */
2424 sa = dimm_params[dimm_number].base_address;
2425 ea = sa + rank_density - 1;
2426 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2427 sa += (i % cs_per_dimm) * rank_density;
2428 ea += (i % cs_per_dimm) * rank_density;
2429 } else {
2430 sa = 0;
2431 ea = 0;
2432 }
2433 break;
2434 }
2435 }
2436
2437 sa >>= 24;
2438 ea >>= 24;
2439
2440 if (cs_en) {
2441 ddr->cs[i].bnds = (0
2442 | ((sa & 0xffff) << 16) /* starting address */
2443 | ((ea & 0xffff) << 0) /* ending address */
2444 );
2445 } else {
2446 /* setting bnds to 0xffffffff for inactive CS */
2447 ddr->cs[i].bnds = 0xffffffff;
2448 }
2449
2450 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2451 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2452 set_csn_config_2(i, ddr);
2453 }
2454
2455 /*
2456 * In the case we only need to compute the ddr sdram size, we only need
2457 * to set csn registers, so return from here.
2458 */
2459 if (size_only)
2460 return 0;
2461
2462 set_ddr_eor(ddr, popts);
2463
2464 #if !defined(CONFIG_SYS_FSL_DDR1)
2465 set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
2466 #endif
2467
2468 set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
2469 additive_latency);
2470 set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2471 set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2472 cas_latency, additive_latency);
2473
2474 set_ddr_cdr1(ddr, popts);
2475 set_ddr_cdr2(ddr, popts);
2476 set_ddr_sdram_cfg(ddr, popts, common_dimm);
2477 ip_rev = fsl_ddr_get_version(ctrl_num);
2478 if (ip_rev > 0x40400)
2479 unq_mrs_en = 1;
2480
2481 if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2482 ddr->debug[18] = popts->cswl_override;
2483
2484 set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2485 set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2486 cas_latency, additive_latency, unq_mrs_en);
2487 set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2488 #ifdef CONFIG_SYS_FSL_DDR4
2489 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2490 set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2491 #endif
2492 set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
2493 set_ddr_data_init(ddr);
2494 set_ddr_sdram_clk_cntl(ddr, popts);
2495 set_ddr_init_addr(ddr);
2496 set_ddr_init_ext_addr(ddr);
2497 set_timing_cfg_4(ddr, popts);
2498 set_timing_cfg_5(ddr, cas_latency);
2499 #ifdef CONFIG_SYS_FSL_DDR4
2500 set_ddr_sdram_cfg_3(ddr, popts);
2501 set_timing_cfg_6(ddr);
2502 set_timing_cfg_7(ctrl_num, ddr, common_dimm);
2503 set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
2504 set_timing_cfg_9(ddr);
2505 set_ddr_dq_mapping(ddr, dimm_params);
2506 #endif
2507
2508 set_ddr_zq_cntl(ddr, zq_en);
2509 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2510
2511 set_ddr_sr_cntr(ddr, sr_it);
2512
2513 set_ddr_sdram_rcw(ddr, popts, common_dimm);
2514
2515 #ifdef CONFIG_SYS_FSL_DDR_EMU
2516 /* disble DDR training for emulator */
2517 ddr->debug[2] = 0x00000400;
2518 ddr->debug[4] = 0xff800800;
2519 ddr->debug[5] = 0x08000800;
2520 ddr->debug[6] = 0x08000800;
2521 ddr->debug[7] = 0x08000800;
2522 ddr->debug[8] = 0x08000800;
2523 #endif
2524 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2525 if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2526 ddr->debug[2] |= 0x00000200; /* set bit 22 */
2527 #endif
2528
2529 return check_fsl_memctl_config_regs(ddr);
2530 }
"Das U-Boot" Source Tree