2 * Copyright 2008, 2010-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fsl_ddr_sdram.h>
12 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
14 #include <asm/arch/clock.h>
18 * Use our own stack based buffer before relocation to allow accessing longer
19 * hwconfig strings that might be in the environment before we've relocated.
20 * This is pretty fragile on both the use of stack and if the buffer is big
21 * enough. However we will get a warning from getenv_f for the later.
24 /* Board-specific functions defined in each board's ddr.c */
25 extern void fsl_ddr_board_options(memctl_options_t
*popts
,
27 unsigned int ctrl_num
);
30 unsigned int odt_rd_cfg
;
31 unsigned int odt_wr_cfg
;
32 unsigned int odt_rtt_norm
;
33 unsigned int odt_rtt_wr
;
36 #ifdef CONFIG_SYS_FSL_DDR4
37 /* Quad rank is not verified yet due availability.
38 * Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option
40 static __maybe_unused
const struct dynamic_odt single_Q
[4] = {
43 FSL_DDR_ODT_CS_AND_OTHER_DIMM
,
44 DDR4_RTT_34_OHM
, /* unverified */
55 FSL_DDR_ODT_CS_AND_OTHER_DIMM
,
61 FSL_DDR_ODT_NEVER
, /* tied high */
67 static __maybe_unused
const struct dynamic_odt single_D
[4] = {
84 static __maybe_unused
const struct dynamic_odt single_S
[4] = {
96 static __maybe_unused
const struct dynamic_odt dual_DD
[4] = {
99 FSL_DDR_ODT_SAME_DIMM
,
104 FSL_DDR_ODT_OTHER_DIMM
,
105 FSL_DDR_ODT_OTHER_DIMM
,
111 FSL_DDR_ODT_SAME_DIMM
,
116 FSL_DDR_ODT_OTHER_DIMM
,
117 FSL_DDR_ODT_OTHER_DIMM
,
123 static __maybe_unused
const struct dynamic_odt dual_DS
[4] = {
126 FSL_DDR_ODT_SAME_DIMM
,
131 FSL_DDR_ODT_OTHER_DIMM
,
132 FSL_DDR_ODT_OTHER_DIMM
,
137 FSL_DDR_ODT_OTHER_DIMM
,
144 static __maybe_unused
const struct dynamic_odt dual_SD
[4] = {
146 FSL_DDR_ODT_OTHER_DIMM
,
154 FSL_DDR_ODT_SAME_DIMM
,
159 FSL_DDR_ODT_OTHER_DIMM
,
160 FSL_DDR_ODT_OTHER_DIMM
,
166 static __maybe_unused
const struct dynamic_odt dual_SS
[4] = {
168 FSL_DDR_ODT_OTHER_DIMM
,
175 FSL_DDR_ODT_OTHER_DIMM
,
183 static __maybe_unused
const struct dynamic_odt dual_D0
[4] = {
186 FSL_DDR_ODT_SAME_DIMM
,
200 static __maybe_unused
const struct dynamic_odt dual_0D
[4] = {
205 FSL_DDR_ODT_SAME_DIMM
,
217 static __maybe_unused
const struct dynamic_odt dual_S0
[4] = {
230 static __maybe_unused
const struct dynamic_odt dual_0S
[4] = {
243 static __maybe_unused
const struct dynamic_odt odt_unknown
[4] = {
269 #elif defined(CONFIG_SYS_FSL_DDR3)
270 static __maybe_unused
const struct dynamic_odt single_Q
[4] = {
273 FSL_DDR_ODT_CS_AND_OTHER_DIMM
,
279 FSL_DDR_ODT_NEVER
, /* tied high */
285 FSL_DDR_ODT_CS_AND_OTHER_DIMM
,
291 FSL_DDR_ODT_NEVER
, /* tied high */
297 static __maybe_unused
const struct dynamic_odt single_D
[4] = {
314 static __maybe_unused
const struct dynamic_odt single_S
[4] = {
326 static __maybe_unused
const struct dynamic_odt dual_DD
[4] = {
329 FSL_DDR_ODT_SAME_DIMM
,
334 FSL_DDR_ODT_OTHER_DIMM
,
335 FSL_DDR_ODT_OTHER_DIMM
,
341 FSL_DDR_ODT_SAME_DIMM
,
346 FSL_DDR_ODT_OTHER_DIMM
,
347 FSL_DDR_ODT_OTHER_DIMM
,
353 static __maybe_unused
const struct dynamic_odt dual_DS
[4] = {
356 FSL_DDR_ODT_SAME_DIMM
,
361 FSL_DDR_ODT_OTHER_DIMM
,
362 FSL_DDR_ODT_OTHER_DIMM
,
367 FSL_DDR_ODT_OTHER_DIMM
,
374 static __maybe_unused
const struct dynamic_odt dual_SD
[4] = {
376 FSL_DDR_ODT_OTHER_DIMM
,
384 FSL_DDR_ODT_SAME_DIMM
,
389 FSL_DDR_ODT_OTHER_DIMM
,
390 FSL_DDR_ODT_OTHER_DIMM
,
396 static __maybe_unused
const struct dynamic_odt dual_SS
[4] = {
398 FSL_DDR_ODT_OTHER_DIMM
,
405 FSL_DDR_ODT_OTHER_DIMM
,
413 static __maybe_unused
const struct dynamic_odt dual_D0
[4] = {
416 FSL_DDR_ODT_SAME_DIMM
,
430 static __maybe_unused
const struct dynamic_odt dual_0D
[4] = {
435 FSL_DDR_ODT_SAME_DIMM
,
447 static __maybe_unused
const struct dynamic_odt dual_S0
[4] = {
460 static __maybe_unused
const struct dynamic_odt dual_0S
[4] = {
473 static __maybe_unused
const struct dynamic_odt odt_unknown
[4] = {
499 #else /* CONFIG_SYS_FSL_DDR3 */
500 static __maybe_unused
const struct dynamic_odt single_Q
[4] = {
507 static __maybe_unused
const struct dynamic_odt single_D
[4] = {
524 static __maybe_unused
const struct dynamic_odt single_S
[4] = {
536 static __maybe_unused
const struct dynamic_odt dual_DD
[4] = {
538 FSL_DDR_ODT_OTHER_DIMM
,
539 FSL_DDR_ODT_OTHER_DIMM
,
550 FSL_DDR_ODT_OTHER_DIMM
,
551 FSL_DDR_ODT_OTHER_DIMM
,
563 static __maybe_unused
const struct dynamic_odt dual_DS
[4] = {
565 FSL_DDR_ODT_OTHER_DIMM
,
566 FSL_DDR_ODT_OTHER_DIMM
,
577 FSL_DDR_ODT_OTHER_DIMM
,
578 FSL_DDR_ODT_OTHER_DIMM
,
585 static __maybe_unused
const struct dynamic_odt dual_SD
[4] = {
587 FSL_DDR_ODT_OTHER_DIMM
,
588 FSL_DDR_ODT_OTHER_DIMM
,
594 FSL_DDR_ODT_OTHER_DIMM
,
595 FSL_DDR_ODT_OTHER_DIMM
,
607 static __maybe_unused
const struct dynamic_odt dual_SS
[4] = {
609 FSL_DDR_ODT_OTHER_DIMM
,
610 FSL_DDR_ODT_OTHER_DIMM
,
616 FSL_DDR_ODT_OTHER_DIMM
,
617 FSL_DDR_ODT_OTHER_DIMM
,
624 static __maybe_unused
const struct dynamic_odt dual_D0
[4] = {
641 static __maybe_unused
const struct dynamic_odt dual_0D
[4] = {
658 static __maybe_unused
const struct dynamic_odt dual_S0
[4] = {
671 static __maybe_unused
const struct dynamic_odt dual_0S
[4] = {
684 static __maybe_unused
const struct dynamic_odt odt_unknown
[4] = {
713 * Automatically seleect bank interleaving mode based on DIMMs
714 * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
715 * This function only deal with one or two slots per controller.
717 static inline unsigned int auto_bank_intlv(dimm_params_t
*pdimm
)
719 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
720 if (pdimm
[0].n_ranks
== 4)
721 return FSL_DDR_CS0_CS1_CS2_CS3
;
722 else if (pdimm
[0].n_ranks
== 2)
723 return FSL_DDR_CS0_CS1
;
724 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
725 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
726 if (pdimm
[0].n_ranks
== 4)
727 return FSL_DDR_CS0_CS1_CS2_CS3
;
729 if (pdimm
[0].n_ranks
== 2) {
730 if (pdimm
[1].n_ranks
== 2)
731 return FSL_DDR_CS0_CS1_CS2_CS3
;
733 return FSL_DDR_CS0_CS1
;
739 unsigned int populate_memctl_options(const common_timing_params_t
*common_dimm
,
740 memctl_options_t
*popts
,
741 dimm_params_t
*pdimm
,
742 unsigned int ctrl_num
)
745 char buffer
[HWCONFIG_BUFFER_SIZE
];
747 #if defined(CONFIG_SYS_FSL_DDR3) || \
748 defined(CONFIG_SYS_FSL_DDR2) || \
749 defined(CONFIG_SYS_FSL_DDR4)
750 const struct dynamic_odt
*pdodt
= odt_unknown
;
755 * Extract hwconfig from environment since we have not properly setup
756 * the environment but need it for ddr config params
758 if (getenv_f("hwconfig", buffer
, sizeof(buffer
)) > 0)
761 #if defined(CONFIG_SYS_FSL_DDR3) || \
762 defined(CONFIG_SYS_FSL_DDR2) || \
763 defined(CONFIG_SYS_FSL_DDR4)
764 /* Chip select options. */
765 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
766 switch (pdimm
[0].n_ranks
) {
777 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
778 switch (pdimm
[0].n_ranks
) {
779 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
782 if (pdimm
[1].n_ranks
)
783 printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n");
787 switch (pdimm
[1].n_ranks
) {
800 switch (pdimm
[1].n_ranks
) {
813 switch (pdimm
[1].n_ranks
) {
823 #endif /* CONFIG_DIMM_SLOTS_PER_CTLR */
824 #endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */
826 /* Pick chip-select local options. */
827 for (i
= 0; i
< CONFIG_CHIP_SELECTS_PER_CTRL
; i
++) {
828 #if defined(CONFIG_SYS_FSL_DDR3) || \
829 defined(CONFIG_SYS_FSL_DDR2) || \
830 defined(CONFIG_SYS_FSL_DDR4)
831 popts
->cs_local_opts
[i
].odt_rd_cfg
= pdodt
[i
].odt_rd_cfg
;
832 popts
->cs_local_opts
[i
].odt_wr_cfg
= pdodt
[i
].odt_wr_cfg
;
833 popts
->cs_local_opts
[i
].odt_rtt_norm
= pdodt
[i
].odt_rtt_norm
;
834 popts
->cs_local_opts
[i
].odt_rtt_wr
= pdodt
[i
].odt_rtt_wr
;
836 popts
->cs_local_opts
[i
].odt_rd_cfg
= FSL_DDR_ODT_NEVER
;
837 popts
->cs_local_opts
[i
].odt_wr_cfg
= FSL_DDR_ODT_CS
;
839 popts
->cs_local_opts
[i
].auto_precharge
= 0;
842 /* Pick interleaving mode. */
845 * 0 = no interleaving
846 * 1 = interleaving between 2 controllers
848 popts
->memctl_interleaving
= 0;
854 * 3 = superbank (only if CS interleaving is enabled)
856 popts
->memctl_interleaving_mode
= 0;
859 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
860 * 1: page: bit to the left of the column bits selects the memctl
861 * 2: bank: bit to the left of the bank bits selects the memctl
862 * 3: superbank: bit to the left of the chip select selects the memctl
864 * NOTE: ba_intlv (rank interleaving) is independent of memory
865 * controller interleaving; it is only within a memory controller.
866 * Must use superbank interleaving if rank interleaving is used and
867 * memory controller interleaving is enabled.
874 * 0x60 = CS0,CS1 + CS2,CS3
875 * 0x04 = CS0,CS1,CS2,CS3
877 popts
->ba_intlv_ctl
= 0;
879 /* Memory Organization Parameters */
880 popts
->registered_dimm_en
= common_dimm
->all_dimms_registered
;
882 /* Operational Mode Paramters */
885 popts
->ecc_mode
= 0; /* 0 = disabled, 1 = enabled */
886 #ifdef CONFIG_DDR_ECC
887 if (hwconfig_sub_f("fsl_ddr", "ecc", buf
)) {
888 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf
))
893 /* 1 = use memory controler to init data */
894 popts
->ecc_init_using_memctl
= popts
->ecc_mode
? 1 : 0;
901 #if defined(CONFIG_SYS_FSL_DDR1)
902 popts
->dqs_config
= 0;
903 #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
904 popts
->dqs_config
= 1;
907 /* Choose self-refresh during sleep. */
908 popts
->self_refresh_in_sleep
= 1;
910 /* Choose dynamic power management mode. */
911 popts
->dynamic_power
= 0;
914 * check first dimm for primary sdram width
915 * presuming all dimms are similar
916 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
918 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
919 if (pdimm
[0].n_ranks
!= 0) {
920 if ((pdimm
[0].data_width
>= 64) && \
921 (pdimm
[0].data_width
<= 72))
922 popts
->data_bus_width
= 0;
923 else if ((pdimm
[0].data_width
>= 32) && \
924 (pdimm
[0].data_width
<= 40))
925 popts
->data_bus_width
= 1;
927 panic("Error: data width %u is invalid!\n",
928 pdimm
[0].data_width
);
932 if (pdimm
[0].n_ranks
!= 0) {
933 if (pdimm
[0].primary_sdram_width
== 64)
934 popts
->data_bus_width
= 0;
935 else if (pdimm
[0].primary_sdram_width
== 32)
936 popts
->data_bus_width
= 1;
937 else if (pdimm
[0].primary_sdram_width
== 16)
938 popts
->data_bus_width
= 2;
940 panic("Error: primary sdram width %u is invalid!\n",
941 pdimm
[0].primary_sdram_width
);
946 popts
->x4_en
= (pdimm
[0].device_width
== 4) ? 1 : 0;
948 /* Choose burst length. */
949 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
950 #if defined(CONFIG_E500MC)
951 popts
->otf_burst_chop_en
= 0; /* on-the-fly burst chop disable */
952 popts
->burst_length
= DDR_BL8
; /* Fixed 8-beat burst len */
954 if ((popts
->data_bus_width
== 1) || (popts
->data_bus_width
== 2)) {
955 /* 32-bit or 16-bit bus */
956 popts
->otf_burst_chop_en
= 0;
957 popts
->burst_length
= DDR_BL8
;
959 popts
->otf_burst_chop_en
= 1; /* on-the-fly burst chop */
960 popts
->burst_length
= DDR_OTF
; /* on-the-fly BC4 and BL8 */
964 popts
->burst_length
= DDR_BL4
; /* has to be 4 for DDR2 */
967 /* Choose ddr controller address mirror mode */
968 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
969 for (i
= 0; i
< CONFIG_DIMM_SLOTS_PER_CTLR
; i
++) {
970 if (pdimm
[i
].n_ranks
) {
971 popts
->mirrored_dimm
= pdimm
[i
].mirrored_dimm
;
977 /* Global Timing Parameters. */
978 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num
));
980 /* Pick a caslat override. */
981 popts
->cas_latency_override
= 0;
982 popts
->cas_latency_override_value
= 3;
983 if (popts
->cas_latency_override
) {
984 debug("using caslat override value = %u\n",
985 popts
->cas_latency_override_value
);
988 /* Decide whether to use the computed derated latency */
989 popts
->use_derated_caslat
= 0;
991 /* Choose an additive latency. */
992 popts
->additive_latency_override
= 0;
993 popts
->additive_latency_override_value
= 3;
994 if (popts
->additive_latency_override
) {
995 debug("using additive latency override value = %u\n",
996 popts
->additive_latency_override_value
);
1002 * Factors to consider for 2T_EN:
1003 * - number of DIMMs installed
1004 * - number of components, number of active ranks
1005 * - how much time you want to spend playing around
1008 popts
->threet_en
= 0;
1010 /* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */
1011 if (popts
->registered_dimm_en
)
1012 popts
->ap_en
= 1; /* 0 = disable, 1 = enable */
1014 popts
->ap_en
= 0; /* disabled for DDR4 UDIMM/discrete default */
1016 if (hwconfig_sub_f("fsl_ddr", "parity", buf
)) {
1017 if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf
)) {
1018 if (popts
->registered_dimm_en
||
1019 (CONFIG_FSL_SDRAM_TYPE
== SDRAM_TYPE_DDR4
))
1025 * BSTTOPRE precharge interval
1027 * Set this to 0 for global auto precharge
1028 * The value of 0x100 has been used for DDR1, DDR2, DDR3.
1029 * It is not wrong. Any value should be OK. The performance depends on
1030 * applications. There is no one good value for all. One way to set
1031 * is to use 1/4 of refint value.
1033 popts
->bstopre
= picos_to_mclk(ctrl_num
, common_dimm
->refresh_rate_ps
)
1037 * Window for four activates -- tFAW
1039 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
1040 * FIXME: varies depending upon number of column addresses or data
1041 * FIXME: width, was considering looking at pdimm->primary_sdram_width
1043 #if defined(CONFIG_SYS_FSL_DDR1)
1044 popts
->tfaw_window_four_activates_ps
= mclk_to_picos(ctrl_num
, 1);
1046 #elif defined(CONFIG_SYS_FSL_DDR2)
1048 * x4/x8; some datasheets have 35000
1049 * x16 wide columns only? Use 50000?
1051 popts
->tfaw_window_four_activates_ps
= 37500;
1054 popts
->tfaw_window_four_activates_ps
= pdimm
[0].tfaw_ps
;
1057 popts
->wrlvl_en
= 0;
1058 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1060 * due to ddr3 dimm is fly-by topology
1061 * we suggest to enable write leveling to
1062 * meet the tQDSS under different loading.
1064 popts
->wrlvl_en
= 1;
1066 popts
->wrlvl_override
= 0;
1070 * Check interleaving configuration from environment.
1071 * Please refer to doc/README.fsl-ddr for the detail.
1073 * If memory controller interleaving is enabled, then the data
1074 * bus widths must be programmed identically for all memory controllers.
1076 * Attempt to set all controllers to the same chip select
1077 * interleaving mode. It will do a best effort to get the
1078 * requested ranks interleaved together such that the result
1079 * should be a subset of the requested configuration.
1081 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
1082 * with 256 Byte is enabled.
1084 #if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
1085 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf
))
1086 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
1091 if (pdimm
[0].n_ranks
== 0) {
1092 printf("There is no rank on CS0 for controller %d.\n", ctrl_num
);
1093 popts
->memctl_interleaving
= 0;
1096 popts
->memctl_interleaving
= 1;
1097 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
1098 popts
->memctl_interleaving_mode
= FSL_DDR_256B_INTERLEAVING
;
1099 popts
->memctl_interleaving
= 1;
1100 debug("256 Byte interleaving\n");
1103 * test null first. if CONFIG_HWCONFIG is not defined
1104 * hwconfig_arg_cmp returns non-zero
1106 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
1108 popts
->memctl_interleaving
= 0;
1109 debug("memory controller interleaving disabled.\n");
1110 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1112 "cacheline", buf
)) {
1113 popts
->memctl_interleaving_mode
=
1114 ((CONFIG_SYS_NUM_DDR_CTLRS
== 3) && ctrl_num
== 2) ?
1115 0 : FSL_DDR_CACHE_LINE_INTERLEAVING
;
1116 popts
->memctl_interleaving
=
1117 ((CONFIG_SYS_NUM_DDR_CTLRS
== 3) && ctrl_num
== 2) ?
1119 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1122 popts
->memctl_interleaving_mode
=
1123 ((CONFIG_SYS_NUM_DDR_CTLRS
== 3) && ctrl_num
== 2) ?
1124 0 : FSL_DDR_PAGE_INTERLEAVING
;
1125 popts
->memctl_interleaving
=
1126 ((CONFIG_SYS_NUM_DDR_CTLRS
== 3) && ctrl_num
== 2) ?
1128 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1131 popts
->memctl_interleaving_mode
=
1132 ((CONFIG_SYS_NUM_DDR_CTLRS
== 3) && ctrl_num
== 2) ?
1133 0 : FSL_DDR_BANK_INTERLEAVING
;
1134 popts
->memctl_interleaving
=
1135 ((CONFIG_SYS_NUM_DDR_CTLRS
== 3) && ctrl_num
== 2) ?
1137 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1139 "superbank", buf
)) {
1140 popts
->memctl_interleaving_mode
=
1141 ((CONFIG_SYS_NUM_DDR_CTLRS
== 3) && ctrl_num
== 2) ?
1142 0 : FSL_DDR_SUPERBANK_INTERLEAVING
;
1143 popts
->memctl_interleaving
=
1144 ((CONFIG_SYS_NUM_DDR_CTLRS
== 3) && ctrl_num
== 2) ?
1146 #if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
1147 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1150 popts
->memctl_interleaving_mode
=
1151 FSL_DDR_3WAY_1KB_INTERLEAVING
;
1152 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1155 popts
->memctl_interleaving_mode
=
1156 FSL_DDR_3WAY_4KB_INTERLEAVING
;
1157 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1160 popts
->memctl_interleaving_mode
=
1161 FSL_DDR_3WAY_8KB_INTERLEAVING
;
1162 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 4)
1163 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1166 popts
->memctl_interleaving_mode
=
1167 FSL_DDR_4WAY_1KB_INTERLEAVING
;
1168 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1171 popts
->memctl_interleaving_mode
=
1172 FSL_DDR_4WAY_4KB_INTERLEAVING
;
1173 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1176 popts
->memctl_interleaving_mode
=
1177 FSL_DDR_4WAY_8KB_INTERLEAVING
;
1180 popts
->memctl_interleaving
= 0;
1181 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
1183 #endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
1185 #endif /* CONFIG_SYS_NUM_DDR_CTLRS > 1 */
1186 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf
)) &&
1187 (CONFIG_CHIP_SELECTS_PER_CTRL
> 1)) {
1188 /* test null first. if CONFIG_HWCONFIG is not defined,
1189 * hwconfig_subarg_cmp_f returns non-zero */
1190 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1192 debug("bank interleaving disabled.\n");
1193 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1195 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1
;
1196 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1198 popts
->ba_intlv_ctl
= FSL_DDR_CS2_CS3
;
1199 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1200 "cs0_cs1_and_cs2_cs3", buf
))
1201 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1_AND_CS2_CS3
;
1202 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1203 "cs0_cs1_cs2_cs3", buf
))
1204 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1_CS2_CS3
;
1205 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1207 popts
->ba_intlv_ctl
= auto_bank_intlv(pdimm
);
1209 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
1210 switch (popts
->ba_intlv_ctl
& FSL_DDR_CS0_CS1_CS2_CS3
) {
1211 case FSL_DDR_CS0_CS1_CS2_CS3
:
1212 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1213 if (pdimm
[0].n_ranks
< 4) {
1214 popts
->ba_intlv_ctl
= 0;
1215 printf("Not enough bank(chip-select) for "
1216 "CS0+CS1+CS2+CS3 on controller %d, "
1217 "interleaving disabled!\n", ctrl_num
);
1219 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1220 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
1221 if (pdimm
[0].n_ranks
== 4)
1224 if ((pdimm
[0].n_ranks
< 2) && (pdimm
[1].n_ranks
< 2)) {
1225 popts
->ba_intlv_ctl
= 0;
1226 printf("Not enough bank(chip-select) for "
1227 "CS0+CS1+CS2+CS3 on controller %d, "
1228 "interleaving disabled!\n", ctrl_num
);
1230 if (pdimm
[0].capacity
!= pdimm
[1].capacity
) {
1231 popts
->ba_intlv_ctl
= 0;
1232 printf("Not identical DIMM size for "
1233 "CS0+CS1+CS2+CS3 on controller %d, "
1234 "interleaving disabled!\n", ctrl_num
);
1238 case FSL_DDR_CS0_CS1
:
1239 if (pdimm
[0].n_ranks
< 2) {
1240 popts
->ba_intlv_ctl
= 0;
1241 printf("Not enough bank(chip-select) for "
1242 "CS0+CS1 on controller %d, "
1243 "interleaving disabled!\n", ctrl_num
);
1246 case FSL_DDR_CS2_CS3
:
1247 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1248 if (pdimm
[0].n_ranks
< 4) {
1249 popts
->ba_intlv_ctl
= 0;
1250 printf("Not enough bank(chip-select) for CS2+CS3 "
1251 "on controller %d, interleaving disabled!\n", ctrl_num
);
1253 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1254 if (pdimm
[1].n_ranks
< 2) {
1255 popts
->ba_intlv_ctl
= 0;
1256 printf("Not enough bank(chip-select) for CS2+CS3 "
1257 "on controller %d, interleaving disabled!\n", ctrl_num
);
1261 case FSL_DDR_CS0_CS1_AND_CS2_CS3
:
1262 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1263 if (pdimm
[0].n_ranks
< 4) {
1264 popts
->ba_intlv_ctl
= 0;
1265 printf("Not enough bank(CS) for CS0+CS1 and "
1266 "CS2+CS3 on controller %d, "
1267 "interleaving disabled!\n", ctrl_num
);
1269 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1270 if ((pdimm
[0].n_ranks
< 2) || (pdimm
[1].n_ranks
< 2)) {
1271 popts
->ba_intlv_ctl
= 0;
1272 printf("Not enough bank(CS) for CS0+CS1 and "
1273 "CS2+CS3 on controller %d, "
1274 "interleaving disabled!\n", ctrl_num
);
1279 popts
->ba_intlv_ctl
= 0;
1284 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf
)) {
1285 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf
))
1286 popts
->addr_hash
= 0;
1287 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
1289 popts
->addr_hash
= 1;
1292 if (pdimm
[0].n_ranks
== 4)
1293 popts
->quad_rank_present
= 1;
1295 ddr_freq
= get_ddr_freq(ctrl_num
) / 1000000;
1296 if (popts
->registered_dimm_en
) {
1297 popts
->rcw_override
= 1;
1298 popts
->rcw_1
= 0x000a5a00;
1299 if (ddr_freq
<= 800)
1300 popts
->rcw_2
= 0x00000000;
1301 else if (ddr_freq
<= 1066)
1302 popts
->rcw_2
= 0x00100000;
1303 else if (ddr_freq
<= 1333)
1304 popts
->rcw_2
= 0x00200000;
1306 popts
->rcw_2
= 0x00300000;
1309 fsl_ddr_board_options(popts
, pdimm
, ctrl_num
);
1314 void check_interleaving_options(fsl_ddr_info_t
*pinfo
)
1316 int i
, j
, k
, check_n_ranks
, intlv_invalid
= 0;
1317 unsigned int check_intlv
, check_n_row_addr
, check_n_col_addr
;
1318 unsigned long long check_rank_density
;
1319 struct dimm_params_s
*dimm
;
1320 int first_ctrl
= pinfo
->first_ctrl
;
1321 int last_ctrl
= first_ctrl
+ pinfo
->num_ctrls
- 1;
1324 * Check if all controllers are configured for memory
1325 * controller interleaving. Identical dimms are recommended. At least
1326 * the size, row and col address should be checked.
1329 check_n_ranks
= pinfo
->dimm_params
[first_ctrl
][0].n_ranks
;
1330 check_rank_density
= pinfo
->dimm_params
[first_ctrl
][0].rank_density
;
1331 check_n_row_addr
= pinfo
->dimm_params
[first_ctrl
][0].n_row_addr
;
1332 check_n_col_addr
= pinfo
->dimm_params
[first_ctrl
][0].n_col_addr
;
1333 check_intlv
= pinfo
->memctl_opts
[first_ctrl
].memctl_interleaving_mode
;
1334 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
1335 dimm
= &pinfo
->dimm_params
[i
][0];
1336 if (!pinfo
->memctl_opts
[i
].memctl_interleaving
) {
1338 } else if (((check_rank_density
!= dimm
->rank_density
) ||
1339 (check_n_ranks
!= dimm
->n_ranks
) ||
1340 (check_n_row_addr
!= dimm
->n_row_addr
) ||
1341 (check_n_col_addr
!= dimm
->n_col_addr
) ||
1343 pinfo
->memctl_opts
[i
].memctl_interleaving_mode
))){
1351 if (intlv_invalid
) {
1352 for (i
= first_ctrl
; i
<= last_ctrl
; i
++)
1353 pinfo
->memctl_opts
[i
].memctl_interleaving
= 0;
1354 printf("Not all DIMMs are identical. "
1355 "Memory controller interleaving disabled.\n");
1357 switch (check_intlv
) {
1358 case FSL_DDR_256B_INTERLEAVING
:
1359 case FSL_DDR_CACHE_LINE_INTERLEAVING
:
1360 case FSL_DDR_PAGE_INTERLEAVING
:
1361 case FSL_DDR_BANK_INTERLEAVING
:
1362 case FSL_DDR_SUPERBANK_INTERLEAVING
:
1363 #if (3 == CONFIG_SYS_NUM_DDR_CTLRS)
1366 k
= CONFIG_SYS_NUM_DDR_CTLRS
;
1369 case FSL_DDR_3WAY_1KB_INTERLEAVING
:
1370 case FSL_DDR_3WAY_4KB_INTERLEAVING
:
1371 case FSL_DDR_3WAY_8KB_INTERLEAVING
:
1372 case FSL_DDR_4WAY_1KB_INTERLEAVING
:
1373 case FSL_DDR_4WAY_4KB_INTERLEAVING
:
1374 case FSL_DDR_4WAY_8KB_INTERLEAVING
:
1376 k
= CONFIG_SYS_NUM_DDR_CTLRS
;
1379 debug("%d of %d controllers are interleaving.\n", j
, k
);
1380 if (j
&& (j
!= k
)) {
1381 for (i
= first_ctrl
; i
<= last_ctrl
; i
++)
1382 pinfo
->memctl_opts
[i
].memctl_interleaving
= 0;
1383 if ((last_ctrl
- first_ctrl
) > 1)
1384 puts("Not all controllers have compatible interleaving mode. All disabled.\n");
1387 debug("Checking interleaving options completed\n");
1390 int fsl_use_spd(void)
1394 #ifdef CONFIG_DDR_SPD
1395 char buffer
[HWCONFIG_BUFFER_SIZE
];
1399 * Extract hwconfig from environment since we have not properly setup
1400 * the environment but need it for ddr config params
1402 if (getenv_f("hwconfig", buffer
, sizeof(buffer
)) > 0)
1405 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1406 if (hwconfig_sub_f("fsl_ddr", "sdram", buf
)) {
1407 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf
))
1409 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",