2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <fsl_esdhc.h>
37 #include <fdt_support.h>
40 DECLARE_GLOBAL_DATA_PTR
;
70 /* Return the XFERTYP flags for a given command and data packet */
71 static uint
esdhc_xfertyp(struct mmc_cmd
*cmd
, struct mmc_data
*data
)
76 xfertyp
|= XFERTYP_DPSEL
;
77 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
78 xfertyp
|= XFERTYP_DMAEN
;
80 if (data
->blocks
> 1) {
81 xfertyp
|= XFERTYP_MSBSEL
;
82 xfertyp
|= XFERTYP_BCEN
;
83 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
84 xfertyp
|= XFERTYP_AC12EN
;
88 if (data
->flags
& MMC_DATA_READ
)
89 xfertyp
|= XFERTYP_DTDSEL
;
92 if (cmd
->resp_type
& MMC_RSP_CRC
)
93 xfertyp
|= XFERTYP_CCCEN
;
94 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
95 xfertyp
|= XFERTYP_CICEN
;
96 if (cmd
->resp_type
& MMC_RSP_136
)
97 xfertyp
|= XFERTYP_RSPTYP_136
;
98 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
99 xfertyp
|= XFERTYP_RSPTYP_48_BUSY
;
100 else if (cmd
->resp_type
& MMC_RSP_PRESENT
)
101 xfertyp
|= XFERTYP_RSPTYP_48
;
103 #if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS)
104 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
105 xfertyp
|= XFERTYP_CMDTYP_ABORT
;
107 return XFERTYP_CMD(cmd
->cmdidx
) | xfertyp
;
110 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
112 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
115 esdhc_pio_read_write(struct mmc
*mmc
, struct mmc_data
*data
)
117 struct fsl_esdhc_cfg
*cfg
= mmc
->priv
;
118 struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
126 if (data
->flags
& MMC_DATA_READ
) {
127 blocks
= data
->blocks
;
130 timeout
= PIO_TIMEOUT
;
131 size
= data
->blocksize
;
132 irqstat
= esdhc_read32(®s
->irqstat
);
133 while (!(esdhc_read32(®s
->prsstat
) & PRSSTAT_BREN
)
136 printf("\nData Read Failed in PIO Mode.");
139 while (size
&& (!(irqstat
& IRQSTAT_TC
))) {
140 udelay(100); /* Wait before last byte transfer complete */
141 irqstat
= esdhc_read32(®s
->irqstat
);
142 databuf
= in_le32(®s
->datport
);
143 *((uint
*)buffer
) = databuf
;
150 blocks
= data
->blocks
;
151 buffer
= (char *)data
->src
;
153 timeout
= PIO_TIMEOUT
;
154 size
= data
->blocksize
;
155 irqstat
= esdhc_read32(®s
->irqstat
);
156 while (!(esdhc_read32(®s
->prsstat
) & PRSSTAT_BWEN
)
159 printf("\nData Write Failed in PIO Mode.");
162 while (size
&& (!(irqstat
& IRQSTAT_TC
))) {
163 udelay(100); /* Wait before last byte transfer complete */
164 databuf
= *((uint
*)buffer
);
167 irqstat
= esdhc_read32(®s
->irqstat
);
168 out_le32(®s
->datport
, databuf
);
176 static int esdhc_setup_data(struct mmc
*mmc
, struct mmc_data
*data
)
179 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
180 struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
181 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
184 wml_value
= data
->blocksize
/4;
186 if (data
->flags
& MMC_DATA_READ
) {
187 if (wml_value
> WML_RD_WML_MAX
)
188 wml_value
= WML_RD_WML_MAX_VAL
;
190 esdhc_clrsetbits32(®s
->wml
, WML_RD_WML_MASK
, wml_value
);
191 esdhc_write32(®s
->dsaddr
, (u32
)data
->dest
);
193 flush_dcache_range((ulong
)data
->src
,
194 (ulong
)data
->src
+data
->blocks
197 if (wml_value
> WML_WR_WML_MAX
)
198 wml_value
= WML_WR_WML_MAX_VAL
;
199 if ((esdhc_read32(®s
->prsstat
) & PRSSTAT_WPSPL
) == 0) {
200 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
204 esdhc_clrsetbits32(®s
->wml
, WML_WR_WML_MASK
,
206 esdhc_write32(®s
->dsaddr
, (u32
)data
->src
);
208 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
209 if (!(data
->flags
& MMC_DATA_READ
)) {
210 if ((esdhc_read32(®s
->prsstat
) & PRSSTAT_WPSPL
) == 0) {
211 printf("\nThe SD card is locked. "
212 "Can not write to a locked card.\n\n");
215 esdhc_write32(®s
->dsaddr
, (u32
)data
->src
);
217 esdhc_write32(®s
->dsaddr
, (u32
)data
->dest
);
218 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
220 esdhc_write32(®s
->blkattr
, data
->blocks
<< 16 | data
->blocksize
);
222 /* Calculate the timeout period for data transactions */
224 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
225 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
226 * So, Number of SD Clock cycles for 0.25sec should be minimum
227 * (SD Clock/sec * 0.25 sec) SD Clock cycles
228 * = (mmc->tran_speed * 1/4) SD Clock cycles
230 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
231 * Taking log2 both the sides
232 * => timeout + 13 >= log2(mmc->tran_speed/4)
233 * Rounding up to next power of 2
234 * => timeout + 13 = log2(mmc->tran_speed/4) + 1
235 * => timeout + 13 = fls(mmc->tran_speed/4)
237 timeout
= fls(mmc
->tran_speed
/4);
246 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
247 if ((timeout
== 4) || (timeout
== 8) || (timeout
== 12))
251 esdhc_clrsetbits32(®s
->sysctl
, SYSCTL_TIMEOUT_MASK
, timeout
<< 16);
256 static void check_and_invalidate_dcache_range
257 (struct mmc_cmd
*cmd
,
258 struct mmc_data
*data
) {
259 unsigned start
= (unsigned)data
->dest
;
260 unsigned size
= roundup(ARCH_DMA_MINALIGN
,
261 data
->blocks
*data
->blocksize
);
262 unsigned end
= start
+size
;
263 invalidate_dcache_range(start
, end
);
266 * Sends a command out on the bus. Takes the mmc pointer,
267 * a command pointer, and an optional data pointer.
270 esdhc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
, struct mmc_data
*data
)
274 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
275 volatile struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
277 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
278 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
282 esdhc_write32(®s
->irqstat
, -1);
286 /* Wait for the bus to be idle */
287 while ((esdhc_read32(®s
->prsstat
) & PRSSTAT_CICHB
) ||
288 (esdhc_read32(®s
->prsstat
) & PRSSTAT_CIDHB
))
291 while (esdhc_read32(®s
->prsstat
) & PRSSTAT_DLA
)
294 /* Wait at least 8 SD clock cycles before the next command */
296 * Note: This is way more than 8 cycles, but 1ms seems to
297 * resolve timing issues with some cards
301 /* Set up for a data transfer if we have one */
305 err
= esdhc_setup_data(mmc
, data
);
310 /* Figure out the transfer arguments */
311 xfertyp
= esdhc_xfertyp(cmd
, data
);
314 esdhc_write32(®s
->irqsigen
, 0);
316 /* Send the command */
317 esdhc_write32(®s
->cmdarg
, cmd
->cmdarg
);
318 #if defined(CONFIG_FSL_USDHC)
319 esdhc_write32(®s
->mixctrl
,
320 (esdhc_read32(®s
->mixctrl
) & 0xFFFFFF80) | (xfertyp
& 0x7F));
321 esdhc_write32(®s
->xfertyp
, xfertyp
& 0xFFFF0000);
323 esdhc_write32(®s
->xfertyp
, xfertyp
);
326 /* Wait for the command to complete */
327 while (!(esdhc_read32(®s
->irqstat
) & (IRQSTAT_CC
| IRQSTAT_CTOE
)))
330 irqstat
= esdhc_read32(®s
->irqstat
);
332 /* Reset CMD and DATA portions on error */
333 if (irqstat
& (CMD_ERR
| IRQSTAT_CTOE
)) {
334 esdhc_write32(®s
->sysctl
, esdhc_read32(®s
->sysctl
) |
336 while (esdhc_read32(®s
->sysctl
) & SYSCTL_RSTC
)
340 esdhc_write32(®s
->sysctl
,
341 esdhc_read32(®s
->sysctl
) |
343 while ((esdhc_read32(®s
->sysctl
) & SYSCTL_RSTD
))
348 if (irqstat
& CMD_ERR
)
351 if (irqstat
& IRQSTAT_CTOE
)
354 /* Workaround for ESDHC errata ENGcm03648 */
355 if (!data
&& (cmd
->resp_type
& MMC_RSP_BUSY
)) {
358 /* Poll on DATA0 line for cmd with busy signal for 250 ms */
359 while (timeout
> 0 && !(esdhc_read32(®s
->prsstat
) &
366 printf("Timeout waiting for DAT0 to go high!\n");
371 /* Copy the response to the response buffer */
372 if (cmd
->resp_type
& MMC_RSP_136
) {
373 u32 cmdrsp3
, cmdrsp2
, cmdrsp1
, cmdrsp0
;
375 cmdrsp3
= esdhc_read32(®s
->cmdrsp3
);
376 cmdrsp2
= esdhc_read32(®s
->cmdrsp2
);
377 cmdrsp1
= esdhc_read32(®s
->cmdrsp1
);
378 cmdrsp0
= esdhc_read32(®s
->cmdrsp0
);
379 cmd
->response
[0] = (cmdrsp3
<< 8) | (cmdrsp2
>> 24);
380 cmd
->response
[1] = (cmdrsp2
<< 8) | (cmdrsp1
>> 24);
381 cmd
->response
[2] = (cmdrsp1
<< 8) | (cmdrsp0
>> 24);
382 cmd
->response
[3] = (cmdrsp0
<< 8);
384 cmd
->response
[0] = esdhc_read32(®s
->cmdrsp0
);
386 /* Wait until all of the blocks are transferred */
388 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
389 esdhc_pio_read_write(mmc
, data
);
392 irqstat
= esdhc_read32(®s
->irqstat
);
394 if (irqstat
& IRQSTAT_DTOE
)
397 if (irqstat
& DATA_ERR
)
399 } while ((irqstat
& DATA_COMPLETE
) != DATA_COMPLETE
);
401 if (data
->flags
& MMC_DATA_READ
)
402 check_and_invalidate_dcache_range(cmd
, data
);
405 esdhc_write32(®s
->irqstat
, -1);
410 static void set_sysctl(struct mmc
*mmc
, uint clock
)
413 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
414 volatile struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
415 int sdhc_clk
= cfg
->sdhc_clk
;
418 if (clock
< mmc
->f_min
)
421 if (sdhc_clk
/ 16 > clock
) {
422 for (pre_div
= 2; pre_div
< 256; pre_div
*= 2)
423 if ((sdhc_clk
/ pre_div
) <= (clock
* 16))
428 for (div
= 1; div
<= 16; div
++)
429 if ((sdhc_clk
/ (div
* pre_div
)) <= clock
)
435 clk
= (pre_div
<< 8) | (div
<< 4);
437 esdhc_clrbits32(®s
->sysctl
, SYSCTL_CKEN
);
439 esdhc_clrsetbits32(®s
->sysctl
, SYSCTL_CLOCK_MASK
, clk
);
443 clk
= SYSCTL_PEREN
| SYSCTL_CKEN
;
445 esdhc_setbits32(®s
->sysctl
, clk
);
448 static void esdhc_set_ios(struct mmc
*mmc
)
450 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
451 struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
453 /* Set the clock speed */
454 set_sysctl(mmc
, mmc
->clock
);
456 /* Set the bus width */
457 esdhc_clrbits32(®s
->proctl
, PROCTL_DTW_4
| PROCTL_DTW_8
);
459 if (mmc
->bus_width
== 4)
460 esdhc_setbits32(®s
->proctl
, PROCTL_DTW_4
);
461 else if (mmc
->bus_width
== 8)
462 esdhc_setbits32(®s
->proctl
, PROCTL_DTW_8
);
466 static int esdhc_init(struct mmc
*mmc
)
468 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
469 struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
472 /* Reset the entire host controller */
473 esdhc_setbits32(®s
->sysctl
, SYSCTL_RSTA
);
475 /* Wait until the controller is available */
476 while ((esdhc_read32(®s
->sysctl
) & SYSCTL_RSTA
) && --timeout
)
480 /* Enable cache snooping */
481 esdhc_write32(®s
->scr
, 0x00000040);
484 esdhc_setbits32(®s
->sysctl
, SYSCTL_HCKEN
| SYSCTL_IPGEN
);
486 /* Set the initial clock speed */
487 mmc_set_clock(mmc
, 400000);
489 /* Disable the BRR and BWR bits in IRQSTAT */
490 esdhc_clrbits32(®s
->irqstaten
, IRQSTATEN_BRR
| IRQSTATEN_BWR
);
492 /* Put the PROCTL reg back to the default */
493 esdhc_write32(®s
->proctl
, PROCTL_INIT
);
495 /* Set timout to the maximum value */
496 esdhc_clrsetbits32(®s
->sysctl
, SYSCTL_TIMEOUT_MASK
, 14 << 16);
501 static int esdhc_getcd(struct mmc
*mmc
)
503 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
504 struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
507 while (!(esdhc_read32(®s
->prsstat
) & PRSSTAT_CINS
) && --timeout
)
513 static void esdhc_reset(struct fsl_esdhc
*regs
)
515 unsigned long timeout
= 100; /* wait max 100 ms */
517 /* reset the controller */
518 esdhc_setbits32(®s
->sysctl
, SYSCTL_RSTA
);
520 /* hardware clears the bit when it is done */
521 while ((esdhc_read32(®s
->sysctl
) & SYSCTL_RSTA
) && --timeout
)
524 printf("MMC/SD: Reset never completed.\n");
527 int fsl_esdhc_initialize(bd_t
*bis
, struct fsl_esdhc_cfg
*cfg
)
529 struct fsl_esdhc
*regs
;
531 u32 caps
, voltage_caps
;
536 mmc
= malloc(sizeof(struct mmc
));
538 sprintf(mmc
->name
, "FSL_SDHC");
539 regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
541 /* First reset the eSDHC controller */
544 esdhc_setbits32(®s
->sysctl
, SYSCTL_PEREN
| SYSCTL_HCKEN
545 | SYSCTL_IPGEN
| SYSCTL_CKEN
);
548 mmc
->send_cmd
= esdhc_send_cmd
;
549 mmc
->set_ios
= esdhc_set_ios
;
550 mmc
->init
= esdhc_init
;
551 mmc
->getcd
= esdhc_getcd
;
555 caps
= regs
->hostcapblt
;
557 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
558 caps
= caps
& ~(ESDHC_HOSTCAPBLT_SRS
|
559 ESDHC_HOSTCAPBLT_VS18
| ESDHC_HOSTCAPBLT_VS30
);
561 if (caps
& ESDHC_HOSTCAPBLT_VS18
)
562 voltage_caps
|= MMC_VDD_165_195
;
563 if (caps
& ESDHC_HOSTCAPBLT_VS30
)
564 voltage_caps
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
565 if (caps
& ESDHC_HOSTCAPBLT_VS33
)
566 voltage_caps
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
568 #ifdef CONFIG_SYS_SD_VOLTAGE
569 mmc
->voltages
= CONFIG_SYS_SD_VOLTAGE
;
571 mmc
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
573 if ((mmc
->voltages
& voltage_caps
) == 0) {
574 printf("voltage not supported by controller\n");
578 mmc
->host_caps
= MMC_MODE_4BIT
| MMC_MODE_8BIT
| MMC_MODE_HC
;
580 if (cfg
->max_bus_width
> 0) {
581 if (cfg
->max_bus_width
< 8)
582 mmc
->host_caps
&= ~MMC_MODE_8BIT
;
583 if (cfg
->max_bus_width
< 4)
584 mmc
->host_caps
&= ~MMC_MODE_4BIT
;
587 if (caps
& ESDHC_HOSTCAPBLT_HSS
)
588 mmc
->host_caps
|= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
591 mmc
->f_max
= MIN(gd
->arch
.sdhc_clk
, 52000000);
599 int fsl_esdhc_mmc_init(bd_t
*bis
)
601 struct fsl_esdhc_cfg
*cfg
;
603 cfg
= calloc(sizeof(struct fsl_esdhc_cfg
), 1);
604 cfg
->esdhc_base
= CONFIG_SYS_FSL_ESDHC_ADDR
;
605 cfg
->sdhc_clk
= gd
->arch
.sdhc_clk
;
606 return fsl_esdhc_initialize(bis
, cfg
);
609 #ifdef CONFIG_OF_LIBFDT
610 void fdt_fixup_esdhc(void *blob
, bd_t
*bd
)
612 const char *compat
= "fsl,esdhc";
614 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
615 if (!hwconfig("esdhc")) {
616 do_fixup_by_compat(blob
, compat
, "status", "disabled",
622 do_fixup_by_compat_u32(blob
, compat
, "clock-frequency",
623 gd
->arch
.sdhc_clk
, 1);
625 do_fixup_by_compat(blob
, compat
, "status", "okay",