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[people/ms/u-boot.git] / drivers / net / e1000.h
1 /*******************************************************************************
2
3
4 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
5 Copyright 2011 Freescale Semiconductor, Inc.
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2 of the License, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 more details.
16
17 You should have received a copy of the GNU General Public License along with
18 this program; if not, write to the Free Software Foundation, Inc., 59
19 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20
21 The full GNU General Public License is included in this distribution in the
22 file called LICENSE.
23
24 Contact Information:
25 Linux NICS <linux.nics@intel.com>
26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27
28 *******************************************************************************/
29
30 /* e1000_hw.h
31 * Structures, enums, and macros for the MAC
32 */
33
34 #ifndef _E1000_HW_H_
35 #define _E1000_HW_H_
36
37 #include <common.h>
38 #include <linux/list.h>
39 #include <malloc.h>
40 #include <net.h>
41 #include <netdev.h>
42 #include <asm/io.h>
43 #include <pci.h>
44
45 #ifdef CONFIG_E1000_SPI
46 #include <spi.h>
47 #endif
48
49 #define E1000_ERR(NIC, fmt, args...) \
50 printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args)
51
52 #ifdef E1000_DEBUG
53 #define E1000_DBG(NIC, fmt, args...) \
54 printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args)
55 #define DEBUGOUT(fmt, args...) printf(fmt ,##args)
56 #define DEBUGFUNC() printf("%s\n", __func__);
57 #else
58 #define E1000_DBG(HW, args...) do { } while (0)
59 #define DEBUGFUNC() do { } while (0)
60 #define DEBUGOUT(fmt, args...) do { } while (0)
61 #endif
62
63 /* I/O wrapper functions */
64 #define E1000_WRITE_REG(a, reg, value) \
65 writel((value), ((a)->hw_addr + E1000_##reg))
66 #define E1000_READ_REG(a, reg) \
67 readl((a)->hw_addr + E1000_##reg)
68 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
69 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))
70 #define E1000_READ_REG_ARRAY(a, reg, offset) \
71 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))
72 #define E1000_WRITE_FLUSH(a) \
73 do { E1000_READ_REG(a, STATUS); } while (0)
74
75 /* Forward declarations of structures used by the shared code */
76 struct e1000_hw;
77 struct e1000_hw_stats;
78
79 /* Internal E1000 helper functions */
80 struct e1000_hw *e1000_find_card(unsigned int cardnum);
81 int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
82 void e1000_standby_eeprom(struct e1000_hw *hw);
83 void e1000_release_eeprom(struct e1000_hw *hw);
84 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
85 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
86
87 #ifdef CONFIG_E1000_SPI
88 int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
89 int argc, char * const argv[]);
90 #endif
91
92 /* Enumerated types specific to the e1000 hardware */
93 /* Media Access Controlers */
94 typedef enum {
95 e1000_undefined = 0,
96 e1000_82542_rev2_0,
97 e1000_82542_rev2_1,
98 e1000_82543,
99 e1000_82544,
100 e1000_82540,
101 e1000_82545,
102 e1000_82545_rev_3,
103 e1000_82546,
104 e1000_82546_rev_3,
105 e1000_82541,
106 e1000_82541_rev_2,
107 e1000_82547,
108 e1000_82547_rev_2,
109 e1000_82571,
110 e1000_82572,
111 e1000_82573,
112 e1000_82574,
113 e1000_80003es2lan,
114 e1000_ich8lan,
115 e1000_num_macs
116 } e1000_mac_type;
117
118 /* Media Types */
119 typedef enum {
120 e1000_media_type_copper = 0,
121 e1000_media_type_fiber = 1,
122 e1000_media_type_internal_serdes = 2,
123 e1000_num_media_types
124 } e1000_media_type;
125
126 typedef enum {
127 e1000_eeprom_uninitialized = 0,
128 e1000_eeprom_spi,
129 e1000_eeprom_microwire,
130 e1000_eeprom_flash,
131 e1000_eeprom_ich8,
132 e1000_eeprom_none, /* No NVM support */
133 e1000_num_eeprom_types
134 } e1000_eeprom_type;
135
136 typedef enum {
137 e1000_10_half = 0,
138 e1000_10_full = 1,
139 e1000_100_half = 2,
140 e1000_100_full = 3
141 } e1000_speed_duplex_type;
142
143 /* Flow Control Settings */
144 typedef enum {
145 e1000_fc_none = 0,
146 e1000_fc_rx_pause = 1,
147 e1000_fc_tx_pause = 2,
148 e1000_fc_full = 3,
149 e1000_fc_default = 0xFF
150 } e1000_fc_type;
151
152 /* PCI bus types */
153 typedef enum {
154 e1000_bus_type_unknown = 0,
155 e1000_bus_type_pci,
156 e1000_bus_type_pcix,
157 e1000_bus_type_pci_express,
158 e1000_bus_type_reserved
159 } e1000_bus_type;
160
161 /* PCI bus speeds */
162 typedef enum {
163 e1000_bus_speed_unknown = 0,
164 e1000_bus_speed_33,
165 e1000_bus_speed_66,
166 e1000_bus_speed_100,
167 e1000_bus_speed_133,
168 e1000_bus_speed_reserved
169 } e1000_bus_speed;
170
171 /* PCI bus widths */
172 typedef enum {
173 e1000_bus_width_unknown = 0,
174 e1000_bus_width_32,
175 e1000_bus_width_64
176 } e1000_bus_width;
177
178 /* PHY status info structure and supporting enums */
179 typedef enum {
180 e1000_cable_length_50 = 0,
181 e1000_cable_length_50_80,
182 e1000_cable_length_80_110,
183 e1000_cable_length_110_140,
184 e1000_cable_length_140,
185 e1000_cable_length_undefined = 0xFF
186 } e1000_cable_length;
187
188 typedef enum {
189 e1000_10bt_ext_dist_enable_normal = 0,
190 e1000_10bt_ext_dist_enable_lower,
191 e1000_10bt_ext_dist_enable_undefined = 0xFF
192 } e1000_10bt_ext_dist_enable;
193
194 typedef enum {
195 e1000_rev_polarity_normal = 0,
196 e1000_rev_polarity_reversed,
197 e1000_rev_polarity_undefined = 0xFF
198 } e1000_rev_polarity;
199
200 typedef enum {
201 e1000_polarity_reversal_enabled = 0,
202 e1000_polarity_reversal_disabled,
203 e1000_polarity_reversal_undefined = 0xFF
204 } e1000_polarity_reversal;
205
206 typedef enum {
207 e1000_auto_x_mode_manual_mdi = 0,
208 e1000_auto_x_mode_manual_mdix,
209 e1000_auto_x_mode_auto1,
210 e1000_auto_x_mode_auto2,
211 e1000_auto_x_mode_undefined = 0xFF
212 } e1000_auto_x_mode;
213
214 typedef enum {
215 e1000_1000t_rx_status_not_ok = 0,
216 e1000_1000t_rx_status_ok,
217 e1000_1000t_rx_status_undefined = 0xFF
218 } e1000_1000t_rx_status;
219
220 typedef enum {
221 e1000_phy_m88 = 0,
222 e1000_phy_igp,
223 e1000_phy_igp_2,
224 e1000_phy_gg82563,
225 e1000_phy_igp_3,
226 e1000_phy_ife,
227 e1000_phy_bm,
228 e1000_phy_undefined = 0xFF
229 } e1000_phy_type;
230
231 struct e1000_phy_info {
232 e1000_cable_length cable_length;
233 e1000_10bt_ext_dist_enable extended_10bt_distance;
234 e1000_rev_polarity cable_polarity;
235 e1000_polarity_reversal polarity_correction;
236 e1000_auto_x_mode mdix_mode;
237 e1000_1000t_rx_status local_rx;
238 e1000_1000t_rx_status remote_rx;
239 };
240
241 struct e1000_phy_stats {
242 uint32_t idle_errors;
243 uint32_t receive_errors;
244 };
245
246 /* Error Codes */
247 #define E1000_SUCCESS 0
248 #define E1000_ERR_EEPROM 1
249 #define E1000_ERR_PHY 2
250 #define E1000_ERR_CONFIG 3
251 #define E1000_ERR_PARAM 4
252 #define E1000_ERR_MAC_TYPE 5
253 #define E1000_ERR_PHY_TYPE 6
254 #define E1000_ERR_NOLINK 7
255 #define E1000_ERR_TIMEOUT 8
256 #define E1000_ERR_RESET 9
257 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
258 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
259 #define E1000_BLK_PHY_RESET 12
260 #define E1000_ERR_SWFW_SYNC 13
261
262 /* PCI Device IDs */
263 #define E1000_DEV_ID_82542 0x1000
264 #define E1000_DEV_ID_82543GC_FIBER 0x1001
265 #define E1000_DEV_ID_82543GC_COPPER 0x1004
266 #define E1000_DEV_ID_82544EI_COPPER 0x1008
267 #define E1000_DEV_ID_82544EI_FIBER 0x1009
268 #define E1000_DEV_ID_82544GC_COPPER 0x100C
269 #define E1000_DEV_ID_82544GC_LOM 0x100D
270 #define E1000_DEV_ID_82540EM 0x100E
271 #define E1000_DEV_ID_82540EM_LOM 0x1015
272 #define E1000_DEV_ID_82540EP_LOM 0x1016
273 #define E1000_DEV_ID_82540EP 0x1017
274 #define E1000_DEV_ID_82540EP_LP 0x101E
275 #define E1000_DEV_ID_82545EM_COPPER 0x100F
276 #define E1000_DEV_ID_82545EM_FIBER 0x1011
277 #define E1000_DEV_ID_82545GM_COPPER 0x1026
278 #define E1000_DEV_ID_82545GM_FIBER 0x1027
279 #define E1000_DEV_ID_82545GM_SERDES 0x1028
280 #define E1000_DEV_ID_82546EB_COPPER 0x1010
281 #define E1000_DEV_ID_82546EB_FIBER 0x1012
282 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
283 #define E1000_DEV_ID_82541EI 0x1013
284 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
285 #define E1000_DEV_ID_82541ER_LOM 0x1014
286 #define E1000_DEV_ID_82541ER 0x1078
287 #define E1000_DEV_ID_82547GI 0x1075
288 #define E1000_DEV_ID_82541GI 0x1076
289 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
290 #define E1000_DEV_ID_82541GI_LF 0x107C
291 #define E1000_DEV_ID_82546GB_COPPER 0x1079
292 #define E1000_DEV_ID_82546GB_FIBER 0x107A
293 #define E1000_DEV_ID_82546GB_SERDES 0x107B
294 #define E1000_DEV_ID_82546GB_PCIE 0x108A
295 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
296 #define E1000_DEV_ID_82547EI 0x1019
297 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
298 #define E1000_DEV_ID_82571EB_COPPER 0x105E
299 #define E1000_DEV_ID_82571EB_FIBER 0x105F
300 #define E1000_DEV_ID_82571EB_SERDES 0x1060
301 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
302 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
303 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
304 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
305 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
306 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
307 #define E1000_DEV_ID_82572EI_COPPER 0x107D
308 #define E1000_DEV_ID_82572EI_FIBER 0x107E
309 #define E1000_DEV_ID_82572EI_SERDES 0x107F
310 #define E1000_DEV_ID_82572EI 0x10B9
311 #define E1000_DEV_ID_82573E 0x108B
312 #define E1000_DEV_ID_82573E_IAMT 0x108C
313 #define E1000_DEV_ID_82573L 0x109A
314 #define E1000_DEV_ID_82574L 0x10D3
315 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
316 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
317 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
318 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
319 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
320
321 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
322 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
323 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
324 #define E1000_DEV_ID_ICH8_IFE 0x104C
325 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
326 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
327 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
328
329 #define IGP03E1000_E_PHY_ID 0x02A80390
330 #define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
331 #define IFE_PLUS_E_PHY_ID 0x02A80320
332 #define IFE_C_E_PHY_ID 0x02A80310
333
334 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status,
335 Control and Address */
336 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special
337 control register */
338 #define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive false
339 Carrier Counter */
340 #define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet
341 Counter */
342 #define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error
343 Frame Counter */
344 #define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error
345 Counter */
346 #define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive
347 Premature End Of Frame
348 Error Counter */
349 #define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of
350 Frame Error Counter */
351 #define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber
352 Detect Counter */
353 #define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and
354 Status */
355 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and
356 LED configuration */
357 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
358 #define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control
359 (HWI) */
360
361 #define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto
362 reduced power down */
363 #define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power
364 state of 100BASE-TX */
365 #define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power
366 state of 10BASE-T */
367 #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T
368 polarity */
369 #define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY
370 address */
371 #define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed
372 result 1=100Mbs, 0=10Mbs */
373 #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation
374 duplex result 1=Full, 0=Half */
375 #define IFE_PESC_POLARITY_REVERSED_SHIFT 8
376
377 #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down
378 disabled */
379 #define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity,
380 0=Normal */
381 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity
382 Disabled, 0=Enabled */
383 #define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled,
384 0=Normal Jabber Operation */
385 #define IFE_PSC_FORCE_POLARITY_SHIFT 5
386 #define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
387
388 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X
389 feature, default 0=disabled */
390 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X,
391 0=force MDI */
392 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
393 #define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm
394 is completed */
395 #define IFE_PMC_MDIX_MODE_SHIFT 6
396 #define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
397
398 #define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI
399 feature */
400 #define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed,
401 0=failed */
402 #define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses
403 on the wire */
404 #define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
405 #define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
406 #define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication
407 type of problem on the line */
408 #define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to
409 the cable problem, in 80cm granularity */
410 #define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
411 #define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
412 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2
413 off */
414 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
415
416
417 #define NUM_DEV_IDS 16
418
419 #define NODE_ADDRESS_SIZE 6
420 #define ETH_LENGTH_OF_ADDRESS 6
421
422 /* MAC decode size is 128K - This is the size of BAR0 */
423 #define MAC_DECODE_SIZE (128 * 1024)
424
425 #define E1000_82542_2_0_REV_ID 2
426 #define E1000_82542_2_1_REV_ID 3
427 #define E1000_REVISION_0 0
428 #define E1000_REVISION_1 1
429 #define E1000_REVISION_2 2
430 #define E1000_REVISION_3 3
431
432 #define SPEED_10 10
433 #define SPEED_100 100
434 #define SPEED_1000 1000
435 #define HALF_DUPLEX 1
436 #define FULL_DUPLEX 2
437
438 /* The sizes (in bytes) of a ethernet packet */
439 #define ENET_HEADER_SIZE 14
440 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
441 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
442 #define ETHERNET_FCS_SIZE 4
443 #define MAXIMUM_ETHERNET_PACKET_SIZE \
444 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
445 #define MINIMUM_ETHERNET_PACKET_SIZE \
446 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
447 #define CRC_LENGTH ETHERNET_FCS_SIZE
448 #define MAX_JUMBO_FRAME_SIZE 0x3F00
449
450 /* 802.1q VLAN Packet Sizes */
451 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
452
453 /* Ethertype field values */
454 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
455 #define ETHERNET_IP_TYPE 0x0800 /* IP packets */
456 #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
457
458 /* Packet Header defines */
459 #define IP_PROTOCOL_TCP 6
460 #define IP_PROTOCOL_UDP 0x11
461
462 /* This defines the bits that are set in the Interrupt Mask
463 * Set/Read Register. Each bit is documented below:
464 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
465 * o RXSEQ = Receive Sequence Error
466 */
467 #define POLL_IMS_ENABLE_MASK ( \
468 E1000_IMS_RXDMT0 | \
469 E1000_IMS_RXSEQ)
470
471 /* This defines the bits that are set in the Interrupt Mask
472 * Set/Read Register. Each bit is documented below:
473 * o RXT0 = Receiver Timer Interrupt (ring 0)
474 * o TXDW = Transmit Descriptor Written Back
475 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
476 * o RXSEQ = Receive Sequence Error
477 * o LSC = Link Status Change
478 */
479 #define IMS_ENABLE_MASK ( \
480 E1000_IMS_RXT0 | \
481 E1000_IMS_TXDW | \
482 E1000_IMS_RXDMT0 | \
483 E1000_IMS_RXSEQ | \
484 E1000_IMS_LSC)
485
486 /* The number of high/low register pairs in the RAR. The RAR (Receive Address
487 * Registers) holds the directed and multicast addresses that we monitor. We
488 * reserve one of these spots for our directed address, allowing us room for
489 * E1000_RAR_ENTRIES - 1 multicast addresses.
490 */
491 #define E1000_RAR_ENTRIES 16
492
493 #define MIN_NUMBER_OF_DESCRIPTORS 8
494 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
495
496 /* Receive Descriptor */
497 struct e1000_rx_desc {
498 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
499 uint16_t length; /* Length of data DMAed into data buffer */
500 uint16_t csum; /* Packet checksum */
501 uint8_t status; /* Descriptor status */
502 uint8_t errors; /* Descriptor Errors */
503 uint16_t special;
504 };
505
506 /* Receive Decriptor bit definitions */
507 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
508 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
509 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
510 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
511 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
512 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
513 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
514 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
515 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
516 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
517 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
518 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
519 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
520 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
521 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
522 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
523 #define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
524 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
525 #define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */
526
527 /* mask to determine if packets should be dropped due to frame errors */
528 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
529 E1000_RXD_ERR_CE | \
530 E1000_RXD_ERR_SE | \
531 E1000_RXD_ERR_SEQ | \
532 E1000_RXD_ERR_CXE | \
533 E1000_RXD_ERR_RXE)
534
535 /* Transmit Descriptor */
536 struct e1000_tx_desc {
537 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
538 union {
539 uint32_t data;
540 struct {
541 uint16_t length; /* Data buffer length */
542 uint8_t cso; /* Checksum offset */
543 uint8_t cmd; /* Descriptor control */
544 } flags;
545 } lower;
546 union {
547 uint32_t data;
548 struct {
549 uint8_t status; /* Descriptor status */
550 uint8_t css; /* Checksum start */
551 uint16_t special;
552 } fields;
553 } upper;
554 };
555
556 /* Transmit Descriptor bit definitions */
557 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
558 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
559 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
560 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
561 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
562 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
563 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
564 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
565 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
566 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
567 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
568 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
569 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
570 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
571 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
572 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
573 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
574 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
575 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
576 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
577
578 /* Offload Context Descriptor */
579 struct e1000_context_desc {
580 union {
581 uint32_t ip_config;
582 struct {
583 uint8_t ipcss; /* IP checksum start */
584 uint8_t ipcso; /* IP checksum offset */
585 uint16_t ipcse; /* IP checksum end */
586 } ip_fields;
587 } lower_setup;
588 union {
589 uint32_t tcp_config;
590 struct {
591 uint8_t tucss; /* TCP checksum start */
592 uint8_t tucso; /* TCP checksum offset */
593 uint16_t tucse; /* TCP checksum end */
594 } tcp_fields;
595 } upper_setup;
596 uint32_t cmd_and_length; /* */
597 union {
598 uint32_t data;
599 struct {
600 uint8_t status; /* Descriptor status */
601 uint8_t hdr_len; /* Header length */
602 uint16_t mss; /* Maximum segment size */
603 } fields;
604 } tcp_seg_setup;
605 };
606
607 /* Offload data descriptor */
608 struct e1000_data_desc {
609 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
610 union {
611 uint32_t data;
612 struct {
613 uint16_t length; /* Data buffer length */
614 uint8_t typ_len_ext; /* */
615 uint8_t cmd; /* */
616 } flags;
617 } lower;
618 union {
619 uint32_t data;
620 struct {
621 uint8_t status; /* Descriptor status */
622 uint8_t popts; /* Packet Options */
623 uint16_t special; /* */
624 } fields;
625 } upper;
626 };
627
628 /* Filters */
629 #define E1000_NUM_UNICAST 16 /* Unicast filter entries */
630 #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
631 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
632
633 /* Receive Address Register */
634 struct e1000_rar {
635 volatile uint32_t low; /* receive address low */
636 volatile uint32_t high; /* receive address high */
637 };
638
639 /* The number of entries in the Multicast Table Array (MTA). */
640 #define E1000_NUM_MTA_REGISTERS 128
641
642 /* IPv4 Address Table Entry */
643 struct e1000_ipv4_at_entry {
644 volatile uint32_t ipv4_addr; /* IP Address (RW) */
645 volatile uint32_t reserved;
646 };
647
648 /* Four wakeup IP addresses are supported */
649 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
650 #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
651 #define E1000_IP6AT_SIZE 1
652
653 /* IPv6 Address Table Entry */
654 struct e1000_ipv6_at_entry {
655 volatile uint8_t ipv6_addr[16];
656 };
657
658 /* Flexible Filter Length Table Entry */
659 struct e1000_fflt_entry {
660 volatile uint32_t length; /* Flexible Filter Length (RW) */
661 volatile uint32_t reserved;
662 };
663
664 /* Flexible Filter Mask Table Entry */
665 struct e1000_ffmt_entry {
666 volatile uint32_t mask; /* Flexible Filter Mask (RW) */
667 volatile uint32_t reserved;
668 };
669
670 /* Flexible Filter Value Table Entry */
671 struct e1000_ffvt_entry {
672 volatile uint32_t value; /* Flexible Filter Value (RW) */
673 volatile uint32_t reserved;
674 };
675
676 /* Four Flexible Filters are supported */
677 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
678
679 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
680 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
681
682 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
683 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
684 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
685
686 /* Register Set. (82543, 82544)
687 *
688 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
689 * These registers are physically located on the NIC, but are mapped into the
690 * host memory address space.
691 *
692 * RW - register is both readable and writable
693 * RO - register is read only
694 * WO - register is write only
695 * R/clr - register is read only and is cleared when read
696 * A - register array
697 */
698 #define E1000_CTRL 0x00000 /* Device Control - RW */
699 #define E1000_STATUS 0x00008 /* Device Status - RO */
700 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
701 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
702 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
703 #define E1000_MDIC 0x00020 /* MDI Control - RW */
704 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
705 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
706 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
707 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
708 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
709 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
710 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
711 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
712 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
713 #define E1000_RCTL 0x00100 /* RX Control - RW */
714 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
715 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
716 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
717 #define E1000_TCTL 0x00400 /* TX Control - RW */
718 #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
719 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
720 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */
721 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
722 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
723 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
724 #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
725 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
726 #define FEXTNVM_SW_CONFIG 0x0001
727 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
728 #define E1000_PBS 0x01008 /* Packet Buffer Size */
729 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
730 #define E1000_FLASH_UPDATES 1000
731 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
732 #define E1000_FLASHT 0x01028 /* FLASH Timer Register */
733 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
734 #define E1000_FLSWCTL 0x01030 /* FLASH control register */
735 #define E1000_FLSWDATA 0x01034 /* FLASH data register */
736 #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
737 #define E1000_FLOP 0x0103C /* FLASH Opcode Register */
738 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
739 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
740 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
741 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
742 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
743 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
744 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
745 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
746 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
747 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
748 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
749 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
750 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
751 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
752 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
753 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
754 #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
755 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
756 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
757 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
758 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
759 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
760 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
761 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
762 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
763 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
764 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
765 #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
766 #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
767 #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
768 #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
769 #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
770 #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
771 #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
772 #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
773 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
774 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
775 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
776 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
777 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
778 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
779 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
780 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
781 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
782 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
783 #define E1000_DC 0x04030 /* Defer Count - R/clr */
784 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
785 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
786 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
787 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
788 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
789 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
790 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
791 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
792 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
793 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
794 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
795 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
796 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
797 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
798 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
799 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
800 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
801 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
802 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
803 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
804 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
805 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
806 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
807 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
808 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
809 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
810 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
811 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
812 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
813 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
814 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
815 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
816 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
817 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
818 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
819 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
820 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
821 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
822 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
823 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
824 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
825 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
826 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
827 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
828 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
829 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
830 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
831 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
832 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
833 #define E1000_RA 0x05400 /* Receive Address - RW Array */
834 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
835 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
836 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
837 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
838 #define E1000_MANC 0x05820 /* Management Control - RW */
839 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
840 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
841 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
842 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
843 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
844 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
845 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
846 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
847
848 /* Register Set (82542)
849 *
850 * Some of the 82542 registers are located at different offsets than they are
851 * in more current versions of the 8254x. Despite the difference in location,
852 * the registers function in the same manner.
853 */
854 #define E1000_82542_CTRL E1000_CTRL
855 #define E1000_82542_STATUS E1000_STATUS
856 #define E1000_82542_EECD E1000_EECD
857 #define E1000_82542_EERD E1000_EERD
858 #define E1000_82542_CTRL_EXT E1000_CTRL_EXT
859 #define E1000_82542_MDIC E1000_MDIC
860 #define E1000_82542_FCAL E1000_FCAL
861 #define E1000_82542_FCAH E1000_FCAH
862 #define E1000_82542_FCT E1000_FCT
863 #define E1000_82542_VET E1000_VET
864 #define E1000_82542_RA 0x00040
865 #define E1000_82542_ICR E1000_ICR
866 #define E1000_82542_ITR E1000_ITR
867 #define E1000_82542_ICS E1000_ICS
868 #define E1000_82542_IMS E1000_IMS
869 #define E1000_82542_IMC E1000_IMC
870 #define E1000_82542_RCTL E1000_RCTL
871 #define E1000_82542_RDTR 0x00108
872 #define E1000_82542_RDBAL 0x00110
873 #define E1000_82542_RDBAH 0x00114
874 #define E1000_82542_RDLEN 0x00118
875 #define E1000_82542_RDH 0x00120
876 #define E1000_82542_RDT 0x00128
877 #define E1000_82542_FCRTH 0x00160
878 #define E1000_82542_FCRTL 0x00168
879 #define E1000_82542_FCTTV E1000_FCTTV
880 #define E1000_82542_TXCW E1000_TXCW
881 #define E1000_82542_RXCW E1000_RXCW
882 #define E1000_82542_MTA 0x00200
883 #define E1000_82542_TCTL E1000_TCTL
884 #define E1000_82542_TIPG E1000_TIPG
885 #define E1000_82542_TDBAL 0x00420
886 #define E1000_82542_TDBAH 0x00424
887 #define E1000_82542_TDLEN 0x00428
888 #define E1000_82542_TDH 0x00430
889 #define E1000_82542_TDT 0x00438
890 #define E1000_82542_TIDV 0x00440
891 #define E1000_82542_TBT E1000_TBT
892 #define E1000_82542_AIT E1000_AIT
893 #define E1000_82542_VFTA 0x00600
894 #define E1000_82542_LEDCTL E1000_LEDCTL
895 #define E1000_82542_PBA E1000_PBA
896 #define E1000_82542_RXDCTL E1000_RXDCTL
897 #define E1000_82542_RADV E1000_RADV
898 #define E1000_82542_RSRPD E1000_RSRPD
899 #define E1000_82542_TXDMAC E1000_TXDMAC
900 #define E1000_82542_TXDCTL E1000_TXDCTL
901 #define E1000_82542_TADV E1000_TADV
902 #define E1000_82542_TSPMT E1000_TSPMT
903 #define E1000_82542_CRCERRS E1000_CRCERRS
904 #define E1000_82542_ALGNERRC E1000_ALGNERRC
905 #define E1000_82542_SYMERRS E1000_SYMERRS
906 #define E1000_82542_RXERRC E1000_RXERRC
907 #define E1000_82542_MPC E1000_MPC
908 #define E1000_82542_SCC E1000_SCC
909 #define E1000_82542_ECOL E1000_ECOL
910 #define E1000_82542_MCC E1000_MCC
911 #define E1000_82542_LATECOL E1000_LATECOL
912 #define E1000_82542_COLC E1000_COLC
913 #define E1000_82542_DC E1000_DC
914 #define E1000_82542_TNCRS E1000_TNCRS
915 #define E1000_82542_SEC E1000_SEC
916 #define E1000_82542_CEXTERR E1000_CEXTERR
917 #define E1000_82542_RLEC E1000_RLEC
918 #define E1000_82542_XONRXC E1000_XONRXC
919 #define E1000_82542_XONTXC E1000_XONTXC
920 #define E1000_82542_XOFFRXC E1000_XOFFRXC
921 #define E1000_82542_XOFFTXC E1000_XOFFTXC
922 #define E1000_82542_FCRUC E1000_FCRUC
923 #define E1000_82542_PRC64 E1000_PRC64
924 #define E1000_82542_PRC127 E1000_PRC127
925 #define E1000_82542_PRC255 E1000_PRC255
926 #define E1000_82542_PRC511 E1000_PRC511
927 #define E1000_82542_PRC1023 E1000_PRC1023
928 #define E1000_82542_PRC1522 E1000_PRC1522
929 #define E1000_82542_GPRC E1000_GPRC
930 #define E1000_82542_BPRC E1000_BPRC
931 #define E1000_82542_MPRC E1000_MPRC
932 #define E1000_82542_GPTC E1000_GPTC
933 #define E1000_82542_GORCL E1000_GORCL
934 #define E1000_82542_GORCH E1000_GORCH
935 #define E1000_82542_GOTCL E1000_GOTCL
936 #define E1000_82542_GOTCH E1000_GOTCH
937 #define E1000_82542_RNBC E1000_RNBC
938 #define E1000_82542_RUC E1000_RUC
939 #define E1000_82542_RFC E1000_RFC
940 #define E1000_82542_ROC E1000_ROC
941 #define E1000_82542_RJC E1000_RJC
942 #define E1000_82542_MGTPRC E1000_MGTPRC
943 #define E1000_82542_MGTPDC E1000_MGTPDC
944 #define E1000_82542_MGTPTC E1000_MGTPTC
945 #define E1000_82542_TORL E1000_TORL
946 #define E1000_82542_TORH E1000_TORH
947 #define E1000_82542_TOTL E1000_TOTL
948 #define E1000_82542_TOTH E1000_TOTH
949 #define E1000_82542_TPR E1000_TPR
950 #define E1000_82542_TPT E1000_TPT
951 #define E1000_82542_PTC64 E1000_PTC64
952 #define E1000_82542_PTC127 E1000_PTC127
953 #define E1000_82542_PTC255 E1000_PTC255
954 #define E1000_82542_PTC511 E1000_PTC511
955 #define E1000_82542_PTC1023 E1000_PTC1023
956 #define E1000_82542_PTC1522 E1000_PTC1522
957 #define E1000_82542_MPTC E1000_MPTC
958 #define E1000_82542_BPTC E1000_BPTC
959 #define E1000_82542_TSCTC E1000_TSCTC
960 #define E1000_82542_TSCTFC E1000_TSCTFC
961 #define E1000_82542_RXCSUM E1000_RXCSUM
962 #define E1000_82542_WUC E1000_WUC
963 #define E1000_82542_WUFC E1000_WUFC
964 #define E1000_82542_WUS E1000_WUS
965 #define E1000_82542_MANC E1000_MANC
966 #define E1000_82542_IPAV E1000_IPAV
967 #define E1000_82542_IP4AT E1000_IP4AT
968 #define E1000_82542_IP6AT E1000_IP6AT
969 #define E1000_82542_WUPL E1000_WUPL
970 #define E1000_82542_WUPM E1000_WUPM
971 #define E1000_82542_FFLT E1000_FFLT
972 #define E1000_82542_FFMT E1000_FFMT
973 #define E1000_82542_FFVT E1000_FFVT
974
975 /* Statistics counters collected by the MAC */
976 struct e1000_hw_stats {
977 uint64_t crcerrs;
978 uint64_t algnerrc;
979 uint64_t symerrs;
980 uint64_t rxerrc;
981 uint64_t mpc;
982 uint64_t scc;
983 uint64_t ecol;
984 uint64_t mcc;
985 uint64_t latecol;
986 uint64_t colc;
987 uint64_t dc;
988 uint64_t tncrs;
989 uint64_t sec;
990 uint64_t cexterr;
991 uint64_t rlec;
992 uint64_t xonrxc;
993 uint64_t xontxc;
994 uint64_t xoffrxc;
995 uint64_t xofftxc;
996 uint64_t fcruc;
997 uint64_t prc64;
998 uint64_t prc127;
999 uint64_t prc255;
1000 uint64_t prc511;
1001 uint64_t prc1023;
1002 uint64_t prc1522;
1003 uint64_t gprc;
1004 uint64_t bprc;
1005 uint64_t mprc;
1006 uint64_t gptc;
1007 uint64_t gorcl;
1008 uint64_t gorch;
1009 uint64_t gotcl;
1010 uint64_t gotch;
1011 uint64_t rnbc;
1012 uint64_t ruc;
1013 uint64_t rfc;
1014 uint64_t roc;
1015 uint64_t rjc;
1016 uint64_t mgprc;
1017 uint64_t mgpdc;
1018 uint64_t mgptc;
1019 uint64_t torl;
1020 uint64_t torh;
1021 uint64_t totl;
1022 uint64_t toth;
1023 uint64_t tpr;
1024 uint64_t tpt;
1025 uint64_t ptc64;
1026 uint64_t ptc127;
1027 uint64_t ptc255;
1028 uint64_t ptc511;
1029 uint64_t ptc1023;
1030 uint64_t ptc1522;
1031 uint64_t mptc;
1032 uint64_t bptc;
1033 uint64_t tsctc;
1034 uint64_t tsctfc;
1035 };
1036
1037 struct e1000_eeprom_info {
1038 e1000_eeprom_type type;
1039 uint16_t word_size;
1040 uint16_t opcode_bits;
1041 uint16_t address_bits;
1042 uint16_t delay_usec;
1043 uint16_t page_size;
1044 bool use_eerd;
1045 bool use_eewr;
1046 };
1047
1048 typedef enum {
1049 e1000_smart_speed_default = 0,
1050 e1000_smart_speed_on,
1051 e1000_smart_speed_off
1052 } e1000_smart_speed;
1053
1054 typedef enum {
1055 e1000_dsp_config_disabled = 0,
1056 e1000_dsp_config_enabled,
1057 e1000_dsp_config_activated,
1058 e1000_dsp_config_undefined = 0xFF
1059 } e1000_dsp_config;
1060
1061 typedef enum {
1062 e1000_ms_hw_default = 0,
1063 e1000_ms_force_master,
1064 e1000_ms_force_slave,
1065 e1000_ms_auto
1066 } e1000_ms_type;
1067
1068 typedef enum {
1069 e1000_ffe_config_enabled = 0,
1070 e1000_ffe_config_active,
1071 e1000_ffe_config_blocked
1072 } e1000_ffe_config;
1073
1074
1075 /* Structure containing variables used by the shared code (e1000_hw.c) */
1076 struct e1000_hw {
1077 struct list_head list_node;
1078 struct eth_device *nic;
1079 #ifdef CONFIG_E1000_SPI
1080 struct spi_slave spi;
1081 #endif
1082 unsigned int cardnum;
1083
1084 pci_dev_t pdev;
1085 uint8_t *hw_addr;
1086 e1000_mac_type mac_type;
1087 e1000_phy_type phy_type;
1088 uint32_t phy_init_script;
1089 uint32_t txd_cmd;
1090 e1000_media_type media_type;
1091 e1000_fc_type fc;
1092 e1000_bus_type bus_type;
1093 #if 0
1094 e1000_bus_speed bus_speed;
1095 e1000_bus_width bus_width;
1096 uint32_t io_base;
1097 #endif
1098 uint32_t asf_firmware_present;
1099 uint32_t eeprom_semaphore_present;
1100 uint32_t swfw_sync_present;
1101 uint32_t swfwhw_semaphore_present;
1102 struct e1000_eeprom_info eeprom;
1103 e1000_ms_type master_slave;
1104 e1000_ms_type original_master_slave;
1105 e1000_ffe_config ffe_config_state;
1106 uint32_t phy_id;
1107 uint32_t phy_revision;
1108 uint32_t phy_addr;
1109 uint32_t original_fc;
1110 uint32_t txcw;
1111 uint32_t autoneg_failed;
1112 #if 0
1113 uint32_t max_frame_size;
1114 uint32_t min_frame_size;
1115 uint32_t mc_filter_type;
1116 uint32_t num_mc_addrs;
1117 uint32_t collision_delta;
1118 uint32_t tx_packet_delta;
1119 uint32_t ledctl_default;
1120 uint32_t ledctl_mode1;
1121 uint32_t ledctl_mode2;
1122 #endif
1123 uint16_t autoneg_advertised;
1124 uint16_t pci_cmd_word;
1125 uint16_t fc_high_water;
1126 uint16_t fc_low_water;
1127 uint16_t fc_pause_time;
1128 #if 0
1129 uint16_t current_ifs_val;
1130 uint16_t ifs_min_val;
1131 uint16_t ifs_max_val;
1132 uint16_t ifs_step_size;
1133 uint16_t ifs_ratio;
1134 #endif
1135 uint16_t device_id;
1136 uint16_t vendor_id;
1137 uint16_t subsystem_id;
1138 uint16_t subsystem_vendor_id;
1139 uint8_t revision_id;
1140 uint8_t autoneg;
1141 uint8_t mdix;
1142 uint8_t forced_speed_duplex;
1143 uint8_t wait_autoneg_complete;
1144 uint8_t dma_fairness;
1145 #if 0
1146 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
1147 #endif
1148 bool disable_polarity_correction;
1149 bool speed_downgraded;
1150 bool get_link_status;
1151 bool tbi_compatibility_en;
1152 bool tbi_compatibility_on;
1153 bool fc_strict_ieee;
1154 bool fc_send_xon;
1155 bool report_tx_early;
1156 bool phy_reset_disable;
1157 bool initialize_hw_bits_disable;
1158 #if 0
1159 bool adaptive_ifs;
1160 bool ifs_params_forced;
1161 bool in_ifs_mode;
1162 #endif
1163 e1000_smart_speed smart_speed;
1164 e1000_dsp_config dsp_config_state;
1165 };
1166
1167 #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1168 #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
1169 #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM
1170 read/write registers */
1171 #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1172 #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start
1173 operation */
1174 #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1175 #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write
1176 complete */
1177 #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1178 #define EEPROM_RESERVED_WORD 0xFFFF
1179
1180 /* Register Bit Masks */
1181 /* Device Control */
1182 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1183 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1184 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1185 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1186 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1187 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1188 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1189 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1190 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1191 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1192 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1193 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1194 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1195 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1196 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1197 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1198 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1199 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1200 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1201 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1202 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1203 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1204 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1205 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1206 #define E1000_CTRL_RST 0x04000000 /* Global reset */
1207 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1208 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1209 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1210 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1211 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1212
1213 /* Device Status */
1214 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1215 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1216 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1217 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1218 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1219 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1220 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1221 #define E1000_STATUS_SPEED_MASK 0x000000C0
1222 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1223 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1224 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1225 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1226 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1227 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1228 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1229 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1230 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1231
1232 /* Constants used to intrepret the masked PCI-X bus speed. */
1233 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1234 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1235 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1236
1237 /* EEPROM/Flash Control */
1238 #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1239 #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1240 #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1241 #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1242 #define E1000_EECD_FWE_MASK 0x00000030
1243 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1244 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1245 #define E1000_EECD_FWE_SHIFT 4
1246 #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1247 #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1248 #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1249 #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1250 #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1251 * (0-small, 1-large) */
1252
1253 #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1254 #ifndef E1000_EEPROM_GRANT_ATTEMPTS
1255 #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1256 #endif
1257 #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1258 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1259 #define E1000_EECD_SIZE_EX_SHIFT 11
1260 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1261 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1262 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1263 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1264 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1265 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1266 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1267 #define E1000_EECD_SECVAL_SHIFT 22
1268 #define E1000_STM_OPCODE 0xDB00
1269 #define E1000_HICR_FW_RESET 0xC0
1270
1271 #define E1000_SHADOW_RAM_WORDS 2048
1272 #define E1000_ICH_NVM_SIG_WORD 0x13
1273 #define E1000_ICH_NVM_SIG_MASK 0xC0
1274
1275 /* EEPROM Read */
1276 #define E1000_EERD_START 0x00000001 /* Start Read */
1277 #define E1000_EERD_DONE 0x00000010 /* Read Done */
1278 #define E1000_EERD_ADDR_SHIFT 8
1279 #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1280 #define E1000_EERD_DATA_SHIFT 16
1281 #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1282
1283 /* EEPROM Commands - Microwire */
1284 #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
1285 #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
1286 #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
1287 #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
1288 #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
1289
1290 /* EEPROM Commands - SPI */
1291 #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1292 #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
1293 #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
1294 #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1295 #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
1296 #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
1297 #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
1298 #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
1299 #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
1300 #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
1301 #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1302
1303 /* EEPROM Size definitions */
1304 #define EEPROM_WORD_SIZE_SHIFT 6
1305 #define EEPROM_SIZE_SHIFT 10
1306 #define EEPROM_SIZE_MASK 0x1C00
1307
1308 /* EEPROM Word Offsets */
1309 #define EEPROM_COMPAT 0x0003
1310 #define EEPROM_ID_LED_SETTINGS 0x0004
1311 #define EEPROM_VERSION 0x0005
1312 #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude
1313 adjustment. */
1314 #define EEPROM_PHY_CLASS_WORD 0x0007
1315 #define EEPROM_INIT_CONTROL1_REG 0x000A
1316 #define EEPROM_INIT_CONTROL2_REG 0x000F
1317 #define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
1318 #define EEPROM_INIT_CONTROL3_PORT_B 0x0014
1319 #define EEPROM_INIT_3GIO_3 0x001A
1320 #define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
1321 #define EEPROM_INIT_CONTROL3_PORT_A 0x0024
1322 #define EEPROM_CFG 0x0012
1323 #define EEPROM_FLASH_VERSION 0x0032
1324 #define EEPROM_CHECKSUM_REG 0x003F
1325
1326 #define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
1327 #define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
1328
1329 /* Extended Device Control */
1330 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1331 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1332 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1333 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1334 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1335 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable
1336 Pin 4 */
1337 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable
1338 Pin 5 */
1339 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1340 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1341 #define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */
1342 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1343 #define E1000_CTRL_EXT_SWDPIN7 0x00000080 /* SWDPIN 7 value */
1344 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1345 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1346 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1347 #define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */
1348 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1349 #define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */
1350 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1351 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1352 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1353 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1354 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1355 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1356 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1357 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1358 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1359 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1360 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1361 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1362 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1363
1364 /* MDI Control */
1365 #define E1000_MDIC_DATA_MASK 0x0000FFFF
1366 #define E1000_MDIC_REG_MASK 0x001F0000
1367 #define E1000_MDIC_REG_SHIFT 16
1368 #define E1000_MDIC_PHY_MASK 0x03E00000
1369 #define E1000_MDIC_PHY_SHIFT 21
1370 #define E1000_MDIC_OP_WRITE 0x04000000
1371 #define E1000_MDIC_OP_READ 0x08000000
1372 #define E1000_MDIC_READY 0x10000000
1373 #define E1000_MDIC_INT_EN 0x20000000
1374 #define E1000_MDIC_ERROR 0x40000000
1375
1376 #define E1000_PHY_CTRL_SPD_EN 0x00000001
1377 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002
1378 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
1379 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
1380 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
1381 #define E1000_PHY_CTRL_B2B_EN 0x00000080
1382 /* LED Control */
1383 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1384 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
1385 #define E1000_LEDCTL_LED0_IVRT 0x00000040
1386 #define E1000_LEDCTL_LED0_BLINK 0x00000080
1387 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1388 #define E1000_LEDCTL_LED1_MODE_SHIFT 8
1389 #define E1000_LEDCTL_LED1_IVRT 0x00004000
1390 #define E1000_LEDCTL_LED1_BLINK 0x00008000
1391 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1392 #define E1000_LEDCTL_LED2_MODE_SHIFT 16
1393 #define E1000_LEDCTL_LED2_IVRT 0x00400000
1394 #define E1000_LEDCTL_LED2_BLINK 0x00800000
1395 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1396 #define E1000_LEDCTL_LED3_MODE_SHIFT 24
1397 #define E1000_LEDCTL_LED3_IVRT 0x40000000
1398 #define E1000_LEDCTL_LED3_BLINK 0x80000000
1399
1400 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1401 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1402 #define E1000_LEDCTL_MODE_LINK_UP 0x2
1403 #define E1000_LEDCTL_MODE_ACTIVITY 0x3
1404 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1405 #define E1000_LEDCTL_MODE_LINK_10 0x5
1406 #define E1000_LEDCTL_MODE_LINK_100 0x6
1407 #define E1000_LEDCTL_MODE_LINK_1000 0x7
1408 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1409 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1410 #define E1000_LEDCTL_MODE_COLLISION 0xA
1411 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1412 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1413 #define E1000_LEDCTL_MODE_PAUSED 0xD
1414 #define E1000_LEDCTL_MODE_LED_ON 0xE
1415 #define E1000_LEDCTL_MODE_LED_OFF 0xF
1416
1417 /* Receive Address */
1418 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1419
1420 /* Interrupt Cause Read */
1421 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1422 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1423 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1424 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1425 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1426 #define E1000_ICR_RXO 0x00000040 /* rx overrun */
1427 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1428 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1429 #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1430 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1431 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1432 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1433 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1434 #define E1000_ICR_TXD_LOW 0x00008000
1435 #define E1000_ICR_SRPD 0x00010000
1436
1437 /* Interrupt Cause Set */
1438 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1439 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1440 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1441 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1442 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1443 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1444 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1445 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1446 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1447 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1448 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1449 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1450 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1451 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1452 #define E1000_ICS_SRPD E1000_ICR_SRPD
1453
1454 /* Interrupt Mask Set */
1455 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1456 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1457 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1458 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1459 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1460 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1461 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1462 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1463 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1464 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1465 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1466 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1467 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1468 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1469 #define E1000_IMS_SRPD E1000_ICR_SRPD
1470
1471 /* Interrupt Mask Clear */
1472 #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1473 #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1474 #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1475 #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1476 #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1477 #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1478 #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1479 #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1480 #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1481 #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1482 #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1483 #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1484 #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1485 #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1486 #define E1000_IMC_SRPD E1000_ICR_SRPD
1487
1488 /* Receive Control */
1489 #define E1000_RCTL_RST 0x00000001 /* Software reset */
1490 #define E1000_RCTL_EN 0x00000002 /* enable */
1491 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1492 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1493 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1494 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1495 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1496 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1497 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1498 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1499 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1500 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1501 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1502 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1503 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1504 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1505 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1506 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1507 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1508 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1509 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1510 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1511 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1512 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1513 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1514 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1515 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1516 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1517 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1518 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1519 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1520 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1521 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1522 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1523 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1524
1525 /* SW_W_SYNC definitions */
1526 #define E1000_SWFW_EEP_SM 0x0001
1527 #define E1000_SWFW_PHY0_SM 0x0002
1528 #define E1000_SWFW_PHY1_SM 0x0004
1529 #define E1000_SWFW_MAC_CSR_SM 0x0008
1530
1531 /* Receive Descriptor */
1532 #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1533 #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1534 #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1535 #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1536 #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1537
1538 /* Flow Control */
1539 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1540 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1541 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1542 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1543
1544 /* Receive Descriptor Control */
1545 #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1546 #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1547 #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1548 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1549 #define E1000_RXDCTL_FULL_RX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1550
1551 /* Transmit Descriptor Control */
1552 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
1553 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
1554 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
1555 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1556 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1557 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1558 #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1559 still to be processed. */
1560
1561 /* Transmit Configuration Word */
1562 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1563 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1564 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1565 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1566 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1567 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1568 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1569 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1570 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1571 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1572
1573 /* Receive Configuration Word */
1574 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1575 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1576 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1577 #define E1000_RXCW_CC 0x10000000 /* Receive config change */
1578 #define E1000_RXCW_C 0x20000000 /* Receive config */
1579 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1580 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1581
1582 /* Transmit Control */
1583 #define E1000_TCTL_RST 0x00000001 /* software reset */
1584 #define E1000_TCTL_EN 0x00000002 /* enable tx */
1585 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1586 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1587 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1588 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1589 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
1590 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1591 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1592 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1593 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
1594
1595 /* Receive Checksum Control */
1596 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1597 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1598 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1599 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1600
1601 /* Definitions for power management and wakeup registers */
1602 /* Wake Up Control */
1603 #define E1000_WUC_APME 0x00000001 /* APM Enable */
1604 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1605 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1606 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1607
1608 /* Wake Up Filter Control */
1609 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1610 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1611 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1612 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1613 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1614 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1615 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1616 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1617 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1618 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1619 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1620 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1621 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1622 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1623 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1624
1625 /* Wake Up Status */
1626 #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1627 #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1628 #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1629 #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1630 #define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1631 #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1632 #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1633 #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1634 #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1635 #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
1636 #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
1637 #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
1638 #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1639
1640 /* Management Control */
1641 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1642 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1643 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1644 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
1645 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
1646 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
1647 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
1648 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
1649 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1650 #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
1651 * Filtering */
1652 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
1653 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
1654 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
1655 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
1656 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
1657 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
1658 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
1659 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
1660 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
1661
1662 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
1663 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
1664
1665 /* Wake Up Packet Length */
1666 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
1667
1668 #define E1000_MDALIGN 4096
1669
1670 /* EEPROM Commands */
1671 #define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */
1672 #define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */
1673 #define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */
1674 #define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */
1675 #define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */
1676
1677 /* Word definitions for ID LED Settings */
1678 #define ID_LED_RESERVED_0000 0x0000
1679 #define ID_LED_RESERVED_FFFF 0xFFFF
1680 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1681 (ID_LED_OFF1_OFF2 << 8) | \
1682 (ID_LED_DEF1_DEF2 << 4) | \
1683 (ID_LED_DEF1_DEF2))
1684 #define ID_LED_DEF1_DEF2 0x1
1685 #define ID_LED_DEF1_ON2 0x2
1686 #define ID_LED_DEF1_OFF2 0x3
1687 #define ID_LED_ON1_DEF2 0x4
1688 #define ID_LED_ON1_ON2 0x5
1689 #define ID_LED_ON1_OFF2 0x6
1690 #define ID_LED_OFF1_DEF2 0x7
1691 #define ID_LED_OFF1_ON2 0x8
1692 #define ID_LED_OFF1_OFF2 0x9
1693
1694 /* Mask bits for fields in Word 0x03 of the EEPROM */
1695 #define EEPROM_COMPAT_SERVER 0x0400
1696 #define EEPROM_COMPAT_CLIENT 0x0200
1697
1698 /* Mask bits for fields in Word 0x0a of the EEPROM */
1699 #define EEPROM_WORD0A_ILOS 0x0010
1700 #define EEPROM_WORD0A_SWDPIO 0x01E0
1701 #define EEPROM_WORD0A_LRST 0x0200
1702 #define EEPROM_WORD0A_FD 0x0400
1703 #define EEPROM_WORD0A_66MHZ 0x0800
1704
1705 /* Mask bits for fields in Word 0x0f of the EEPROM */
1706 #define EEPROM_WORD0F_PAUSE_MASK 0x3000
1707 #define EEPROM_WORD0F_PAUSE 0x1000
1708 #define EEPROM_WORD0F_ASM_DIR 0x2000
1709 #define EEPROM_WORD0F_ANE 0x0800
1710 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
1711
1712 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
1713 #define EEPROM_SUM 0xBABA
1714
1715 /* EEPROM Map defines (WORD OFFSETS)*/
1716 #define EEPROM_NODE_ADDRESS_BYTE_0 0
1717 #define EEPROM_PBA_BYTE_1 8
1718
1719 /* EEPROM Map Sizes (Byte Counts) */
1720 #define PBA_SIZE 4
1721
1722 /* Collision related configuration parameters */
1723 #define E1000_COLLISION_THRESHOLD 0xF
1724 #define E1000_CT_SHIFT 4
1725 #define E1000_COLLISION_DISTANCE 63
1726 #define E1000_COLLISION_DISTANCE_82542 64
1727 #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1728 #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1729 #define E1000_GB_HDX_COLLISION_DISTANCE 512
1730 #define E1000_COLD_SHIFT 12
1731
1732 /* The number of Transmit and Receive Descriptors must be a multiple of 8 */
1733 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
1734 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
1735
1736 /* Default values for the transmit IPG register */
1737 #define DEFAULT_82542_TIPG_IPGT 10
1738 #define DEFAULT_82543_TIPG_IPGT_FIBER 9
1739 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
1740
1741 #define E1000_TIPG_IPGT_MASK 0x000003FF
1742 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
1743 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
1744
1745 #define DEFAULT_82542_TIPG_IPGR1 2
1746 #define DEFAULT_82543_TIPG_IPGR1 8
1747 #define E1000_TIPG_IPGR1_SHIFT 10
1748
1749 #define DEFAULT_82542_TIPG_IPGR2 10
1750 #define DEFAULT_82543_TIPG_IPGR2 6
1751 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
1752 #define E1000_TIPG_IPGR2_SHIFT 20
1753
1754 #define E1000_TXDMAC_DPP 0x00000001
1755
1756 /* Adaptive IFS defines */
1757 #define TX_THRESHOLD_START 8
1758 #define TX_THRESHOLD_INCREMENT 10
1759 #define TX_THRESHOLD_DECREMENT 1
1760 #define TX_THRESHOLD_STOP 190
1761 #define TX_THRESHOLD_DISABLE 0
1762 #define TX_THRESHOLD_TIMER_MS 10000
1763 #define MIN_NUM_XMITS 1000
1764 #define IFS_MAX 80
1765 #define IFS_STEP 10
1766 #define IFS_MIN 40
1767 #define IFS_RATIO 4
1768
1769 /* PBA constants */
1770 #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
1771 #define E1000_PBA_24K 0x0018
1772 #define E1000_PBA_38K 0x0026
1773 #define E1000_PBA_40K 0x0028
1774 #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
1775
1776 /* Flow Control Constants */
1777 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
1778 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
1779 #define FLOW_CONTROL_TYPE 0x8808
1780
1781 /* The historical defaults for the flow control values are given below. */
1782 #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
1783 #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
1784 #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
1785
1786 /* Flow Control High-Watermark: 43464 bytes */
1787 #define E1000_FC_HIGH_THRESH 0xA9C8
1788 /* Flow Control Low-Watermark: 43456 bytes */
1789 #define E1000_FC_LOW_THRESH 0xA9C0
1790 /* Flow Control Pause Time: 858 usec */
1791 #define E1000_FC_PAUSE_TIME 0x0680
1792
1793 /* PCIX Config space */
1794 #define PCIX_COMMAND_REGISTER 0xE6
1795 #define PCIX_STATUS_REGISTER_LO 0xE8
1796 #define PCIX_STATUS_REGISTER_HI 0xEA
1797
1798 #define PCIX_COMMAND_MMRBC_MASK 0x000C
1799 #define PCIX_COMMAND_MMRBC_SHIFT 0x2
1800 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1801 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1802 #define PCIX_STATUS_HI_MMRBC_4K 0x3
1803 #define PCIX_STATUS_HI_MMRBC_2K 0x2
1804
1805 /* The number of bits that we need to shift right to move the "pause"
1806 * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
1807 * in the TXCW register
1808 */
1809 #define PAUSE_SHIFT 5
1810
1811 /* The number of bits that we need to shift left to move the "SWDPIO"
1812 * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
1813 * in the CTRL register
1814 */
1815 #define SWDPIO_SHIFT 17
1816
1817 /* The number of bits that we need to shift left to move the "SWDPIO_EXT"
1818 * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
1819 * Extended CTRL register.
1820 * in the CTRL register
1821 */
1822 #define SWDPIO__EXT_SHIFT 4
1823
1824 /* The number of bits that we need to shift left to move the "ILOS"
1825 * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
1826 * in the CTRL register
1827 */
1828 #define ILOS_SHIFT 3
1829
1830 #define RECEIVE_BUFFER_ALIGN_SIZE (256)
1831
1832 /* The number of milliseconds we wait for auto-negotiation to complete */
1833 #define LINK_UP_TIMEOUT 500
1834
1835 #define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
1836
1837 /* The carrier extension symbol, as received by the NIC. */
1838 #define CARRIER_EXTENSION 0x0F
1839
1840 /* TBI_ACCEPT macro definition:
1841 *
1842 * This macro requires:
1843 * adapter = a pointer to struct e1000_hw
1844 * status = the 8 bit status field of the RX descriptor with EOP set
1845 * error = the 8 bit error field of the RX descriptor with EOP set
1846 * length = the sum of all the length fields of the RX descriptors that
1847 * make up the current frame
1848 * last_byte = the last byte of the frame DMAed by the hardware
1849 * max_frame_length = the maximum frame length we want to accept.
1850 * min_frame_length = the minimum frame length we want to accept.
1851 *
1852 * This macro is a conditional that should be used in the interrupt
1853 * handler's Rx processing routine when RxErrors have been detected.
1854 *
1855 * Typical use:
1856 * ...
1857 * if (TBI_ACCEPT) {
1858 * accept_frame = true;
1859 * e1000_tbi_adjust_stats(adapter, MacAddress);
1860 * frame_length--;
1861 * } else {
1862 * accept_frame = false;
1863 * }
1864 * ...
1865 */
1866
1867 #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
1868 ((adapter)->tbi_compatibility_on && \
1869 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
1870 ((last_byte) == CARRIER_EXTENSION) && \
1871 (((status) & E1000_RXD_STAT_VP) ? \
1872 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
1873 ((length) <= ((adapter)->max_frame_size + 1))) : \
1874 (((length) > (adapter)->min_frame_size) && \
1875 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
1876
1877 /* Structures, enums, and macros for the PHY */
1878
1879 /* Bit definitions for the Management Data IO (MDIO) and Management Data
1880 * Clock (MDC) pins in the Device Control Register.
1881 */
1882 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
1883 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
1884 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
1885 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
1886 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
1887 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
1888 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
1889 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
1890
1891 /* PHY 1000 MII Register/Bit Definitions */
1892 /* PHY Registers defined by IEEE */
1893 #define PHY_CTRL 0x00 /* Control Register */
1894 #define PHY_STATUS 0x01 /* Status Regiser */
1895 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1896 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1897 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1898 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1899 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1900 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
1901 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1902 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1903 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1904 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1905
1906 /* M88E1000 Specific Registers */
1907 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1908 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
1909 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
1910 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
1911 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1912 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1913
1914 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
1915 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
1916
1917 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1918
1919 /* M88EC018 Rev 2 specific DownShift settings */
1920 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1921 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
1922 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
1923 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
1924 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
1925 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1926 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
1927 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
1928 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
1929
1930 /* IGP01E1000 specifics */
1931 #define IGP01E1000_IEEE_REGS_PAGE 0x0000
1932 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
1933 #define IGP01E1000_IEEE_FORCE_GIGA 0x0140
1934
1935 /* IGP01E1000 Specific Registers */
1936 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
1937 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
1938 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
1939 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
1940 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
1941 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
1942 #define IGP02E1000_PHY_POWER_MGMT 0x19
1943 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
1944
1945 /* IGP01E1000 AGC Registers - stores the cable length values*/
1946 #define IGP01E1000_PHY_AGC_A 0x1172
1947 #define IGP01E1000_PHY_AGC_B 0x1272
1948 #define IGP01E1000_PHY_AGC_C 0x1472
1949 #define IGP01E1000_PHY_AGC_D 0x1872
1950
1951 /* IGP01E1000 Specific Port Config Register - R/W */
1952 #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
1953 #define IGP01E1000_PSCFR_PRE_EN 0x0020
1954 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
1955 #define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
1956 #define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
1957 #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
1958 /* IGP02E1000 AGC Registers for cable length values */
1959 #define IGP02E1000_PHY_AGC_A 0x11B1
1960 #define IGP02E1000_PHY_AGC_B 0x12B1
1961 #define IGP02E1000_PHY_AGC_C 0x14B1
1962 #define IGP02E1000_PHY_AGC_D 0x18B1
1963
1964 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
1965 #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in
1966 non-D0a modes */
1967 #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in
1968 D0a mode */
1969
1970 /* IGP01E1000 DSP Reset Register */
1971 #define IGP01E1000_PHY_DSP_RESET 0x1F33
1972 #define IGP01E1000_PHY_DSP_SET 0x1F71
1973 #define IGP01E1000_PHY_DSP_FFE 0x1F35
1974
1975 #define IGP01E1000_PHY_CHANNEL_NUM 4
1976 #define IGP02E1000_PHY_CHANNEL_NUM 4
1977
1978 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171
1979 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271
1980 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471
1981 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871
1982
1983 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
1984 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
1985
1986 #define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
1987 #define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
1988 #define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
1989 #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
1990
1991 #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
1992 /* IGP01E1000 PCS Initialization register - stores the polarity status when
1993 * speed = 1000 Mbps. */
1994 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
1995 #define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
1996
1997 #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
1998
1999 /* IGP01E1000 GMII FIFO Register */
2000 #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
2001 * on Link-Up */
2002 #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
2003
2004 /* IGP01E1000 Analog Register */
2005 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
2006 #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
2007 #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
2008 #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
2009
2010 #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
2011 #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
2012 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
2013 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
2014 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
2015
2016 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
2017 #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
2018 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
2019 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
2020
2021 /* IGP01E1000 Specific Port Control Register - R/W */
2022 #define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2023 #define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2024 #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2025 #define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2026 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2027 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2028 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
2029 #define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */
2030 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal
2031 Disabled */
2032 #define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */
2033 #define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter
2034 Disabled */
2035 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
2036 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI
2037 configuration */
2038 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX
2039 configuration */
2040 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic
2041 crossover */
2042 #define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended
2043 Distance */
2044 #define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300
2045 #define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */
2046 #define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only
2047 (Energy Detect) */
2048 #define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */
2049 #define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */
2050 #define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */
2051 #define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000
2052 #define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12
2053
2054 /* PHY Specific Status Register (Page 0, Register 17) */
2055 #define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */
2056 #define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */
2057 #define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */
2058 #define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */
2059 #define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */
2060 #define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */
2061 #define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */
2062 #define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */
2063 #define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */
2064 #define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */
2065 #define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */
2066 #define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
2067 #define GG82563_PSSR_SPEED_MASK 0xC000
2068 #define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */
2069 #define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */
2070 #define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */
2071
2072 /* PHY Specific Status Register 2 (Page 0, Register 19) */
2073 #define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */
2074 #define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */
2075 #define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
2076 #define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
2077 #define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
2078 #define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=false Carrier */
2079 #define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
2080 #define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
2081 #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
2082 #define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */
2083 #define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */
2084 #define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */
2085 #define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
2086
2087 /* PHY Specific Control Register 2 (Page 0, Register 26) */
2088 #define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative
2089 Polarity */
2090 #define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C
2091 #define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal
2092 Operation */
2093 #define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns
2094 Sequence */
2095 #define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns
2096 Sequence */
2097 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse
2098 Auto-Negotiation */
2099 #define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable
2100 1000BASE-T */
2101 #define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
2102 #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */
2103 #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */
2104
2105 /* MAC Specific Control Register (Page 2, Register 21) */
2106 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
2107 #define GG82563_MSCR_TX_CLK_MASK 0x0007
2108 #define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
2109 #define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
2110 #define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
2111 #define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
2112
2113 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
2114
2115 /* DSP Distance Register (Page 5, Register 26) */
2116 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
2117 1 = 50-80M;
2118 2 = 80-110M;
2119 3 = 110-140M;
2120 4 = >140M */
2121
2122 /* Kumeran Mode Control Register (Page 193, Register 16) */
2123 #define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs,
2124 0=Kumeran Inband LEDs */
2125 #define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */
2126 #define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080
2127 #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400
2128 #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz,
2129 0=0.8MHz */
2130 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
2131
2132 /* Power Management Control Register (Page 193, Register 20) */
2133 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES
2134 Electrical Idle */
2135 #define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */
2136 #define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */
2137 #define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse
2138 Auto-Negotiation */
2139 #define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps
2140 Auto-Neg in non D0 */
2141 #define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps
2142 Auto-Neg Always */
2143 #define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a
2144 Reverse Auto-Negotiation */
2145 #define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */
2146 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300
2147 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */
2148 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */
2149 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */
2150 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */
2151
2152 /* In-Band Control Register (Page 194, Register 18) */
2153 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
2154
2155
2156 /* Bits...
2157 * 15-5: page
2158 * 4-0: register offset
2159 */
2160 #define GG82563_PAGE_SHIFT 5
2161 #define GG82563_REG(page, reg) \
2162 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2163 #define GG82563_MIN_ALT_REG 30
2164
2165 /* GG82563 Specific Registers */
2166 #define GG82563_PHY_SPEC_CTRL \
2167 GG82563_REG(0, 16) /* PHY Specific Control */
2168 #define GG82563_PHY_SPEC_STATUS \
2169 GG82563_REG(0, 17) /* PHY Specific Status */
2170 #define GG82563_PHY_INT_ENABLE \
2171 GG82563_REG(0, 18) /* Interrupt Enable */
2172 #define GG82563_PHY_SPEC_STATUS_2 \
2173 GG82563_REG(0, 19) /* PHY Specific Status 2 */
2174 #define GG82563_PHY_RX_ERR_CNTR \
2175 GG82563_REG(0, 21) /* Receive Error Counter */
2176 #define GG82563_PHY_PAGE_SELECT \
2177 GG82563_REG(0, 22) /* Page Select */
2178 #define GG82563_PHY_SPEC_CTRL_2 \
2179 GG82563_REG(0, 26) /* PHY Specific Control 2 */
2180 #define GG82563_PHY_PAGE_SELECT_ALT \
2181 GG82563_REG(0, 29) /* Alternate Page Select */
2182 #define GG82563_PHY_TEST_CLK_CTRL \
2183 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
2184
2185 #define GG82563_PHY_MAC_SPEC_CTRL \
2186 GG82563_REG(2, 21) /* MAC Specific Control Register */
2187 #define GG82563_PHY_MAC_SPEC_CTRL_2 \
2188 GG82563_REG(2, 26) /* MAC Specific Control 2 */
2189
2190 #define GG82563_PHY_DSP_DISTANCE \
2191 GG82563_REG(5, 26) /* DSP Distance */
2192
2193 /* Page 193 - Port Control Registers */
2194 #define GG82563_PHY_KMRN_MODE_CTRL \
2195 GG82563_REG(193, 16) /* Kumeran Mode Control */
2196 #define GG82563_PHY_PORT_RESET \
2197 GG82563_REG(193, 17) /* Port Reset */
2198 #define GG82563_PHY_REVISION_ID \
2199 GG82563_REG(193, 18) /* Revision ID */
2200 #define GG82563_PHY_DEVICE_ID \
2201 GG82563_REG(193, 19) /* Device ID */
2202 #define GG82563_PHY_PWR_MGMT_CTRL \
2203 GG82563_REG(193, 20) /* Power Management Control */
2204 #define GG82563_PHY_RATE_ADAPT_CTRL \
2205 GG82563_REG(193, 25) /* Rate Adaptation Control */
2206
2207 /* Page 194 - KMRN Registers */
2208 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
2209 GG82563_REG(194, 16) /* FIFO's Control/Status */
2210 #define GG82563_PHY_KMRN_CTRL \
2211 GG82563_REG(194, 17) /* Control */
2212 #define GG82563_PHY_INBAND_CTRL \
2213 GG82563_REG(194, 18) /* Inband Control */
2214 #define GG82563_PHY_KMRN_DIAGNOSTIC \
2215 GG82563_REG(194, 19) /* Diagnostic */
2216 #define GG82563_PHY_ACK_TIMEOUTS \
2217 GG82563_REG(194, 20) /* Acknowledge Timeouts */
2218 #define GG82563_PHY_ADV_ABILITY \
2219 GG82563_REG(194, 21) /* Advertised Ability */
2220 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
2221 GG82563_REG(194, 23) /* Link Partner Advertised Ability */
2222 #define GG82563_PHY_ADV_NEXT_PAGE \
2223 GG82563_REG(194, 24) /* Advertised Next Page */
2224 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
2225 GG82563_REG(194, 25) /* Link Partner Advertised Next page */
2226 #define GG82563_PHY_KMRN_MISC \
2227 GG82563_REG(194, 26) /* Misc. */
2228
2229 /* PHY Control Register */
2230 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2231 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2232 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2233 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2234 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2235 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
2236 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2237 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2238 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2239 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
2240
2241 /* PHY Status Register */
2242 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2243 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2244 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2245 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2246 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2247 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2248 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2249 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2250 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2251 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2252 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2253 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2254 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2255 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2256 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
2257
2258 /* Autoneg Advertisement Register */
2259 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2260 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2261 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2262 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2263 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2264 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2265 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2266 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2267 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2268 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2269
2270 /* Link Partner Ability Register (Base Page) */
2271 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2272 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2273 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2274 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2275 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2276 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2277 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2278 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2279 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2280 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2281 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2282
2283 /* Autoneg Expansion Register */
2284 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2285 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2286 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2287 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2288 #define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */
2289
2290 /* Next Page TX Register */
2291 #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2292 #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2293 * of different NP
2294 */
2295 #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2296 * 0 = cannot comply with msg
2297 */
2298 #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2299 #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2300 * 0 = sending last NP
2301 */
2302
2303 /* Link Partner Next Page Register */
2304 #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2305 #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2306 * of different NP
2307 */
2308 #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2309 * 0 = cannot comply with msg
2310 */
2311 #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2312 #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2313 #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2314 * 0 = sending last NP
2315 */
2316
2317 /* 1000BASE-T Control Register */
2318 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2319 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2320 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2321 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2322 /* 0=DTE device */
2323 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2324 /* 0=Configure PHY as Slave */
2325 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2326 /* 0=Automatic Master/Slave config */
2327 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2328 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2329 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2330 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2331 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
2332
2333 /* 1000BASE-T Status Register */
2334 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2335 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2336 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2337 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2338 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2339 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2340 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2341 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
2342 #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2343 #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2344
2345 /* Extended Status Register */
2346 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2347 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2348 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2349 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
2350
2351 #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2352 #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
2353
2354 #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2355 /* (0=enable, 1=disable) */
2356
2357 /* M88E1000 PHY Specific Control Register */
2358 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
2359 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2360 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2361 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
2362 * 0=CLK125 toggling
2363 */
2364 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2365 /* Manual MDI configuration */
2366 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2367 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2368 * 100BASE-TX/10BASE-T:
2369 * MDI Mode
2370 */
2371 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2372 * all speeds.
2373 */
2374 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2375 /* 1=Enable Extended 10BASE-T distance
2376 * (Lower 10BASE-T RX Threshold)
2377 * 0=Normal 10BASE-T RX Threshold */
2378 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2379 /* 1=5-Bit interface in 100BASE-TX
2380 * 0=MII interface in 100BASE-TX */
2381 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2382 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2383 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
2384
2385 #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2386 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2387 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2388
2389 /* M88E1000 PHY Specific Status Register */
2390 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2391 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2392 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2393 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2394 * 3=110-140M;4=>140M */
2395 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2396 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2397 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2398 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2399 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2400 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2401 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2402 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
2403
2404 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2405 #define M88E1000_PSSR_MDIX_SHIFT 6
2406 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2407
2408 /* M88E1000 Extended PHY Specific Control Register */
2409 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2410 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
2411 * Will assert lost lock and bring
2412 * link down if idle not seen
2413 * within 1ms in 1000BASE-T
2414 */
2415 /* Number of times we will attempt to autonegotiate before downshifting if we
2416 * are the master */
2417 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2418 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2419 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
2420 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
2421 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2422 /* Number of times we will attempt to autonegotiate before downshifting if we
2423 * are the slave */
2424 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2425 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2426 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2427 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2428 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2429 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2430 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2431 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2432
2433 /* Bit definitions for valid PHY IDs. */
2434 #define M88E1000_E_PHY_ID 0x01410C50
2435 #define M88E1000_I_PHY_ID 0x01410C30
2436 #define M88E1011_I_PHY_ID 0x01410C20
2437 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2438 #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2439 #define IGP01E1000_I_PHY_ID 0x02A80380
2440 #define M88E1011_I_REV_4 0x04
2441 #define M88E1111_I_PHY_ID 0x01410CC0
2442 #define L1LXT971A_PHY_ID 0x001378E0
2443 #define GG82563_E_PHY_ID 0x01410CA0
2444
2445 #define BME1000_E_PHY_ID 0x01410CB0
2446
2447 /* Miscellaneous PHY bit definitions. */
2448 #define PHY_PREAMBLE 0xFFFFFFFF
2449 #define PHY_SOF 0x01
2450 #define PHY_OP_READ 0x02
2451 #define PHY_OP_WRITE 0x01
2452 #define PHY_TURNAROUND 0x02
2453 #define PHY_PREAMBLE_SIZE 32
2454 #define MII_CR_SPEED_1000 0x0040
2455 #define MII_CR_SPEED_100 0x2000
2456 #define MII_CR_SPEED_10 0x0000
2457 #define E1000_PHY_ADDRESS 0x01
2458 #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
2459 #define PHY_FORCE_TIME 20 /* 2.0 Seconds */
2460 #define PHY_REVISION_MASK 0xFFFFFFF0
2461 #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
2462 #define REG4_SPEED_MASK 0x01E0
2463 #define REG9_SPEED_MASK 0x0300
2464 #define ADVERTISE_10_HALF 0x0001
2465 #define ADVERTISE_10_FULL 0x0002
2466 #define ADVERTISE_100_HALF 0x0004
2467 #define ADVERTISE_100_FULL 0x0008
2468 #define ADVERTISE_1000_HALF 0x0010
2469 #define ADVERTISE_1000_FULL 0x0020
2470
2471 #define ICH_FLASH_GFPREG 0x0000
2472 #define ICH_FLASH_HSFSTS 0x0004
2473 #define ICH_FLASH_HSFCTL 0x0006
2474 #define ICH_FLASH_FADDR 0x0008
2475 #define ICH_FLASH_FDATA0 0x0010
2476 #define ICH_FLASH_FRACC 0x0050
2477 #define ICH_FLASH_FREG0 0x0054
2478 #define ICH_FLASH_FREG1 0x0058
2479 #define ICH_FLASH_FREG2 0x005C
2480 #define ICH_FLASH_FREG3 0x0060
2481 #define ICH_FLASH_FPR0 0x0074
2482 #define ICH_FLASH_FPR1 0x0078
2483 #define ICH_FLASH_SSFSTS 0x0090
2484 #define ICH_FLASH_SSFCTL 0x0092
2485 #define ICH_FLASH_PREOP 0x0094
2486 #define ICH_FLASH_OPTYPE 0x0096
2487 #define ICH_FLASH_OPMENU 0x0098
2488
2489 #define ICH_FLASH_REG_MAPSIZE 0x00A0
2490 #define ICH_FLASH_SECTOR_SIZE 4096
2491 #define ICH_GFPREG_BASE_MASK 0x1FFF
2492 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
2493
2494 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
2495
2496 /* SPI EEPROM Status Register */
2497 #define EEPROM_STATUS_RDY_SPI 0x01
2498 #define EEPROM_STATUS_WEN_SPI 0x02
2499 #define EEPROM_STATUS_BP0_SPI 0x04
2500 #define EEPROM_STATUS_BP1_SPI 0x08
2501 #define EEPROM_STATUS_WPEN_SPI 0x80
2502
2503 /* SW Semaphore Register */
2504 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
2505 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
2506 #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
2507 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
2508
2509 /* FW Semaphore Register */
2510 #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
2511 #define E1000_FWSM_MODE_SHIFT 1
2512 #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2513
2514 #define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2515 #define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
2516 #define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
2517 #define E1000_FWSM_SKUEL_SHIFT 29
2518 #define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
2519 #define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
2520 #define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
2521 #define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
2522
2523 #define E1000_GCR 0x05B00 /* PCI-Ex Control */
2524 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
2525 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
2526 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
2527 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
2528 #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
2529 #define E1000_SWSM 0x05B50 /* SW Semaphore */
2530 #define E1000_FWSM 0x05B54 /* FW Semaphore */
2531 #define E1000_FFLT_DBG 0x05F04 /* Debug Register */
2532 #define E1000_HICR 0x08F00 /* Host Inteface Control */
2533
2534 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
2535 #define IGP_ACTIVITY_LED_ENABLE 0x0300
2536 #define IGP_LED3_MODE 0x07000000
2537
2538 /* Mask bit for PHY class in Word 7 of the EEPROM */
2539 #define EEPROM_PHY_CLASS_A 0x8000
2540 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
2541 #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
2542 #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
2543
2544 #define E1000_KUMCTRLSTA_MASK 0x0000FFFF
2545 #define E1000_KUMCTRLSTA_OFFSET 0x001F0000
2546 #define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
2547 #define E1000_KUMCTRLSTA_REN 0x00200000
2548
2549 #define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
2550 #define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
2551 #define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
2552 #define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
2553 #define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
2554 #define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
2555 #define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
2556 #define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
2557 #define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
2558
2559 /* FIFO Control */
2560 #define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
2561 #define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
2562
2563 /* In-Band Control */
2564 #define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
2565 #define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
2566
2567 /* Half-Duplex Control */
2568 #define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
2569 #define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
2570
2571 #define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
2572
2573 #define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
2574 #define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
2575
2576 #define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
2577 #define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
2578 #define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
2579
2580 #define E1000_MNG_ICH_IAMT_MODE 0x2
2581 #define E1000_MNG_IAMT_MODE 0x3
2582 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
2583 #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
2584 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
2585 #define PHY_CFG_TIMEOUT 100
2586 #define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
2587 #define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
2588 #define AUTO_ALL_MODES 0
2589
2590 #ifndef E1000_MASTER_SLAVE
2591 /* Switch to override PHY master/slave setting */
2592 #define E1000_MASTER_SLAVE e1000_ms_hw_default
2593 #endif
2594 /* Extended Transmit Control */
2595 #define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
2596 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
2597
2598 #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
2599
2600 #define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
2601
2602 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2603 #define E1000_MC_TBL_SIZE_ICH8LAN 32
2604
2605 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers
2606 after IMS clear */
2607 #endif /* _E1000_HW_H_ */
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