drivers/net/fm/fm.h

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __FM_H__
   8 #define __FM_H__
   9
  10 #include <common.h>
  11 #include <fm_eth.h>
  12 #include <asm/fsl_enet.h>
  13 #include <asm/fsl_fman.h>
  14
  15 /* Port ID */
  16 #define OH_PORT_ID_BASE         0x01
  17 #define MAX_NUM_OH_PORT         7
  18 #define RX_PORT_1G_BASE         0x08
  19 #define MAX_NUM_RX_PORT_1G      CONFIG_SYS_NUM_FM1_DTSEC
  20 #define RX_PORT_10G_BASE        0x10
  21 #define TX_PORT_1G_BASE         0x28
  22 #define MAX_NUM_TX_PORT_1G      CONFIG_SYS_NUM_FM1_DTSEC
  23 #define TX_PORT_10G_BASE        0x30
  24
  25 struct fm_muram {
  26         u32 base;
  27         u32 top;
  28         u32 size;
  29         u32 alloc;
  30 };
  31 #define FM_MURAM_RES_SIZE       0x01000
  32
  33 /* Rx/Tx buffer descriptor */
  34 struct fm_port_bd {
  35         u16 status;
  36         u16 len;
  37         u32 res0;
  38         u16 res1;
  39         u16 buf_ptr_hi;
  40         u32 buf_ptr_lo;
  41 };
  42
  43 /* Common BD flags */
  44 #define BD_LAST                 0x0800
  45
  46 /* Rx BD status flags */
  47 #define RxBD_EMPTY              0x8000
  48 #define RxBD_LAST               BD_LAST
  49 #define RxBD_FIRST              0x0400
  50 #define RxBD_PHYS_ERR           0x0008
  51 #define RxBD_SIZE_ERR           0x0004
  52 #define RxBD_ERROR              (RxBD_PHYS_ERR | RxBD_SIZE_ERR)
  53
  54 /* Tx BD status flags */
  55 #define TxBD_READY              0x8000
  56 #define TxBD_LAST               BD_LAST
  57
  58 /* Rx/Tx queue descriptor */
  59 struct fm_port_qd {
  60         u16 gen;
  61         u16 bd_ring_base_hi;
  62         u32 bd_ring_base_lo;
  63         u16 bd_ring_size;
  64         u16 offset_in;
  65         u16 offset_out;
  66         u16 res0;
  67         u32 res1[0x4];
  68 };
  69
  70 /* IM global parameter RAM */
  71 struct fm_port_global_pram {
  72         u32 mode;       /* independent mode register */
  73         u32 rxqd_ptr;   /* Rx queue descriptor pointer */
  74         u32 txqd_ptr;   /* Tx queue descriptor pointer */
  75         u16 mrblr;      /* max Rx buffer length */
  76         u16 rxqd_bsy_cnt;       /* RxQD busy counter, should be cleared */
  77         u32 res0[0x4];
  78         struct fm_port_qd rxqd; /* Rx queue descriptor */
  79         struct fm_port_qd txqd; /* Tx queue descriptor */
  80         u32 res1[0x28];
  81 };
  82
  83 #define FM_PRAM_SIZE            sizeof(struct fm_port_global_pram)
  84 #define FM_PRAM_ALIGN           256
  85 #define PRAM_MODE_GLOBAL        0x20000000
  86 #define PRAM_MODE_GRACEFUL_STOP 0x00800000
  87
  88 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
  89 #define FM_FREE_POOL_SIZE       0x2000 /* 8K bytes */
  90 #else
  91 #define FM_FREE_POOL_SIZE       0x20000 /* 128K bytes */
  92 #endif
  93 #define FM_FREE_POOL_ALIGN      256
  94
  95 u32 fm_muram_alloc(int fm_idx, u32 size, u32 align);
  96 u32 fm_muram_base(int fm_idx);
  97 int fm_init_common(int index, struct ccsr_fman *reg);
  98 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info);
  99 phy_interface_t fman_port_enet_if(enum fm_port port);
 100 void fman_disable_port(enum fm_port port);
 101
 102 struct fsl_enet_mac {
 103         void *base; /* MAC controller registers base address */
 104         void *phyregs;
 105         int max_rx_len;
 106         void (*init_mac)(struct fsl_enet_mac *mac);
 107         void (*enable_mac)(struct fsl_enet_mac *mac);
 108         void (*disable_mac)(struct fsl_enet_mac *mac);
 109         void (*set_mac_addr)(struct fsl_enet_mac *mac, u8 *mac_addr);
 110         void (*set_if_mode)(struct fsl_enet_mac *mac, phy_interface_t type,
 111                                 int speed);
 112 };
 113
 114 /* Fman ethernet private struct */
 115 struct fm_eth {
 116         int fm_index;                   /* Fman index */
 117         u32 num;                        /* 0..n-1 for give type */
 118         struct fm_bmi_tx_port *tx_port;
 119         struct fm_bmi_rx_port *rx_port;
 120         enum fm_eth_type type;          /* 1G or 10G ethernet */
 121         phy_interface_t enet_if;
 122         struct fsl_enet_mac *mac;       /* MAC controller */
 123         struct mii_dev *bus;
 124         struct phy_device *phydev;
 125         int phyaddr;
 126         struct eth_device *dev;
 127         int max_rx_len;
 128         struct fm_port_global_pram *rx_pram; /* Rx parameter table */
 129         struct fm_port_global_pram *tx_pram; /* Tx parameter table */
 130         void *rx_bd_ring;               /* Rx BD ring base */
 131         void *cur_rxbd;                 /* current Rx BD */
 132         void *rx_buf;                   /* Rx buffer base */
 133         void *tx_bd_ring;               /* Tx BD ring base */
 134         void *cur_txbd;                 /* current Tx BD */
 135 };
 136
 137 #define RX_BD_RING_SIZE         8
 138 #define TX_BD_RING_SIZE         8
 139 #define MAX_RXBUF_LOG2          11
 140 #define MAX_RXBUF_LEN           (1 << MAX_RXBUF_LOG2)
 141
 142 #define PORT_IS_ENABLED(port)   fm_info[fm_port_to_index(port)].enabled
 143
 144 #endif /* __FM_H__ */