drivers/net/fm/memac.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  *      Roy Zang <tie-fei.zang@freescale.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 /* MAXFRM - maximum frame length */
  22 #define MAXFRM_MASK     0x0000ffff
  23
  24 #include <common.h>
  25 #include <phy.h>
  26 #include <asm/types.h>
  27 #include <asm/io.h>
  28 #include <asm/fsl_enet.h>
  29 #include <asm/fsl_memac.h>
  30
  31 #include "fm.h"
  32
  33 static void memac_init_mac(struct fsl_enet_mac *mac)
  34 {
  35         struct memac *regs = mac->base;
  36
  37         /* mask all interrupt */
  38         out_be32(&regs->imask, IMASK_MASK_ALL);
  39
  40         /* clear all events */
  41         out_be32(&regs->ievent, IEVENT_CLEAR_ALL);
  42
  43         /* set the max receive length */
  44         out_be32(&regs->maxfrm, mac->max_rx_len & MAXFRM_MASK);
  45
  46         /* multicast frame reception for the hash entry disable */
  47         out_be32(&regs->hashtable_ctrl, 0);
  48 }
  49
  50 static void memac_enable_mac(struct fsl_enet_mac *mac)
  51 {
  52         struct memac *regs = mac->base;
  53
  54         setbits_be32(&regs->command_config, MEMAC_CMD_CFG_RXTX_EN);
  55 }
  56
  57 static void memac_disable_mac(struct fsl_enet_mac *mac)
  58 {
  59         struct memac *regs = mac->base;
  60
  61         clrbits_be32(&regs->command_config, MEMAC_CMD_CFG_RXTX_EN);
  62 }
  63
  64 static void memac_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr)
  65 {
  66         struct memac *regs = mac->base;
  67         u32 mac_addr0, mac_addr1;
  68
  69         /*
  70          * if a station address of 0x12345678ABCD, perform a write to
  71          * MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB
  72          */
  73         mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \
  74                         (mac_addr[1] << 8)  | (mac_addr[0]);
  75         out_be32(&regs->mac_addr_0, mac_addr0);
  76
  77         mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff;
  78         out_be32(&regs->mac_addr_1, mac_addr1);
  79 }
  80
  81 static void memac_set_interface_mode(struct fsl_enet_mac *mac,
  82                                         phy_interface_t type, int speed)
  83 {
  84         /* Roy need more work here */
  85
  86         struct memac *regs = mac->base;
  87         u32 if_mode, if_status;
  88
  89         /* clear all bits relative with interface mode */
  90         if_mode = in_be32(&regs->if_mode);
  91         if_status = in_be32(&regs->if_status);
  92
  93         /* set interface mode */
  94         switch (type) {
  95         case PHY_INTERFACE_MODE_GMII:
  96                 if_mode &= ~IF_MODE_MASK;
  97                 if_mode |= IF_MODE_GMII;
  98                 break;
  99         case PHY_INTERFACE_MODE_RGMII:
 100                 if_mode |= (IF_MODE_GMII | IF_MODE_RG);
 101                 break;
 102         case PHY_INTERFACE_MODE_RMII:
 103                 if_mode |= (IF_MODE_GMII | IF_MODE_RM);
 104                 break;
 105         case PHY_INTERFACE_MODE_SGMII:
 106                 if_mode &= ~IF_MODE_MASK;
 107                 if_mode |= (IF_MODE_GMII);
 108                 break;
 109         default:
 110                 break;
 111         }
 112         /* Enable automatic speed selection */
 113         if_mode |= IF_MODE_EN_AUTO;
 114
 115         if (type == PHY_INTERFACE_MODE_RGMII) {
 116                 if_mode &= ~IF_MODE_EN_AUTO;
 117                 if_mode &= ~IF_MODE_SETSP_MASK;
 118                 switch (speed) {
 119                 case SPEED_1000:
 120                         if_mode |= IF_MODE_SETSP_1000M;
 121                         break;
 122                 case SPEED_100:
 123                         if_mode |= IF_MODE_SETSP_100M;
 124                         break;
 125                 case SPEED_10:
 126                         if_mode |= IF_MODE_SETSP_10M;
 127                 default:
 128                         break;
 129                 }
 130         }
 131
 132         debug(" %s, if_mode = %x\n", __func__,  if_mode);
 133         debug(" %s, if_status = %x\n", __func__,  if_status);
 134         out_be32(&regs->if_mode, if_mode);
 135         return;
 136 }
 137
 138 void init_memac(struct fsl_enet_mac *mac, void *base,
 139                 void *phyregs, int max_rx_len)
 140 {
 141         mac->base = base;
 142         mac->phyregs = phyregs;
 143         mac->max_rx_len = max_rx_len;
 144         mac->init_mac = memac_init_mac;
 145         mac->enable_mac = memac_enable_mac;
 146         mac->disable_mac = memac_disable_mac;
 147         mac->set_mac_addr = memac_set_mac_addr;
 148         mac->set_if_mode = memac_set_interface_mode;
 149 }