2 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/err.h>
11 #include <dm/device.h>
12 #include <dm/pinctrl.h>
14 #include "pinctrl-imx.h"
16 DECLARE_GLOBAL_DATA_PTR
;
18 static int imx_pinctrl_set_state(struct udevice
*dev
, struct udevice
*config
)
20 struct imx_pinctrl_priv
*priv
= dev_get_priv(dev
);
21 struct imx_pinctrl_soc_info
*info
= priv
->info
;
22 int node
= dev_of_offset(config
);
23 const struct fdt_property
*prop
;
25 int npins
, size
, pin_size
;
26 int mux_reg
, conf_reg
, input_reg
, input_val
, mux_mode
, config_val
;
27 u32 mux_shift
= info
->mux_mask
? ffs(info
->mux_mask
) - 1 : 0;
30 dev_dbg(dev
, "%s: %s\n", __func__
, config
->name
);
32 if (info
->flags
& SHARE_MUX_CONF_REG
)
33 pin_size
= SHARE_FSL_PIN_SIZE
;
35 pin_size
= FSL_PIN_SIZE
;
37 prop
= fdt_getprop(gd
->fdt_blob
, node
, "fsl,pins", &size
);
39 dev_err(dev
, "No fsl,pins property in node %s\n", config
->name
);
43 if (!size
|| size
% pin_size
) {
44 dev_err(dev
, "Invalid fsl,pins property in node %s\n",
49 pin_data
= devm_kzalloc(dev
, size
, 0);
53 if (fdtdec_get_int_array(gd
->fdt_blob
, node
, "fsl,pins",
54 pin_data
, size
>> 2)) {
55 dev_err(dev
, "Error reading pin data.\n");
56 devm_kfree(dev
, pin_data
);
60 npins
= size
/ pin_size
;
63 * Refer to linux documentation for details:
64 * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
66 for (i
= 0; i
< npins
; i
++) {
67 mux_reg
= pin_data
[j
++];
69 if (!(info
->flags
& ZERO_OFFSET_VALID
) && !mux_reg
)
72 if (info
->flags
& SHARE_MUX_CONF_REG
) {
75 conf_reg
= pin_data
[j
++];
76 if (!(info
->flags
& ZERO_OFFSET_VALID
) && !conf_reg
)
80 if ((mux_reg
== -1) || (conf_reg
== -1)) {
81 dev_err(dev
, "Error mux_reg or conf_reg\n");
82 devm_kfree(dev
, pin_data
);
86 input_reg
= pin_data
[j
++];
87 mux_mode
= pin_data
[j
++];
88 input_val
= pin_data
[j
++];
89 config_val
= pin_data
[j
++];
91 dev_dbg(dev
, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, "
92 "mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n",
93 mux_reg
, conf_reg
, input_reg
, mux_mode
, input_val
,
96 if (config_val
& IMX_PAD_SION
)
97 mux_mode
|= IOMUXC_CONFIG_SION
;
99 config_val
&= ~IMX_PAD_SION
;
102 if (info
->flags
& SHARE_MUX_CONF_REG
) {
103 clrsetbits_le32(info
->base
+ mux_reg
, info
->mux_mask
,
104 mux_mode
<< mux_shift
);
106 writel(mux_mode
, info
->base
+ mux_reg
);
109 dev_dbg(dev
, "write mux: offset 0x%x val 0x%x\n", mux_reg
,
115 * If the select input value begins with 0xff, it's a quirky
116 * select input and the value should be interpreted as below.
118 * | 0xff | shift | width | select |
119 * It's used to work around the problem that the select
120 * input for some pin is not implemented in the select
121 * input register but in some general purpose register.
122 * We encode the select input value, width and shift of
123 * the bit field into input_val cell of pin function ID
124 * in device tree, and then decode them here for setting
125 * up the select input bits in general purpose register.
128 if (input_val
>> 24 == 0xff) {
130 u8 select
= val
& 0xff;
131 u8 width
= (val
>> 8) & 0xff;
132 u8 shift
= (val
>> 16) & 0xff;
133 u32 mask
= ((1 << width
) - 1) << shift
;
135 * The input_reg[i] here is actually some IOMUXC general
136 * purpose register, not regular select input register.
138 val
= readl(info
->base
+ input_reg
);
140 val
|= select
<< shift
;
141 writel(val
, info
->base
+ input_reg
);
142 } else if (input_reg
) {
144 * Regular select input register can never be at offset
145 * 0, and we only print register value for regular case.
147 if (info
->input_sel_base
)
148 writel(input_val
, info
->input_sel_base
+
151 writel(input_val
, info
->base
+ input_reg
);
153 dev_dbg(dev
, "select_input: offset 0x%x val 0x%x\n",
154 input_reg
, input_val
);
158 if (!(config_val
& IMX_NO_PAD_CTL
)) {
159 if (info
->flags
& SHARE_MUX_CONF_REG
) {
160 clrsetbits_le32(info
->base
+ conf_reg
,
161 info
->mux_mask
, config_val
);
163 writel(config_val
, info
->base
+ conf_reg
);
166 dev_dbg(dev
, "write config: offset 0x%x val 0x%x\n",
167 conf_reg
, config_val
);
171 devm_kfree(dev
, pin_data
);
176 const struct pinctrl_ops imx_pinctrl_ops
= {
177 .set_state
= imx_pinctrl_set_state
,
180 int imx_pinctrl_probe(struct udevice
*dev
,
181 struct imx_pinctrl_soc_info
*info
)
183 struct imx_pinctrl_priv
*priv
= dev_get_priv(dev
);
184 int node
= dev_of_offset(dev
), ret
;
185 struct fdtdec_phandle_args arg
;
190 dev_err(dev
, "wrong pinctrl info\n");
197 addr
= fdtdec_get_addr_size(gd
->fdt_blob
, dev_of_offset(dev
), "reg",
200 if (addr
== FDT_ADDR_T_NONE
)
203 info
->base
= map_sysmem(addr
, size
);
208 info
->mux_mask
= fdtdec_get_int(gd
->fdt_blob
, node
, "fsl,mux_mask", 0);
210 * Refer to linux documentation for details:
211 * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
213 if (fdtdec_get_bool(gd
->fdt_blob
, node
, "fsl,input-sel")) {
214 ret
= fdtdec_parse_phandle_with_args(gd
->fdt_blob
,
215 node
, "fsl,input-sel",
218 dev_err(dev
, "iomuxc fsl,input-sel property not found\n");
222 addr
= fdtdec_get_addr_size(gd
->fdt_blob
, arg
.node
, "reg",
224 if (addr
== FDT_ADDR_T_NONE
)
227 info
->input_sel_base
= map_sysmem(addr
, size
);
228 if (!info
->input_sel_base
)
232 dev_dbg(dev
, "initialized IMX pinctrl driver\n");
237 int imx_pinctrl_remove(struct udevice
*dev
)
239 struct imx_pinctrl_priv
*priv
= dev_get_priv(dev
);
240 struct imx_pinctrl_soc_info
*info
= priv
->info
;
242 if (info
->input_sel_base
)
243 unmap_sysmem(info
->input_sel_base
);
245 unmap_sysmem(info
->base
);