drivers/pinctrl/rockchip/pinctrl_rk3328.c

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <syscon.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/arch/grf_rk3328.h>
  14 #include <asm/arch/periph.h>
  15 #include <asm/io.h>
  16 #include <dm/pinctrl.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 struct rk3328_pinctrl_priv {
  21         struct rk3328_grf_regs *grf;
  22 };
  23
  24 enum {
  25         /* GRF_GPIO0A_IOMUX */
  26         GRF_GPIO0A5_SEL_SHIFT   = 10,
  27         GRF_GPIO0A5_SEL_MASK    = 3 << GRF_GPIO0A5_SEL_SHIFT,
  28         GRF_I2C3_SCL            = 2,
  29
  30         GRF_GPIO0A6_SEL_SHIFT   = 12,
  31         GRF_GPIO0A6_SEL_MASK    = 3 << GRF_GPIO0A6_SEL_SHIFT,
  32         GRF_I2C3_SDA            = 2,
  33
  34         GRF_GPIO0A7_SEL_SHIFT   = 14,
  35         GRF_GPIO0A7_SEL_MASK    = 3 << GRF_GPIO0A7_SEL_SHIFT,
  36         GRF_EMMC_DATA0          = 2,
  37
  38         /* GRF_GPIO1A_IOMUX */
  39         GRF_GPIO1A0_SEL_SHIFT   = 0,
  40         GRF_GPIO1A0_SEL_MASK    = 0x3fff << GRF_GPIO1A0_SEL_SHIFT,
  41         GRF_CARD_DATA_CLK_CMD_DETN      = 0x1555,
  42
  43         /* GRF_GPIO2A_IOMUX */
  44         GRF_GPIO2A0_SEL_SHIFT   = 0,
  45         GRF_GPIO2A0_SEL_MASK    = 3 << GRF_GPIO2A0_SEL_SHIFT,
  46         GRF_UART2_TX_M1         = 1,
  47
  48         GRF_GPIO2A1_SEL_SHIFT   = 2,
  49         GRF_GPIO2A1_SEL_MASK    = 3 << GRF_GPIO2A1_SEL_SHIFT,
  50         GRF_UART2_RX_M1         = 1,
  51
  52         GRF_GPIO2A2_SEL_SHIFT   = 4,
  53         GRF_GPIO2A2_SEL_MASK    = 3 << GRF_GPIO2A2_SEL_SHIFT,
  54         GRF_PWM_IR              = 1,
  55
  56         GRF_GPIO2A4_SEL_SHIFT   = 8,
  57         GRF_GPIO2A4_SEL_MASK    = 3 << GRF_GPIO2A4_SEL_SHIFT,
  58         GRF_PWM_0               = 1,
  59         GRF_I2C1_SDA,
  60
  61         GRF_GPIO2A5_SEL_SHIFT   = 10,
  62         GRF_GPIO2A5_SEL_MASK    = 3 << GRF_GPIO2A5_SEL_SHIFT,
  63         GRF_PWM_1               = 1,
  64         GRF_I2C1_SCL,
  65
  66         GRF_GPIO2A6_SEL_SHIFT   = 12,
  67         GRF_GPIO2A6_SEL_MASK    = 3 << GRF_GPIO2A6_SEL_SHIFT,
  68         GRF_PWM_2               = 1,
  69
  70         GRF_GPIO2A7_SEL_SHIFT   = 14,
  71         GRF_GPIO2A7_SEL_MASK    = 3 << GRF_GPIO2A7_SEL_SHIFT,
  72         GRF_CARD_PWR_EN_M0      = 1,
  73
  74         /* GRF_GPIO2BL_IOMUX */
  75         GRF_GPIO2BL0_SEL_SHIFT  = 0,
  76         GRF_GPIO2BL0_SEL_MASK   = 0x3f << GRF_GPIO2BL0_SEL_SHIFT,
  77         GRF_SPI_CLK_TX_RX_M0    = 0x15,
  78
  79         GRF_GPIO2BL3_SEL_SHIFT  = 6,
  80         GRF_GPIO2BL3_SEL_MASK   = 3 << GRF_GPIO2BL3_SEL_SHIFT,
  81         GRF_SPI_CSN0_M0         = 1,
  82
  83         GRF_GPIO2BL4_SEL_SHIFT  = 8,
  84         GRF_GPIO2BL4_SEL_MASK   = 3 << GRF_GPIO2BL4_SEL_SHIFT,
  85         GRF_SPI_CSN1_M0         = 1,
  86
  87         GRF_GPIO2BL5_SEL_SHIFT  = 10,
  88         GRF_GPIO2BL5_SEL_MASK   = 3 << GRF_GPIO2BL5_SEL_SHIFT,
  89         GRF_I2C2_SDA            = 1,
  90
  91         GRF_GPIO2BL6_SEL_SHIFT  = 12,
  92         GRF_GPIO2BL6_SEL_MASK   = 3 << GRF_GPIO2BL6_SEL_SHIFT,
  93         GRF_I2C2_SCL            = 1,
  94
  95         /* GRF_GPIO2D_IOMUX */
  96         GRF_GPIO2D0_SEL_SHIFT   = 0,
  97         GRF_GPIO2D0_SEL_MASK    = 3 << GRF_GPIO2D0_SEL_SHIFT,
  98         GRF_I2C0_SCL            = 1,
  99
 100         GRF_GPIO2D1_SEL_SHIFT   = 2,
 101         GRF_GPIO2D1_SEL_MASK    = 3 << GRF_GPIO2D1_SEL_SHIFT,
 102         GRF_I2C0_SDA            = 1,
 103
 104         GRF_GPIO2D4_SEL_SHIFT   = 8,
 105         GRF_GPIO2D4_SEL_MASK    = 0xff << GRF_GPIO2D4_SEL_SHIFT,
 106         GRF_EMMC_DATA123        = 0xaa,
 107
 108         /* GRF_GPIO3C_IOMUX */
 109         GRF_GPIO3C0_SEL_SHIFT   = 0,
 110         GRF_GPIO3C0_SEL_MASK    = 0x3fff << GRF_GPIO3C0_SEL_SHIFT,
 111         GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD       = 0x2aaa,
 112
 113         /* GRF_COM_IOMUX */
 114         GRF_UART2_IOMUX_SEL_SHIFT       = 0,
 115         GRF_UART2_IOMUX_SEL_MASK        = 3 << GRF_UART2_IOMUX_SEL_SHIFT,
 116         GRF_UART2_IOMUX_SEL_M0          = 0,
 117         GRF_UART2_IOMUX_SEL_M1,
 118
 119         GRF_SPI_IOMUX_SEL_SHIFT = 4,
 120         GRF_SPI_IOMUX_SEL_MASK  = 3 << GRF_SPI_IOMUX_SEL_SHIFT,
 121         GRF_SPI_IOMUX_SEL_M0    = 0,
 122         GRF_SPI_IOMUX_SEL_M1,
 123         GRF_SPI_IOMUX_SEL_M2,
 124
 125         GRF_CARD_IOMUX_SEL_SHIFT        = 7,
 126         GRF_CARD_IOMUX_SEL_MASK         = 1 << GRF_CARD_IOMUX_SEL_SHIFT,
 127         GRF_CARD_IOMUX_SEL_M0           = 0,
 128         GRF_CARD_IOMUX_SEL_M1,
 129 };
 130
 131 static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id)
 132 {
 133         switch (pwm_id) {
 134         case PERIPH_ID_PWM0:
 135                 rk_clrsetreg(&grf->gpio2a_iomux,
 136                              GRF_GPIO2A4_SEL_MASK,
 137                              GRF_PWM_0 << GRF_GPIO2A4_SEL_SHIFT);
 138                 break;
 139         case PERIPH_ID_PWM1:
 140                 rk_clrsetreg(&grf->gpio2a_iomux,
 141                              GRF_GPIO2A5_SEL_MASK,
 142                              GRF_PWM_1 << GRF_GPIO2A5_SEL_SHIFT);
 143                 break;
 144         case PERIPH_ID_PWM2:
 145                 rk_clrsetreg(&grf->gpio2a_iomux,
 146                              GRF_GPIO2A6_SEL_MASK,
 147                              GRF_PWM_2 << GRF_GPIO2A6_SEL_SHIFT);
 148                 break;
 149         case PERIPH_ID_PWM3:
 150                 rk_clrsetreg(&grf->gpio2a_iomux,
 151                              GRF_GPIO2A2_SEL_MASK,
 152                              GRF_PWM_IR << GRF_GPIO2A2_SEL_SHIFT);
 153                 break;
 154         default:
 155                 debug("pwm id = %d iomux error!\n", pwm_id);
 156                 break;
 157         }
 158 }
 159
 160 static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id)
 161 {
 162         switch (i2c_id) {
 163         case PERIPH_ID_I2C0:
 164                 rk_clrsetreg(&grf->gpio2d_iomux,
 165                              GRF_GPIO2D0_SEL_MASK | GRF_GPIO2D1_SEL_MASK,
 166                              GRF_I2C0_SCL << GRF_GPIO2D0_SEL_SHIFT
 167                              | GRF_I2C0_SDA << GRF_GPIO2D1_SEL_SHIFT);
 168                 break;
 169         case PERIPH_ID_I2C1:
 170                 rk_clrsetreg(&grf->gpio2a_iomux,
 171                              GRF_GPIO2A4_SEL_MASK | GRF_GPIO2A5_SEL_MASK,
 172                              GRF_I2C1_SCL << GRF_GPIO2A5_SEL_SHIFT
 173                              | GRF_I2C1_SDA << GRF_GPIO2A4_SEL_SHIFT);
 174                 break;
 175         case PERIPH_ID_I2C2:
 176                 rk_clrsetreg(&grf->gpio2bl_iomux,
 177                              GRF_GPIO2BL5_SEL_MASK | GRF_GPIO2BL6_SEL_MASK,
 178                              GRF_I2C2_SCL << GRF_GPIO2BL6_SEL_SHIFT
 179                              | GRF_I2C2_SDA << GRF_GPIO2BL6_SEL_SHIFT);
 180                 break;
 181         case PERIPH_ID_I2C3:
 182                 rk_clrsetreg(&grf->gpio0a_iomux,
 183                              GRF_GPIO0A5_SEL_MASK | GRF_GPIO0A6_SEL_MASK,
 184                              GRF_I2C3_SCL << GRF_GPIO0A5_SEL_SHIFT
 185                              | GRF_I2C3_SDA << GRF_GPIO0A6_SEL_SHIFT);
 186                 break;
 187         default:
 188                 debug("i2c id = %d iomux error!\n", i2c_id);
 189                 break;
 190         }
 191 }
 192
 193 static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id)
 194 {
 195         switch (lcd_id) {
 196         case PERIPH_ID_LCDC0:
 197                 break;
 198         default:
 199                 debug("lcdc id = %d iomux error!\n", lcd_id);
 200                 break;
 201         }
 202 }
 203
 204 static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf,
 205                                      enum periph_id spi_id, int cs)
 206 {
 207         rk_clrsetreg(&grf->com_iomux,
 208                      GRF_SPI_IOMUX_SEL_MASK,
 209                      GRF_SPI_IOMUX_SEL_M0 << GRF_SPI_IOMUX_SEL_SHIFT);
 210
 211         switch (spi_id) {
 212         case PERIPH_ID_SPI0:
 213                 switch (cs) {
 214                 case 0:
 215                         rk_clrsetreg(&grf->gpio2bl_iomux,
 216                                      GRF_GPIO2BL3_SEL_MASK,
 217                                      GRF_SPI_CSN0_M0 << GRF_GPIO2BL3_SEL_SHIFT);
 218                         break;
 219                 case 1:
 220                         rk_clrsetreg(&grf->gpio2bl_iomux,
 221                                      GRF_GPIO2BL4_SEL_MASK,
 222                                      GRF_SPI_CSN1_M0 << GRF_GPIO2BL4_SEL_SHIFT);
 223                         break;
 224                 default:
 225                         goto err;
 226                 }
 227                 rk_clrsetreg(&grf->gpio2bl_iomux,
 228                              GRF_GPIO2BL0_SEL_MASK,
 229                              GRF_SPI_CLK_TX_RX_M0 << GRF_GPIO2BL0_SEL_SHIFT);
 230                 break;
 231         default:
 232                 goto err;
 233         }
 234
 235         return 0;
 236 err:
 237         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 238         return -ENOENT;
 239 }
 240
 241 static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id)
 242 {
 243         switch (uart_id) {
 244         case PERIPH_ID_UART2:
 245                 break;
 246                 /* uart2 iomux select m1 */
 247                 rk_clrsetreg(&grf->com_iomux,
 248                              GRF_UART2_IOMUX_SEL_MASK,
 249                              GRF_UART2_IOMUX_SEL_M1
 250                              << GRF_UART2_IOMUX_SEL_SHIFT);
 251                 rk_clrsetreg(&grf->gpio2a_iomux,
 252                              GRF_GPIO2A0_SEL_MASK | GRF_GPIO2A1_SEL_MASK,
 253                              GRF_UART2_TX_M1 << GRF_GPIO2A0_SEL_SHIFT |
 254                              GRF_UART2_RX_M1 << GRF_GPIO2A1_SEL_SHIFT);
 255                 break;
 256         case PERIPH_ID_UART0:
 257         case PERIPH_ID_UART1:
 258         case PERIPH_ID_UART3:
 259         case PERIPH_ID_UART4:
 260         default:
 261                 debug("uart id = %d iomux error!\n", uart_id);
 262                 break;
 263         }
 264 }
 265
 266 static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
 267                                         int mmc_id)
 268 {
 269         switch (mmc_id) {
 270         case PERIPH_ID_EMMC:
 271                 rk_clrsetreg(&grf->gpio0a_iomux,
 272                              GRF_GPIO0A7_SEL_MASK,
 273                              GRF_EMMC_DATA0 << GRF_GPIO0A7_SEL_SHIFT);
 274                 rk_clrsetreg(&grf->gpio2d_iomux,
 275                              GRF_GPIO2D4_SEL_MASK,
 276                              GRF_EMMC_DATA123 << GRF_GPIO2D4_SEL_SHIFT);
 277                 rk_clrsetreg(&grf->gpio3c_iomux,
 278                              GRF_GPIO3C0_SEL_MASK,
 279                              GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD
 280                              << GRF_GPIO3C0_SEL_SHIFT);
 281                 break;
 282         case PERIPH_ID_SDCARD:
 283                 /* sdcard iomux select m0 */
 284                 rk_clrsetreg(&grf->com_iomux,
 285                              GRF_CARD_IOMUX_SEL_MASK,
 286                              GRF_CARD_IOMUX_SEL_M0 << GRF_CARD_IOMUX_SEL_SHIFT);
 287                 rk_clrsetreg(&grf->gpio2a_iomux,
 288                              GRF_GPIO2A7_SEL_MASK,
 289                              GRF_CARD_PWR_EN_M0 << GRF_GPIO2A7_SEL_SHIFT);
 290                 rk_clrsetreg(&grf->gpio1a_iomux,
 291                              GRF_GPIO1A0_SEL_MASK,
 292                              GRF_CARD_DATA_CLK_CMD_DETN
 293                              << GRF_GPIO1A0_SEL_SHIFT);
 294                 break;
 295         default:
 296                 debug("mmc id = %d iomux error!\n", mmc_id);
 297                 break;
 298         }
 299 }
 300
 301 static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags)
 302 {
 303         struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
 304
 305         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 306         switch (func) {
 307         case PERIPH_ID_PWM0:
 308         case PERIPH_ID_PWM1:
 309         case PERIPH_ID_PWM2:
 310         case PERIPH_ID_PWM3:
 311                 pinctrl_rk3328_pwm_config(priv->grf, func);
 312                 break;
 313         case PERIPH_ID_I2C0:
 314         case PERIPH_ID_I2C1:
 315         case PERIPH_ID_I2C2:
 316         case PERIPH_ID_I2C3:
 317                 pinctrl_rk3328_i2c_config(priv->grf, func);
 318                 break;
 319         case PERIPH_ID_SPI0:
 320                 pinctrl_rk3328_spi_config(priv->grf, func, flags);
 321                 break;
 322         case PERIPH_ID_UART0:
 323         case PERIPH_ID_UART1:
 324         case PERIPH_ID_UART2:
 325         case PERIPH_ID_UART3:
 326         case PERIPH_ID_UART4:
 327                 pinctrl_rk3328_uart_config(priv->grf, func);
 328                 break;
 329         case PERIPH_ID_LCDC0:
 330         case PERIPH_ID_LCDC1:
 331                 pinctrl_rk3328_lcdc_config(priv->grf, func);
 332                 break;
 333         case PERIPH_ID_SDMMC0:
 334         case PERIPH_ID_SDMMC1:
 335                 pinctrl_rk3328_sdmmc_config(priv->grf, func);
 336                 break;
 337         default:
 338                 return -EINVAL;
 339         }
 340
 341         return 0;
 342 }
 343
 344 static int rk3328_pinctrl_get_periph_id(struct udevice *dev,
 345                                         struct udevice *periph)
 346 {
 347         u32 cell[3];
 348         int ret;
 349
 350         ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
 351                                    "interrupts", cell, ARRAY_SIZE(cell));
 352         if (ret < 0)
 353                 return -EINVAL;
 354
 355         switch (cell[1]) {
 356         case 49:
 357                 return PERIPH_ID_SPI0;
 358         case 50:
 359                 return PERIPH_ID_PWM0;
 360         case 36:
 361                 return PERIPH_ID_I2C0;
 362         case 37: /* Note strange order */
 363                 return PERIPH_ID_I2C1;
 364         case 38:
 365                 return PERIPH_ID_I2C2;
 366         case 39:
 367                 return PERIPH_ID_I2C3;
 368         case 12:
 369                 return PERIPH_ID_SDCARD;
 370         case 14:
 371                 return PERIPH_ID_EMMC;
 372         }
 373
 374         return -ENOENT;
 375 }
 376
 377 static int rk3328_pinctrl_set_state_simple(struct udevice *dev,
 378                                            struct udevice *periph)
 379 {
 380         int func;
 381
 382         func = rk3328_pinctrl_get_periph_id(dev, periph);
 383         if (func < 0)
 384                 return func;
 385
 386         return rk3328_pinctrl_request(dev, func, 0);
 387 }
 388
 389 static struct pinctrl_ops rk3328_pinctrl_ops = {
 390         .set_state_simple       = rk3328_pinctrl_set_state_simple,
 391         .request        = rk3328_pinctrl_request,
 392         .get_periph_id  = rk3328_pinctrl_get_periph_id,
 393 };
 394
 395 static int rk3328_pinctrl_probe(struct udevice *dev)
 396 {
 397         struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
 398         int ret = 0;
 399
 400         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 401         debug("%s: grf=%p\n", __func__, priv->grf);
 402
 403         return ret;
 404 }
 405
 406 static const struct udevice_id rk3328_pinctrl_ids[] = {
 407         { .compatible = "rockchip,rk3328-pinctrl" },
 408         { }
 409 };
 410
 411 U_BOOT_DRIVER(pinctrl_rk3328) = {
 412         .name           = "rockchip_rk3328_pinctrl",
 413         .id             = UCLASS_PINCTRL,
 414         .of_match       = rk3328_pinctrl_ids,
 415         .priv_auto_alloc_size = sizeof(struct rk3328_pinctrl_priv),
 416         .ops            = &rk3328_pinctrl_ops,
 417         .bind           = dm_scan_fdt_dev,
 418         .probe          = rk3328_pinctrl_probe,
 419 };