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Merge branch 'master' of git://git.denx.de/u-boot-microblaze
[people/ms/u-boot.git] / drivers / qe / uec.c
1 /*
2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
3 *
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22 #include "common.h"
23 #include "net.h"
24 #include "malloc.h"
25 #include "asm/errno.h"
26 #include "asm/io.h"
27 #include "asm/immap_qe.h"
28 #include "qe.h"
29 #include "uccf.h"
30 #include "uec.h"
31 #include "uec_phy.h"
32 #include "miiphy.h"
33
34 /* Default UTBIPAR SMI address */
35 #ifndef CONFIG_UTBIPAR_INIT_TBIPA
36 #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
37 #endif
38
39 static uec_info_t uec_info[] = {
40 #ifdef CONFIG_UEC_ETH1
41 STD_UEC_INFO(1), /* UEC1 */
42 #endif
43 #ifdef CONFIG_UEC_ETH2
44 STD_UEC_INFO(2), /* UEC2 */
45 #endif
46 #ifdef CONFIG_UEC_ETH3
47 STD_UEC_INFO(3), /* UEC3 */
48 #endif
49 #ifdef CONFIG_UEC_ETH4
50 STD_UEC_INFO(4), /* UEC4 */
51 #endif
52 #ifdef CONFIG_UEC_ETH5
53 STD_UEC_INFO(5), /* UEC5 */
54 #endif
55 #ifdef CONFIG_UEC_ETH6
56 STD_UEC_INFO(6), /* UEC6 */
57 #endif
58 #ifdef CONFIG_UEC_ETH7
59 STD_UEC_INFO(7), /* UEC7 */
60 #endif
61 #ifdef CONFIG_UEC_ETH8
62 STD_UEC_INFO(8), /* UEC8 */
63 #endif
64 };
65
66 #define MAXCONTROLLERS (8)
67
68 static struct eth_device *devlist[MAXCONTROLLERS];
69
70 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
71 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
72
73 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
74 {
75 uec_t *uec_regs;
76 u32 maccfg1;
77
78 if (!uec) {
79 printf("%s: uec not initial\n", __FUNCTION__);
80 return -EINVAL;
81 }
82 uec_regs = uec->uec_regs;
83
84 maccfg1 = in_be32(&uec_regs->maccfg1);
85
86 if (mode & COMM_DIR_TX) {
87 maccfg1 |= MACCFG1_ENABLE_TX;
88 out_be32(&uec_regs->maccfg1, maccfg1);
89 uec->mac_tx_enabled = 1;
90 }
91
92 if (mode & COMM_DIR_RX) {
93 maccfg1 |= MACCFG1_ENABLE_RX;
94 out_be32(&uec_regs->maccfg1, maccfg1);
95 uec->mac_rx_enabled = 1;
96 }
97
98 return 0;
99 }
100
101 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
102 {
103 uec_t *uec_regs;
104 u32 maccfg1;
105
106 if (!uec) {
107 printf("%s: uec not initial\n", __FUNCTION__);
108 return -EINVAL;
109 }
110 uec_regs = uec->uec_regs;
111
112 maccfg1 = in_be32(&uec_regs->maccfg1);
113
114 if (mode & COMM_DIR_TX) {
115 maccfg1 &= ~MACCFG1_ENABLE_TX;
116 out_be32(&uec_regs->maccfg1, maccfg1);
117 uec->mac_tx_enabled = 0;
118 }
119
120 if (mode & COMM_DIR_RX) {
121 maccfg1 &= ~MACCFG1_ENABLE_RX;
122 out_be32(&uec_regs->maccfg1, maccfg1);
123 uec->mac_rx_enabled = 0;
124 }
125
126 return 0;
127 }
128
129 static int uec_graceful_stop_tx(uec_private_t *uec)
130 {
131 ucc_fast_t *uf_regs;
132 u32 cecr_subblock;
133 u32 ucce;
134
135 if (!uec || !uec->uccf) {
136 printf("%s: No handle passed.\n", __FUNCTION__);
137 return -EINVAL;
138 }
139
140 uf_regs = uec->uccf->uf_regs;
141
142 /* Clear the grace stop event */
143 out_be32(&uf_regs->ucce, UCCE_GRA);
144
145 /* Issue host command */
146 cecr_subblock =
147 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
148 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
149 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
150
151 /* Wait for command to complete */
152 do {
153 ucce = in_be32(&uf_regs->ucce);
154 } while (! (ucce & UCCE_GRA));
155
156 uec->grace_stopped_tx = 1;
157
158 return 0;
159 }
160
161 static int uec_graceful_stop_rx(uec_private_t *uec)
162 {
163 u32 cecr_subblock;
164 u8 ack;
165
166 if (!uec) {
167 printf("%s: No handle passed.\n", __FUNCTION__);
168 return -EINVAL;
169 }
170
171 if (!uec->p_rx_glbl_pram) {
172 printf("%s: No init rx global parameter\n", __FUNCTION__);
173 return -EINVAL;
174 }
175
176 /* Clear acknowledge bit */
177 ack = uec->p_rx_glbl_pram->rxgstpack;
178 ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
179 uec->p_rx_glbl_pram->rxgstpack = ack;
180
181 /* Keep issuing cmd and checking ack bit until it is asserted */
182 do {
183 /* Issue host command */
184 cecr_subblock =
185 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
186 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
187 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
188 ack = uec->p_rx_glbl_pram->rxgstpack;
189 } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
190
191 uec->grace_stopped_rx = 1;
192
193 return 0;
194 }
195
196 static int uec_restart_tx(uec_private_t *uec)
197 {
198 u32 cecr_subblock;
199
200 if (!uec || !uec->uec_info) {
201 printf("%s: No handle passed.\n", __FUNCTION__);
202 return -EINVAL;
203 }
204
205 cecr_subblock =
206 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
207 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
208 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
209
210 uec->grace_stopped_tx = 0;
211
212 return 0;
213 }
214
215 static int uec_restart_rx(uec_private_t *uec)
216 {
217 u32 cecr_subblock;
218
219 if (!uec || !uec->uec_info) {
220 printf("%s: No handle passed.\n", __FUNCTION__);
221 return -EINVAL;
222 }
223
224 cecr_subblock =
225 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
226 qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
227 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
228
229 uec->grace_stopped_rx = 0;
230
231 return 0;
232 }
233
234 static int uec_open(uec_private_t *uec, comm_dir_e mode)
235 {
236 ucc_fast_private_t *uccf;
237
238 if (!uec || !uec->uccf) {
239 printf("%s: No handle passed.\n", __FUNCTION__);
240 return -EINVAL;
241 }
242 uccf = uec->uccf;
243
244 /* check if the UCC number is in range. */
245 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
246 printf("%s: ucc_num out of range.\n", __FUNCTION__);
247 return -EINVAL;
248 }
249
250 /* Enable MAC */
251 uec_mac_enable(uec, mode);
252
253 /* Enable UCC fast */
254 ucc_fast_enable(uccf, mode);
255
256 /* RISC microcode start */
257 if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
258 uec_restart_tx(uec);
259 }
260 if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
261 uec_restart_rx(uec);
262 }
263
264 return 0;
265 }
266
267 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
268 {
269 ucc_fast_private_t *uccf;
270
271 if (!uec || !uec->uccf) {
272 printf("%s: No handle passed.\n", __FUNCTION__);
273 return -EINVAL;
274 }
275 uccf = uec->uccf;
276
277 /* check if the UCC number is in range. */
278 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
279 printf("%s: ucc_num out of range.\n", __FUNCTION__);
280 return -EINVAL;
281 }
282 /* Stop any transmissions */
283 if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
284 uec_graceful_stop_tx(uec);
285 }
286 /* Stop any receptions */
287 if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
288 uec_graceful_stop_rx(uec);
289 }
290
291 /* Disable the UCC fast */
292 ucc_fast_disable(uec->uccf, mode);
293
294 /* Disable the MAC */
295 uec_mac_disable(uec, mode);
296
297 return 0;
298 }
299
300 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
301 {
302 uec_t *uec_regs;
303 u32 maccfg2;
304
305 if (!uec) {
306 printf("%s: uec not initial\n", __FUNCTION__);
307 return -EINVAL;
308 }
309 uec_regs = uec->uec_regs;
310
311 if (duplex == DUPLEX_HALF) {
312 maccfg2 = in_be32(&uec_regs->maccfg2);
313 maccfg2 &= ~MACCFG2_FDX;
314 out_be32(&uec_regs->maccfg2, maccfg2);
315 }
316
317 if (duplex == DUPLEX_FULL) {
318 maccfg2 = in_be32(&uec_regs->maccfg2);
319 maccfg2 |= MACCFG2_FDX;
320 out_be32(&uec_regs->maccfg2, maccfg2);
321 }
322
323 return 0;
324 }
325
326 static int uec_set_mac_if_mode(uec_private_t *uec,
327 enet_interface_type_e if_mode, int speed)
328 {
329 enet_interface_type_e enet_if_mode;
330 uec_info_t *uec_info;
331 uec_t *uec_regs;
332 u32 upsmr;
333 u32 maccfg2;
334
335 if (!uec) {
336 printf("%s: uec not initial\n", __FUNCTION__);
337 return -EINVAL;
338 }
339
340 uec_info = uec->uec_info;
341 uec_regs = uec->uec_regs;
342 enet_if_mode = if_mode;
343
344 maccfg2 = in_be32(&uec_regs->maccfg2);
345 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
346
347 upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
348 upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
349
350 switch (speed) {
351 case 10:
352 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
353 switch (enet_if_mode) {
354 case MII:
355 break;
356 case RGMII:
357 upsmr |= (UPSMR_RPM | UPSMR_R10M);
358 break;
359 case RMII:
360 upsmr |= (UPSMR_R10M | UPSMR_RMM);
361 break;
362 default:
363 return -EINVAL;
364 break;
365 }
366 break;
367 case 100:
368 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
369 switch (enet_if_mode) {
370 case MII:
371 break;
372 case RGMII:
373 upsmr |= UPSMR_RPM;
374 break;
375 case RMII:
376 upsmr |= UPSMR_RMM;
377 break;
378 default:
379 return -EINVAL;
380 break;
381 }
382 break;
383 case 1000:
384 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
385 switch (enet_if_mode) {
386 case GMII:
387 break;
388 case TBI:
389 upsmr |= UPSMR_TBIM;
390 break;
391 case RTBI:
392 upsmr |= (UPSMR_RPM | UPSMR_TBIM);
393 break;
394 case RGMII_RXID:
395 case RGMII_ID:
396 case RGMII:
397 upsmr |= UPSMR_RPM;
398 break;
399 case SGMII:
400 upsmr |= UPSMR_SGMM;
401 break;
402 default:
403 return -EINVAL;
404 break;
405 }
406 break;
407 default:
408 return -EINVAL;
409 break;
410 }
411
412 out_be32(&uec_regs->maccfg2, maccfg2);
413 out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
414
415 return 0;
416 }
417
418 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
419 {
420 uint timeout = 0x1000;
421 u32 miimcfg = 0;
422
423 miimcfg = in_be32(&uec_mii_regs->miimcfg);
424 miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
425 out_be32(&uec_mii_regs->miimcfg, miimcfg);
426
427 /* Wait until the bus is free */
428 while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
429 if (timeout <= 0) {
430 printf("%s: The MII Bus is stuck!", __FUNCTION__);
431 return -ETIMEDOUT;
432 }
433
434 return 0;
435 }
436
437 static int init_phy(struct eth_device *dev)
438 {
439 uec_private_t *uec;
440 uec_mii_t *umii_regs;
441 struct uec_mii_info *mii_info;
442 struct phy_info *curphy;
443 int err;
444
445 uec = (uec_private_t *)dev->priv;
446 umii_regs = uec->uec_mii_regs;
447
448 uec->oldlink = 0;
449 uec->oldspeed = 0;
450 uec->oldduplex = -1;
451
452 mii_info = malloc(sizeof(*mii_info));
453 if (!mii_info) {
454 printf("%s: Could not allocate mii_info", dev->name);
455 return -ENOMEM;
456 }
457 memset(mii_info, 0, sizeof(*mii_info));
458
459 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
460 mii_info->speed = SPEED_1000;
461 } else {
462 mii_info->speed = SPEED_100;
463 }
464
465 mii_info->duplex = DUPLEX_FULL;
466 mii_info->pause = 0;
467 mii_info->link = 1;
468
469 mii_info->advertising = (ADVERTISED_10baseT_Half |
470 ADVERTISED_10baseT_Full |
471 ADVERTISED_100baseT_Half |
472 ADVERTISED_100baseT_Full |
473 ADVERTISED_1000baseT_Full);
474 mii_info->autoneg = 1;
475 mii_info->mii_id = uec->uec_info->phy_address;
476 mii_info->dev = dev;
477
478 mii_info->mdio_read = &uec_read_phy_reg;
479 mii_info->mdio_write = &uec_write_phy_reg;
480
481 uec->mii_info = mii_info;
482
483 qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
484
485 if (init_mii_management_configuration(umii_regs)) {
486 printf("%s: The MII Bus is stuck!", dev->name);
487 err = -1;
488 goto bus_fail;
489 }
490
491 /* get info for this PHY */
492 curphy = uec_get_phy_info(uec->mii_info);
493 if (!curphy) {
494 printf("%s: No PHY found", dev->name);
495 err = -1;
496 goto no_phy;
497 }
498
499 mii_info->phyinfo = curphy;
500
501 /* Run the commands which initialize the PHY */
502 if (curphy->init) {
503 err = curphy->init(uec->mii_info);
504 if (err)
505 goto phy_init_fail;
506 }
507
508 return 0;
509
510 phy_init_fail:
511 no_phy:
512 bus_fail:
513 free(mii_info);
514 return err;
515 }
516
517 static void adjust_link(struct eth_device *dev)
518 {
519 uec_private_t *uec = (uec_private_t *)dev->priv;
520 uec_t *uec_regs;
521 struct uec_mii_info *mii_info = uec->mii_info;
522
523 extern void change_phy_interface_mode(struct eth_device *dev,
524 enet_interface_type_e mode, int speed);
525 uec_regs = uec->uec_regs;
526
527 if (mii_info->link) {
528 /* Now we make sure that we can be in full duplex mode.
529 * If not, we operate in half-duplex mode. */
530 if (mii_info->duplex != uec->oldduplex) {
531 if (!(mii_info->duplex)) {
532 uec_set_mac_duplex(uec, DUPLEX_HALF);
533 printf("%s: Half Duplex\n", dev->name);
534 } else {
535 uec_set_mac_duplex(uec, DUPLEX_FULL);
536 printf("%s: Full Duplex\n", dev->name);
537 }
538 uec->oldduplex = mii_info->duplex;
539 }
540
541 if (mii_info->speed != uec->oldspeed) {
542 enet_interface_type_e mode = \
543 uec->uec_info->enet_interface_type;
544 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
545 switch (mii_info->speed) {
546 case 1000:
547 break;
548 case 100:
549 printf ("switching to rgmii 100\n");
550 mode = RGMII;
551 break;
552 case 10:
553 printf ("switching to rgmii 10\n");
554 mode = RGMII;
555 break;
556 default:
557 printf("%s: Ack,Speed(%d)is illegal\n",
558 dev->name, mii_info->speed);
559 break;
560 }
561 }
562
563 /* change phy */
564 change_phy_interface_mode(dev, mode, mii_info->speed);
565 /* change the MAC interface mode */
566 uec_set_mac_if_mode(uec, mode, mii_info->speed);
567
568 printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
569 uec->oldspeed = mii_info->speed;
570 }
571
572 if (!uec->oldlink) {
573 printf("%s: Link is up\n", dev->name);
574 uec->oldlink = 1;
575 }
576
577 } else { /* if (mii_info->link) */
578 if (uec->oldlink) {
579 printf("%s: Link is down\n", dev->name);
580 uec->oldlink = 0;
581 uec->oldspeed = 0;
582 uec->oldduplex = -1;
583 }
584 }
585 }
586
587 static void phy_change(struct eth_device *dev)
588 {
589 uec_private_t *uec = (uec_private_t *)dev->priv;
590
591 /* Update the link, speed, duplex */
592 uec->mii_info->phyinfo->read_status(uec->mii_info);
593
594 /* Adjust the interface according to speed */
595 adjust_link(dev);
596 }
597
598 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
599
600 /*
601 * Find a device index from the devlist by name
602 *
603 * Returns:
604 * The index where the device is located, -1 on error
605 */
606 static int uec_miiphy_find_dev_by_name(const char *devname)
607 {
608 int i;
609
610 for (i = 0; i < MAXCONTROLLERS; i++) {
611 if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) {
612 break;
613 }
614 }
615
616 /* If device cannot be found, returns -1 */
617 if (i == MAXCONTROLLERS) {
618 debug ("%s: device %s not found in devlist\n", __FUNCTION__, devname);
619 i = -1;
620 }
621
622 return i;
623 }
624
625 /*
626 * Read a MII PHY register.
627 *
628 * Returns:
629 * 0 on success
630 */
631 static int uec_miiphy_read(const char *devname, unsigned char addr,
632 unsigned char reg, unsigned short *value)
633 {
634 int devindex = 0;
635
636 if (devname == NULL || value == NULL) {
637 debug("%s: NULL pointer given\n", __FUNCTION__);
638 } else {
639 devindex = uec_miiphy_find_dev_by_name(devname);
640 if (devindex >= 0) {
641 *value = uec_read_phy_reg(devlist[devindex], addr, reg);
642 }
643 }
644 return 0;
645 }
646
647 /*
648 * Write a MII PHY register.
649 *
650 * Returns:
651 * 0 on success
652 */
653 static int uec_miiphy_write(const char *devname, unsigned char addr,
654 unsigned char reg, unsigned short value)
655 {
656 int devindex = 0;
657
658 if (devname == NULL) {
659 debug("%s: NULL pointer given\n", __FUNCTION__);
660 } else {
661 devindex = uec_miiphy_find_dev_by_name(devname);
662 if (devindex >= 0) {
663 uec_write_phy_reg(devlist[devindex], addr, reg, value);
664 }
665 }
666 return 0;
667 }
668 #endif
669
670 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
671 {
672 uec_t *uec_regs;
673 u32 mac_addr1;
674 u32 mac_addr2;
675
676 if (!uec) {
677 printf("%s: uec not initial\n", __FUNCTION__);
678 return -EINVAL;
679 }
680
681 uec_regs = uec->uec_regs;
682
683 /* if a station address of 0x12345678ABCD, perform a write to
684 MACSTNADDR1 of 0xCDAB7856,
685 MACSTNADDR2 of 0x34120000 */
686
687 mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
688 (mac_addr[3] << 8) | (mac_addr[2]);
689 out_be32(&uec_regs->macstnaddr1, mac_addr1);
690
691 mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
692 out_be32(&uec_regs->macstnaddr2, mac_addr2);
693
694 return 0;
695 }
696
697 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
698 int *threads_num_ret)
699 {
700 int num_threads_numerica;
701
702 switch (threads_num) {
703 case UEC_NUM_OF_THREADS_1:
704 num_threads_numerica = 1;
705 break;
706 case UEC_NUM_OF_THREADS_2:
707 num_threads_numerica = 2;
708 break;
709 case UEC_NUM_OF_THREADS_4:
710 num_threads_numerica = 4;
711 break;
712 case UEC_NUM_OF_THREADS_6:
713 num_threads_numerica = 6;
714 break;
715 case UEC_NUM_OF_THREADS_8:
716 num_threads_numerica = 8;
717 break;
718 default:
719 printf("%s: Bad number of threads value.",
720 __FUNCTION__);
721 return -EINVAL;
722 }
723
724 *threads_num_ret = num_threads_numerica;
725
726 return 0;
727 }
728
729 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
730 {
731 uec_info_t *uec_info;
732 u32 end_bd;
733 u8 bmrx = 0;
734 int i;
735
736 uec_info = uec->uec_info;
737
738 /* Alloc global Tx parameter RAM page */
739 uec->tx_glbl_pram_offset = qe_muram_alloc(
740 sizeof(uec_tx_global_pram_t),
741 UEC_TX_GLOBAL_PRAM_ALIGNMENT);
742 uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
743 qe_muram_addr(uec->tx_glbl_pram_offset);
744
745 /* Zero the global Tx prameter RAM */
746 memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
747
748 /* Init global Tx parameter RAM */
749
750 /* TEMODER, RMON statistics disable, one Tx queue */
751 out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
752
753 /* SQPTR */
754 uec->send_q_mem_reg_offset = qe_muram_alloc(
755 sizeof(uec_send_queue_qd_t),
756 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
757 uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
758 qe_muram_addr(uec->send_q_mem_reg_offset);
759 out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
760
761 /* Setup the table with TxBDs ring */
762 end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
763 * SIZEOFBD;
764 out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
765 (u32)(uec->p_tx_bd_ring));
766 out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
767 end_bd);
768
769 /* Scheduler Base Pointer, we have only one Tx queue, no need it */
770 out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
771
772 /* TxRMON Base Pointer, TxRMON disable, we don't need it */
773 out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
774
775 /* TSTATE, global snooping, big endian, the CSB bus selected */
776 bmrx = BMR_INIT_VALUE;
777 out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
778
779 /* IPH_Offset */
780 for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
781 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
782 }
783
784 /* VTAG table */
785 for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
786 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
787 }
788
789 /* TQPTR */
790 uec->thread_dat_tx_offset = qe_muram_alloc(
791 num_threads_tx * sizeof(uec_thread_data_tx_t) +
792 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
793
794 uec->p_thread_data_tx = (uec_thread_data_tx_t *)
795 qe_muram_addr(uec->thread_dat_tx_offset);
796 out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
797 }
798
799 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
800 {
801 u8 bmrx = 0;
802 int i;
803 uec_82xx_address_filtering_pram_t *p_af_pram;
804
805 /* Allocate global Rx parameter RAM page */
806 uec->rx_glbl_pram_offset = qe_muram_alloc(
807 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
808 uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
809 qe_muram_addr(uec->rx_glbl_pram_offset);
810
811 /* Zero Global Rx parameter RAM */
812 memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
813
814 /* Init global Rx parameter RAM */
815 /* REMODER, Extended feature mode disable, VLAN disable,
816 LossLess flow control disable, Receive firmware statisic disable,
817 Extended address parsing mode disable, One Rx queues,
818 Dynamic maximum/minimum frame length disable, IP checksum check
819 disable, IP address alignment disable
820 */
821 out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
822
823 /* RQPTR */
824 uec->thread_dat_rx_offset = qe_muram_alloc(
825 num_threads_rx * sizeof(uec_thread_data_rx_t),
826 UEC_THREAD_DATA_ALIGNMENT);
827 uec->p_thread_data_rx = (uec_thread_data_rx_t *)
828 qe_muram_addr(uec->thread_dat_rx_offset);
829 out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
830
831 /* Type_or_Len */
832 out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
833
834 /* RxRMON base pointer, we don't need it */
835 out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
836
837 /* IntCoalescingPTR, we don't need it, no interrupt */
838 out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
839
840 /* RSTATE, global snooping, big endian, the CSB bus selected */
841 bmrx = BMR_INIT_VALUE;
842 out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
843
844 /* MRBLR */
845 out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
846
847 /* RBDQPTR */
848 uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
849 sizeof(uec_rx_bd_queues_entry_t) + \
850 sizeof(uec_rx_prefetched_bds_t),
851 UEC_RX_BD_QUEUES_ALIGNMENT);
852 uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
853 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
854
855 /* Zero it */
856 memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
857 sizeof(uec_rx_prefetched_bds_t));
858 out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
859 out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
860 (u32)uec->p_rx_bd_ring);
861
862 /* MFLR */
863 out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
864 /* MINFLR */
865 out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
866 /* MAXD1 */
867 out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
868 /* MAXD2 */
869 out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
870 /* ECAM_PTR */
871 out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
872 /* L2QT */
873 out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
874 /* L3QT */
875 for (i = 0; i < 8; i++) {
876 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
877 }
878
879 /* VLAN_TYPE */
880 out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
881 /* TCI */
882 out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
883
884 /* Clear PQ2 style address filtering hash table */
885 p_af_pram = (uec_82xx_address_filtering_pram_t *) \
886 uec->p_rx_glbl_pram->addressfiltering;
887
888 p_af_pram->iaddr_h = 0;
889 p_af_pram->iaddr_l = 0;
890 p_af_pram->gaddr_h = 0;
891 p_af_pram->gaddr_l = 0;
892 }
893
894 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
895 int thread_tx, int thread_rx)
896 {
897 uec_init_cmd_pram_t *p_init_enet_param;
898 u32 init_enet_param_offset;
899 uec_info_t *uec_info;
900 int i;
901 int snum;
902 u32 init_enet_offset;
903 u32 entry_val;
904 u32 command;
905 u32 cecr_subblock;
906
907 uec_info = uec->uec_info;
908
909 /* Allocate init enet command parameter */
910 uec->init_enet_param_offset = qe_muram_alloc(
911 sizeof(uec_init_cmd_pram_t), 4);
912 init_enet_param_offset = uec->init_enet_param_offset;
913 uec->p_init_enet_param = (uec_init_cmd_pram_t *)
914 qe_muram_addr(uec->init_enet_param_offset);
915
916 /* Zero init enet command struct */
917 memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
918
919 /* Init the command struct */
920 p_init_enet_param = uec->p_init_enet_param;
921 p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
922 p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
923 p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
924 p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
925 p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
926 p_init_enet_param->largestexternallookupkeysize = 0;
927
928 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
929 << ENET_INIT_PARAM_RGF_SHIFT;
930 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
931 << ENET_INIT_PARAM_TGF_SHIFT;
932
933 /* Init Rx global parameter pointer */
934 p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
935 (u32)uec_info->risc_rx;
936
937 /* Init Rx threads */
938 for (i = 0; i < (thread_rx + 1); i++) {
939 if ((snum = qe_get_snum()) < 0) {
940 printf("%s can not get snum\n", __FUNCTION__);
941 return -ENOMEM;
942 }
943
944 if (i==0) {
945 init_enet_offset = 0;
946 } else {
947 init_enet_offset = qe_muram_alloc(
948 sizeof(uec_thread_rx_pram_t),
949 UEC_THREAD_RX_PRAM_ALIGNMENT);
950 }
951
952 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
953 init_enet_offset | (u32)uec_info->risc_rx;
954 p_init_enet_param->rxthread[i] = entry_val;
955 }
956
957 /* Init Tx global parameter pointer */
958 p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
959 (u32)uec_info->risc_tx;
960
961 /* Init Tx threads */
962 for (i = 0; i < thread_tx; i++) {
963 if ((snum = qe_get_snum()) < 0) {
964 printf("%s can not get snum\n", __FUNCTION__);
965 return -ENOMEM;
966 }
967
968 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
969 UEC_THREAD_TX_PRAM_ALIGNMENT);
970
971 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
972 init_enet_offset | (u32)uec_info->risc_tx;
973 p_init_enet_param->txthread[i] = entry_val;
974 }
975
976 __asm__ __volatile__("sync");
977
978 /* Issue QE command */
979 command = QE_INIT_TX_RX;
980 cecr_subblock = ucc_fast_get_qe_cr_subblock(
981 uec->uec_info->uf_info.ucc_num);
982 qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
983 init_enet_param_offset);
984
985 return 0;
986 }
987
988 static int uec_startup(uec_private_t *uec)
989 {
990 uec_info_t *uec_info;
991 ucc_fast_info_t *uf_info;
992 ucc_fast_private_t *uccf;
993 ucc_fast_t *uf_regs;
994 uec_t *uec_regs;
995 int num_threads_tx;
996 int num_threads_rx;
997 u32 utbipar;
998 u32 length;
999 u32 align;
1000 qe_bd_t *bd;
1001 u8 *buf;
1002 int i;
1003
1004 if (!uec || !uec->uec_info) {
1005 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
1006 return -EINVAL;
1007 }
1008
1009 uec_info = uec->uec_info;
1010 uf_info = &(uec_info->uf_info);
1011
1012 /* Check if Rx BD ring len is illegal */
1013 if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
1014 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
1015 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1016 __FUNCTION__);
1017 return -EINVAL;
1018 }
1019
1020 /* Check if Tx BD ring len is illegal */
1021 if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
1022 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1023 __FUNCTION__);
1024 return -EINVAL;
1025 }
1026
1027 /* Check if MRBLR is illegal */
1028 if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) {
1029 printf("%s: max rx buffer length must be mutliple of 128.\n",
1030 __FUNCTION__);
1031 return -EINVAL;
1032 }
1033
1034 /* Both Rx and Tx are stopped */
1035 uec->grace_stopped_rx = 1;
1036 uec->grace_stopped_tx = 1;
1037
1038 /* Init UCC fast */
1039 if (ucc_fast_init(uf_info, &uccf)) {
1040 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1041 return -ENOMEM;
1042 }
1043
1044 /* Save uccf */
1045 uec->uccf = uccf;
1046
1047 /* Convert the Tx threads number */
1048 if (uec_convert_threads_num(uec_info->num_threads_tx,
1049 &num_threads_tx)) {
1050 return -EINVAL;
1051 }
1052
1053 /* Convert the Rx threads number */
1054 if (uec_convert_threads_num(uec_info->num_threads_rx,
1055 &num_threads_rx)) {
1056 return -EINVAL;
1057 }
1058
1059 uf_regs = uccf->uf_regs;
1060
1061 /* UEC register is following UCC fast registers */
1062 uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1063
1064 /* Save the UEC register pointer to UEC private struct */
1065 uec->uec_regs = uec_regs;
1066
1067 /* Init UPSMR, enable hardware statistics (UCC) */
1068 out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1069
1070 /* Init MACCFG1, flow control disable, disable Tx and Rx */
1071 out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1072
1073 /* Init MACCFG2, length check, MAC PAD and CRC enable */
1074 out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1075
1076 /* Setup MAC interface mode */
1077 uec_set_mac_if_mode(uec, uec_info->enet_interface_type, uec_info->speed);
1078
1079 /* Setup MII management base */
1080 #ifndef CONFIG_eTSEC_MDIO_BUS
1081 uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1082 #else
1083 uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1084 #endif
1085
1086 /* Setup MII master clock source */
1087 qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1088
1089 /* Setup UTBIPAR */
1090 utbipar = in_be32(&uec_regs->utbipar);
1091 utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1092
1093 /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
1094 * This frees up the remaining SMI addresses for use.
1095 */
1096 utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
1097 out_be32(&uec_regs->utbipar, utbipar);
1098
1099 /* Configure the TBI for SGMII operation */
1100 if ((uec->uec_info->enet_interface_type == SGMII) &&
1101 (uec->uec_info->speed == 1000)) {
1102 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1103 ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1104
1105 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1106 ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1107
1108 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1109 ENET_TBI_MII_CR, TBICR_SETTINGS);
1110 }
1111
1112 /* Allocate Tx BDs */
1113 length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1114 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1115 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1116 if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1117 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1118 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1119 }
1120
1121 align = UEC_TX_BD_RING_ALIGNMENT;
1122 uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1123 if (uec->tx_bd_ring_offset != 0) {
1124 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1125 & ~(align - 1));
1126 }
1127
1128 /* Zero all of Tx BDs */
1129 memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1130
1131 /* Allocate Rx BDs */
1132 length = uec_info->rx_bd_ring_len * SIZEOFBD;
1133 align = UEC_RX_BD_RING_ALIGNMENT;
1134 uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1135 if (uec->rx_bd_ring_offset != 0) {
1136 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1137 & ~(align - 1));
1138 }
1139
1140 /* Zero all of Rx BDs */
1141 memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1142
1143 /* Allocate Rx buffer */
1144 length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1145 align = UEC_RX_DATA_BUF_ALIGNMENT;
1146 uec->rx_buf_offset = (u32)malloc(length + align);
1147 if (uec->rx_buf_offset != 0) {
1148 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1149 & ~(align - 1));
1150 }
1151
1152 /* Zero all of the Rx buffer */
1153 memset((void *)(uec->rx_buf_offset), 0, length + align);
1154
1155 /* Init TxBD ring */
1156 bd = (qe_bd_t *)uec->p_tx_bd_ring;
1157 uec->txBd = bd;
1158
1159 for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1160 BD_DATA_CLEAR(bd);
1161 BD_STATUS_SET(bd, 0);
1162 BD_LENGTH_SET(bd, 0);
1163 bd ++;
1164 }
1165 BD_STATUS_SET((--bd), TxBD_WRAP);
1166
1167 /* Init RxBD ring */
1168 bd = (qe_bd_t *)uec->p_rx_bd_ring;
1169 uec->rxBd = bd;
1170 buf = uec->p_rx_buf;
1171 for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1172 BD_DATA_SET(bd, buf);
1173 BD_LENGTH_SET(bd, 0);
1174 BD_STATUS_SET(bd, RxBD_EMPTY);
1175 buf += MAX_RXBUF_LEN;
1176 bd ++;
1177 }
1178 BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1179
1180 /* Init global Tx parameter RAM */
1181 uec_init_tx_parameter(uec, num_threads_tx);
1182
1183 /* Init global Rx parameter RAM */
1184 uec_init_rx_parameter(uec, num_threads_rx);
1185
1186 /* Init ethernet Tx and Rx parameter command */
1187 if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1188 num_threads_rx)) {
1189 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1190 return -ENOMEM;
1191 }
1192
1193 return 0;
1194 }
1195
1196 static int uec_init(struct eth_device* dev, bd_t *bd)
1197 {
1198 uec_private_t *uec;
1199 int err, i;
1200 struct phy_info *curphy;
1201
1202 uec = (uec_private_t *)dev->priv;
1203
1204 if (uec->the_first_run == 0) {
1205 err = init_phy(dev);
1206 if (err) {
1207 printf("%s: Cannot initialize PHY, aborting.\n",
1208 dev->name);
1209 return err;
1210 }
1211
1212 curphy = uec->mii_info->phyinfo;
1213
1214 if (curphy->config_aneg) {
1215 err = curphy->config_aneg(uec->mii_info);
1216 if (err) {
1217 printf("%s: Can't negotiate PHY\n", dev->name);
1218 return err;
1219 }
1220 }
1221
1222 /* Give PHYs up to 5 sec to report a link */
1223 i = 50;
1224 do {
1225 err = curphy->read_status(uec->mii_info);
1226 if (!(((i-- > 0) && !uec->mii_info->link) || err))
1227 break;
1228 udelay(100000);
1229 } while (1);
1230
1231 if (err || i <= 0)
1232 printf("warning: %s: timeout on PHY link\n", dev->name);
1233
1234 adjust_link(dev);
1235 uec->the_first_run = 1;
1236 }
1237
1238 /* Set up the MAC address */
1239 if (dev->enetaddr[0] & 0x01) {
1240 printf("%s: MacAddress is multcast address\n",
1241 __FUNCTION__);
1242 return -1;
1243 }
1244 uec_set_mac_address(uec, dev->enetaddr);
1245
1246
1247 err = uec_open(uec, COMM_DIR_RX_AND_TX);
1248 if (err) {
1249 printf("%s: cannot enable UEC device\n", dev->name);
1250 return -1;
1251 }
1252
1253 phy_change(dev);
1254
1255 return (uec->mii_info->link ? 0 : -1);
1256 }
1257
1258 static void uec_halt(struct eth_device* dev)
1259 {
1260 uec_private_t *uec = (uec_private_t *)dev->priv;
1261 uec_stop(uec, COMM_DIR_RX_AND_TX);
1262 }
1263
1264 static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1265 {
1266 uec_private_t *uec;
1267 ucc_fast_private_t *uccf;
1268 volatile qe_bd_t *bd;
1269 u16 status;
1270 int i;
1271 int result = 0;
1272
1273 uec = (uec_private_t *)dev->priv;
1274 uccf = uec->uccf;
1275 bd = uec->txBd;
1276
1277 /* Find an empty TxBD */
1278 for (i = 0; bd->status & TxBD_READY; i++) {
1279 if (i > 0x100000) {
1280 printf("%s: tx buffer not ready\n", dev->name);
1281 return result;
1282 }
1283 }
1284
1285 /* Init TxBD */
1286 BD_DATA_SET(bd, buf);
1287 BD_LENGTH_SET(bd, len);
1288 status = bd->status;
1289 status &= BD_WRAP;
1290 status |= (TxBD_READY | TxBD_LAST);
1291 BD_STATUS_SET(bd, status);
1292
1293 /* Tell UCC to transmit the buffer */
1294 ucc_fast_transmit_on_demand(uccf);
1295
1296 /* Wait for buffer to be transmitted */
1297 for (i = 0; bd->status & TxBD_READY; i++) {
1298 if (i > 0x100000) {
1299 printf("%s: tx error\n", dev->name);
1300 return result;
1301 }
1302 }
1303
1304 /* Ok, the buffer be transimitted */
1305 BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1306 uec->txBd = bd;
1307 result = 1;
1308
1309 return result;
1310 }
1311
1312 static int uec_recv(struct eth_device* dev)
1313 {
1314 uec_private_t *uec = dev->priv;
1315 volatile qe_bd_t *bd;
1316 u16 status;
1317 u16 len;
1318 u8 *data;
1319
1320 bd = uec->rxBd;
1321 status = bd->status;
1322
1323 while (!(status & RxBD_EMPTY)) {
1324 if (!(status & RxBD_ERROR)) {
1325 data = BD_DATA(bd);
1326 len = BD_LENGTH(bd);
1327 NetReceive(data, len);
1328 } else {
1329 printf("%s: Rx error\n", dev->name);
1330 }
1331 status &= BD_CLEAN;
1332 BD_LENGTH_SET(bd, 0);
1333 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1334 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1335 status = bd->status;
1336 }
1337 uec->rxBd = bd;
1338
1339 return 1;
1340 }
1341
1342 int uec_initialize(bd_t *bis, uec_info_t *uec_info)
1343 {
1344 struct eth_device *dev;
1345 int i;
1346 uec_private_t *uec;
1347 int err;
1348
1349 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1350 if (!dev)
1351 return 0;
1352 memset(dev, 0, sizeof(struct eth_device));
1353
1354 /* Allocate the UEC private struct */
1355 uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1356 if (!uec) {
1357 return -ENOMEM;
1358 }
1359 memset(uec, 0, sizeof(uec_private_t));
1360
1361 /* Adjust uec_info */
1362 #if (MAX_QE_RISC == 4)
1363 uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
1364 uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
1365 #endif
1366
1367 devlist[uec_info->uf_info.ucc_num] = dev;
1368
1369 uec->uec_info = uec_info;
1370 uec->dev = dev;
1371
1372 sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num);
1373 dev->iobase = 0;
1374 dev->priv = (void *)uec;
1375 dev->init = uec_init;
1376 dev->halt = uec_halt;
1377 dev->send = uec_send;
1378 dev->recv = uec_recv;
1379
1380 /* Clear the ethnet address */
1381 for (i = 0; i < 6; i++)
1382 dev->enetaddr[i] = 0;
1383
1384 eth_register(dev);
1385
1386 err = uec_startup(uec);
1387 if (err) {
1388 printf("%s: Cannot configure net device, aborting.",dev->name);
1389 return err;
1390 }
1391
1392 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1393 miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
1394 #endif
1395
1396 return 1;
1397 }
1398
1399 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num)
1400 {
1401 int i;
1402
1403 for (i = 0; i < num; i++)
1404 uec_initialize(bis, &uecs[i]);
1405
1406 return 0;
1407 }
1408
1409 int uec_standard_init(bd_t *bis)
1410 {
1411 return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info));
1412 }
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