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1 /*
2 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <serial.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
16 struct arc_serial_regs {
17 unsigned int id0;
18 unsigned int id1;
19 unsigned int id2;
20 unsigned int id3;
21 unsigned int data;
22 unsigned int status;
23 unsigned int baudl;
24 unsigned int baudh;
25 };
26
27
28 struct arc_serial_platdata {
29 struct arc_serial_regs *reg;
30 unsigned int uartclk;
31 };
32
33 /* Bit definitions of STATUS register */
34 #define UART_RXEMPTY (1 << 5)
35 #define UART_OVERFLOW_ERR (1 << 1)
36 #define UART_TXEMPTY (1 << 7)
37
38 static int arc_serial_setbrg(struct udevice *dev, int baudrate)
39 {
40 struct arc_serial_platdata *plat = dev->platdata;
41 struct arc_serial_regs *const regs = plat->reg;
42 int arc_console_baud = gd->cpu_clk / (baudrate * 4) - 1;
43
44 writeb(arc_console_baud & 0xff, &regs->baudl);
45
46 #ifdef CONFIG_ARC
47 /*
48 * UART ISS(Instruction Set simulator) emulation has a subtle bug:
49 * A existing value of Baudh = 0 is used as a indication to startup
50 * it's internal state machine.
51 * Thus if baudh is set to 0, 2 times, it chokes.
52 * This happens with BAUD=115200 and the formaula above
53 * Until that is fixed, when running on ISS, we will set baudh to !0
54 */
55 if (gd->arch.running_on_hw)
56 writeb((arc_console_baud & 0xff00) >> 8, &regs->baudh);
57 else
58 writeb(1, &regs->baudh);
59 #else
60 writeb((arc_console_baud & 0xff00) >> 8, &regs->baudh);
61 #endif
62
63 return 0;
64 }
65
66 static int arc_serial_putc(struct udevice *dev, const char c)
67 {
68 struct arc_serial_platdata *plat = dev->platdata;
69 struct arc_serial_regs *const regs = plat->reg;
70
71 if (c == '\n')
72 arc_serial_putc(dev, '\r');
73
74 while (!(readb(&regs->status) & UART_TXEMPTY))
75 ;
76
77 writeb(c, &regs->data);
78
79 return 0;
80 }
81
82 static int arc_serial_tstc(struct arc_serial_regs *const regs)
83 {
84 return !(readb(&regs->status) & UART_RXEMPTY);
85 }
86
87 static int arc_serial_pending(struct udevice *dev, bool input)
88 {
89 struct arc_serial_platdata *plat = dev->platdata;
90 struct arc_serial_regs *const regs = plat->reg;
91 uint32_t status = readb(&regs->status);
92
93 if (input)
94 return status & UART_RXEMPTY ? 0 : 1;
95 else
96 return status & UART_TXEMPTY ? 0 : 1;
97 }
98
99 static int arc_serial_getc(struct udevice *dev)
100 {
101 struct arc_serial_platdata *plat = dev->platdata;
102 struct arc_serial_regs *const regs = plat->reg;
103
104 while (!arc_serial_tstc(regs))
105 ;
106
107 /* Check for overflow errors */
108 if (readb(&regs->status) & UART_OVERFLOW_ERR)
109 return 0;
110
111 return readb(&regs->data) & 0xFF;
112 }
113
114 static int arc_serial_probe(struct udevice *dev)
115 {
116 return 0;
117 }
118
119 static const struct dm_serial_ops arc_serial_ops = {
120 .putc = arc_serial_putc,
121 .pending = arc_serial_pending,
122 .getc = arc_serial_getc,
123 .setbrg = arc_serial_setbrg,
124 };
125
126 static const struct udevice_id arc_serial_ids[] = {
127 { .compatible = "snps,arc-uart" },
128 { }
129 };
130
131 static int arc_serial_ofdata_to_platdata(struct udevice *dev)
132 {
133 struct arc_serial_platdata *plat = dev_get_platdata(dev);
134 DECLARE_GLOBAL_DATA_PTR;
135
136 plat->reg = (struct arc_serial_regs *)fdtdec_get_addr(gd->fdt_blob,
137 dev->of_offset, "reg");
138 plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
139 "clock-frequency", 0);
140
141 return 0;
142 }
143
144 U_BOOT_DRIVER(serial_arc) = {
145 .name = "serial_arc",
146 .id = UCLASS_SERIAL,
147 .of_match = arc_serial_ids,
148 .ofdata_to_platdata = arc_serial_ofdata_to_platdata,
149 .probe = arc_serial_probe,
150 .ops = &arc_serial_ops,
151 .flags = DM_FLAG_PRE_RELOC,
152 };