drivers/serial/serial_lpuart.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <watchdog.h>
  10 #include <asm/io.h>
  11 #include <serial.h>
  12 #include <linux/compiler.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/clock.h>
  15
  16 #define US1_TDRE        (1 << 7)
  17 #define US1_RDRF        (1 << 5)
  18 #define US1_OR          (1 << 3)
  19 #define UC2_TE          (1 << 3)
  20 #define UC2_RE          (1 << 2)
  21 #define CFIFO_TXFLUSH   (1 << 7)
  22 #define CFIFO_RXFLUSH   (1 << 6)
  23 #define SFIFO_RXOF      (1 << 2)
  24 #define SFIFO_RXUF      (1 << 0)
  25
  26 #define STAT_LBKDIF     (1 << 31)
  27 #define STAT_RXEDGIF    (1 << 30)
  28 #define STAT_TDRE       (1 << 23)
  29 #define STAT_RDRF       (1 << 21)
  30 #define STAT_IDLE       (1 << 20)
  31 #define STAT_OR         (1 << 19)
  32 #define STAT_NF         (1 << 18)
  33 #define STAT_FE         (1 << 17)
  34 #define STAT_PF         (1 << 16)
  35 #define STAT_MA1F       (1 << 15)
  36 #define STAT_MA2F       (1 << 14)
  37 #define STAT_FLAGS      (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
  38                          STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
  39
  40 #define CTRL_TE         (1 << 19)
  41 #define CTRL_RE         (1 << 18)
  42
  43 #define FIFO_TXFE               0x80
  44 #define FIFO_RXFE               0x40
  45
  46 #define WATER_TXWATER_OFF       1
  47 #define WATER_RXWATER_OFF       16
  48
  49 DECLARE_GLOBAL_DATA_PTR;
  50
  51 struct lpuart_serial_platdata {
  52         struct lpuart_fsl *reg;
  53 };
  54
  55 #ifndef CONFIG_LPUART_32B_REG
  56 static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate)
  57 {
  58         u32 clk = mxc_get_clock(MXC_UART_CLK);
  59         u16 sbr;
  60
  61         sbr = (u16)(clk / (16 * baudrate));
  62
  63         /* place adjustment later - n/32 BRFA */
  64         __raw_writeb(sbr >> 8, &base->ubdh);
  65         __raw_writeb(sbr & 0xff, &base->ubdl);
  66 }
  67
  68 static int _lpuart_serial_getc(struct lpuart_fsl *base)
  69 {
  70         while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
  71                 WATCHDOG_RESET();
  72
  73         barrier();
  74
  75         return __raw_readb(&base->ud);
  76 }
  77
  78 static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c)
  79 {
  80         if (c == '\n')
  81                 _lpuart_serial_putc(base, '\r');
  82
  83         while (!(__raw_readb(&base->us1) & US1_TDRE))
  84                 WATCHDOG_RESET();
  85
  86         __raw_writeb(c, &base->ud);
  87 }
  88
  89 /* Test whether a character is in the RX buffer */
  90 static int _lpuart_serial_tstc(struct lpuart_fsl *base)
  91 {
  92         if (__raw_readb(&base->urcfifo) == 0)
  93                 return 0;
  94
  95         return 1;
  96 }
  97
  98 /*
  99  * Initialise the serial port with the given baudrate. The settings
 100  * are always 8 data bits, no parity, 1 stop bit, no start bits.
 101  */
 102 static int _lpuart_serial_init(struct lpuart_fsl *base)
 103 {
 104         u8 ctrl;
 105
 106         ctrl = __raw_readb(&base->uc2);
 107         ctrl &= ~UC2_RE;
 108         ctrl &= ~UC2_TE;
 109         __raw_writeb(ctrl, &base->uc2);
 110
 111         __raw_writeb(0, &base->umodem);
 112         __raw_writeb(0, &base->uc1);
 113
 114         /* Disable FIFO and flush buffer */
 115         __raw_writeb(0x0, &base->upfifo);
 116         __raw_writeb(0x0, &base->utwfifo);
 117         __raw_writeb(0x1, &base->urwfifo);
 118         __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
 119
 120         /* provide data bits, parity, stop bit, etc */
 121         _lpuart_serial_setbrg(base, gd->baudrate);
 122
 123         __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
 124
 125         return 0;
 126 }
 127
 128 static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
 129 {
 130         struct lpuart_serial_platdata *plat = dev->platdata;
 131         struct lpuart_fsl *reg = plat->reg;
 132
 133         _lpuart_serial_setbrg(reg, baudrate);
 134
 135         return 0;
 136 }
 137
 138 static int lpuart_serial_getc(struct udevice *dev)
 139 {
 140         struct lpuart_serial_platdata *plat = dev->platdata;
 141         struct lpuart_fsl *reg = plat->reg;
 142
 143         return _lpuart_serial_getc(reg);
 144 }
 145
 146 static int lpuart_serial_putc(struct udevice *dev, const char c)
 147 {
 148         struct lpuart_serial_platdata *plat = dev->platdata;
 149         struct lpuart_fsl *reg = plat->reg;
 150
 151         _lpuart_serial_putc(reg, c);
 152
 153         return 0;
 154 }
 155
 156 static int lpuart_serial_pending(struct udevice *dev, bool input)
 157 {
 158         struct lpuart_serial_platdata *plat = dev->platdata;
 159         struct lpuart_fsl *reg = plat->reg;
 160
 161         if (input)
 162                 return _lpuart_serial_tstc(reg);
 163         else
 164                 return __raw_readb(&reg->us1) & US1_TDRE ? 0 : 1;
 165 }
 166
 167 static int lpuart_serial_probe(struct udevice *dev)
 168 {
 169         struct lpuart_serial_platdata *plat = dev->platdata;
 170         struct lpuart_fsl *reg = plat->reg;
 171
 172         return _lpuart_serial_init(reg);
 173 }
 174 #else
 175
 176 static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate)
 177 {
 178         u32 clk = CONFIG_SYS_CLK_FREQ;
 179         u32 sbr;
 180
 181         sbr = (clk / (16 * baudrate));
 182
 183         /* place adjustment later - n/32 BRFA */
 184         out_be32(&base->baud, sbr);
 185 }
 186
 187 static int _lpuart32_serial_getc(struct lpuart_fsl *base)
 188 {
 189         u32 stat;
 190
 191         while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
 192                 out_be32(&base->stat, STAT_FLAGS);
 193                 WATCHDOG_RESET();
 194         }
 195
 196         return in_be32(&base->data) & 0x3ff;
 197 }
 198
 199 static void _lpuart32_serial_putc(struct lpuart_fsl *base, const char c)
 200 {
 201         if (c == '\n')
 202                 _lpuart32_serial_putc(base, '\r');
 203
 204         while (!(in_be32(&base->stat) & STAT_TDRE))
 205                 WATCHDOG_RESET();
 206
 207         out_be32(&base->data, c);
 208 }
 209
 210 /* Test whether a character is in the RX buffer */
 211 static int _lpuart32_serial_tstc(struct lpuart_fsl *base)
 212 {
 213         if ((in_be32(&base->water) >> 24) == 0)
 214                 return 0;
 215
 216         return 1;
 217 }
 218
 219 /*
 220  * Initialise the serial port with the given baudrate. The settings
 221  * are always 8 data bits, no parity, 1 stop bit, no start bits.
 222  */
 223 static int _lpuart32_serial_init(struct lpuart_fsl *base)
 224 {
 225         u8 ctrl;
 226
 227         ctrl = in_be32(&base->ctrl);
 228         ctrl &= ~CTRL_RE;
 229         ctrl &= ~CTRL_TE;
 230         out_be32(&base->ctrl, ctrl);
 231
 232         out_be32(&base->modir, 0);
 233         out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
 234
 235         out_be32(&base->match, 0);
 236
 237         /* provide data bits, parity, stop bit, etc */
 238         _lpuart32_serial_setbrg(base, gd->baudrate);
 239
 240         out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
 241
 242         return 0;
 243 }
 244
 245 static int lpuart32_serial_setbrg(struct udevice *dev, int baudrate)
 246 {
 247         struct lpuart_serial_platdata *plat = dev->platdata;
 248         struct lpuart_fsl *reg = plat->reg;
 249
 250         _lpuart32_serial_setbrg(reg, baudrate);
 251
 252         return 0;
 253 }
 254
 255 static int lpuart32_serial_getc(struct udevice *dev)
 256 {
 257         struct lpuart_serial_platdata *plat = dev->platdata;
 258         struct lpuart_fsl *reg = plat->reg;
 259
 260         return _lpuart32_serial_getc(reg);
 261 }
 262
 263 static int lpuart32_serial_putc(struct udevice *dev, const char c)
 264 {
 265         struct lpuart_serial_platdata *plat = dev->platdata;
 266         struct lpuart_fsl *reg = plat->reg;
 267
 268         _lpuart32_serial_putc(reg, c);
 269
 270         return 0;
 271 }
 272
 273 static int lpuart32_serial_pending(struct udevice *dev, bool input)
 274 {
 275         struct lpuart_serial_platdata *plat = dev->platdata;
 276         struct lpuart_fsl *reg = plat->reg;
 277
 278         if (input)
 279                 return _lpuart32_serial_tstc(reg);
 280         else
 281                 return in_be32(&reg->stat) & STAT_TDRE ? 0 : 1;
 282 }
 283
 284 static int lpuart32_serial_probe(struct udevice *dev)
 285 {
 286         struct lpuart_serial_platdata *plat = dev->platdata;
 287         struct lpuart_fsl *reg = plat->reg;
 288
 289         return _lpuart32_serial_init(reg);
 290 }
 291 #endif /* CONFIG_LPUART_32B_REG */
 292
 293 static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
 294 {
 295         struct lpuart_serial_platdata *plat = dev->platdata;
 296         fdt_addr_t addr;
 297
 298         addr = dev_get_addr(dev);
 299         if (addr == FDT_ADDR_T_NONE)
 300                 return -EINVAL;
 301
 302         plat->reg = (struct lpuart_fsl *)addr;
 303
 304         return 0;
 305 }
 306
 307 #ifndef CONFIG_LPUART_32B_REG
 308 static const struct dm_serial_ops lpuart_serial_ops = {
 309         .putc = lpuart_serial_putc,
 310         .pending = lpuart_serial_pending,
 311         .getc = lpuart_serial_getc,
 312         .setbrg = lpuart_serial_setbrg,
 313 };
 314
 315 static const struct udevice_id lpuart_serial_ids[] = {
 316         { .compatible = "fsl,vf610-lpuart" },
 317         { }
 318 };
 319
 320 U_BOOT_DRIVER(serial_lpuart) = {
 321         .name   = "serial_lpuart",
 322         .id     = UCLASS_SERIAL,
 323         .of_match = lpuart_serial_ids,
 324         .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
 325         .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
 326         .probe = lpuart_serial_probe,
 327         .ops    = &lpuart_serial_ops,
 328         .flags = DM_FLAG_PRE_RELOC,
 329 };
 330 #else /* CONFIG_LPUART_32B_REG */
 331 static const struct dm_serial_ops lpuart32_serial_ops = {
 332         .putc = lpuart32_serial_putc,
 333         .pending = lpuart32_serial_pending,
 334         .getc = lpuart32_serial_getc,
 335         .setbrg = lpuart32_serial_setbrg,
 336 };
 337
 338 static const struct udevice_id lpuart32_serial_ids[] = {
 339         { .compatible = "fsl,ls1021a-lpuart" },
 340         { }
 341 };
 342
 343 U_BOOT_DRIVER(serial_lpuart32) = {
 344         .name   = "serial_lpuart32",
 345         .id     = UCLASS_SERIAL,
 346         .of_match = lpuart32_serial_ids,
 347         .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
 348         .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
 349         .probe = lpuart32_serial_probe,
 350         .ops    = &lpuart32_serial_ops,
 351         .flags = DM_FLAG_PRE_RELOC,
 352 };
 353 #endif /* CONFIG_LPUART_32B_REG */