drivers/spi/mxs_spi.c

   1 /*
   2  * Freescale i.MX28 SPI driver
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  *
   9  * NOTE: This driver only supports the SPI-controller chipselects,
  10  *       GPIO driven chipselects are not supported.
  11  */
  12
  13 #include <common.h>
  14 #include <malloc.h>
  15 #include <spi.h>
  16 #include <asm/errno.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/imx-regs.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/imx-common/dma.h>
  22
  23 #define MXS_SPI_MAX_TIMEOUT     1000000
  24 #define MXS_SPI_PORT_OFFSET     0x2000
  25 #define MXS_SSP_CHIPSELECT_MASK         0x00300000
  26 #define MXS_SSP_CHIPSELECT_SHIFT        20
  27
  28 #define MXSSSP_SMALL_TRANSFER   512
  29
  30 struct mxs_spi_slave {
  31         struct spi_slave        slave;
  32         uint32_t                max_khz;
  33         uint32_t                mode;
  34         struct mxs_ssp_regs     *regs;
  35 };
  36
  37 static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
  38 {
  39         return container_of(slave, struct mxs_spi_slave, slave);
  40 }
  41
  42 void spi_init(void)
  43 {
  44 }
  45
  46 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  47 {
  48         /* MXS SPI: 4 ports and 3 chip selects maximum */
  49         if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
  50                 return 0;
  51         else
  52                 return 1;
  53 }
  54
  55 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  56                                   unsigned int max_hz, unsigned int mode)
  57 {
  58         struct mxs_spi_slave *mxs_slave;
  59         struct mxs_ssp_regs *ssp_regs;
  60         int reg;
  61
  62         if (!spi_cs_is_valid(bus, cs)) {
  63                 printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
  64                 return NULL;
  65         }
  66
  67         mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
  68         if (!mxs_slave)
  69                 return NULL;
  70
  71         if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
  72                 goto err_init;
  73
  74         mxs_slave->max_khz = max_hz / 1000;
  75         mxs_slave->mode = mode;
  76         mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
  77         ssp_regs = mxs_slave->regs;
  78
  79         reg = readl(&ssp_regs->hw_ssp_ctrl0);
  80         reg &= ~(MXS_SSP_CHIPSELECT_MASK);
  81         reg |= cs << MXS_SSP_CHIPSELECT_SHIFT;
  82
  83         writel(reg, &ssp_regs->hw_ssp_ctrl0);
  84         return &mxs_slave->slave;
  85
  86 err_init:
  87         free(mxs_slave);
  88         return NULL;
  89 }
  90
  91 void spi_free_slave(struct spi_slave *slave)
  92 {
  93         struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
  94         free(mxs_slave);
  95 }
  96
  97 int spi_claim_bus(struct spi_slave *slave)
  98 {
  99         struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
 100         struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
 101         uint32_t reg = 0;
 102
 103         mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
 104
 105         writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
 106
 107         reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
 108         reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
 109         reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
 110         writel(reg, &ssp_regs->hw_ssp_ctrl1);
 111
 112         writel(0, &ssp_regs->hw_ssp_cmd0);
 113
 114         mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
 115
 116         return 0;
 117 }
 118
 119 void spi_release_bus(struct spi_slave *slave)
 120 {
 121 }
 122
 123 static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
 124 {
 125         writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
 126         writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
 127 }
 128
 129 static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
 130 {
 131         writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
 132         writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
 133 }
 134
 135 static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
 136                         char *data, int length, int write, unsigned long flags)
 137 {
 138         struct mxs_ssp_regs *ssp_regs = slave->regs;
 139
 140         if (flags & SPI_XFER_BEGIN)
 141                 mxs_spi_start_xfer(ssp_regs);
 142
 143         while (length--) {
 144                 /* We transfer 1 byte */
 145 #if defined(CONFIG_MX23)
 146                 writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
 147                 writel(1, &ssp_regs->hw_ssp_ctrl0_set);
 148 #elif defined(CONFIG_MX28)
 149                 writel(1, &ssp_regs->hw_ssp_xfer_size);
 150 #endif
 151
 152                 if ((flags & SPI_XFER_END) && !length)
 153                         mxs_spi_end_xfer(ssp_regs);
 154
 155                 if (write)
 156                         writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
 157                 else
 158                         writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
 159
 160                 writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
 161
 162                 if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
 163                         SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
 164                         printf("MXS SPI: Timeout waiting for start\n");
 165                         return -ETIMEDOUT;
 166                 }
 167
 168                 if (write)
 169                         writel(*data++, &ssp_regs->hw_ssp_data);
 170
 171                 writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
 172
 173                 if (!write) {
 174                         if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
 175                                 SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
 176                                 printf("MXS SPI: Timeout waiting for data\n");
 177                                 return -ETIMEDOUT;
 178                         }
 179
 180                         *data = readl(&ssp_regs->hw_ssp_data);
 181                         data++;
 182                 }
 183
 184                 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
 185                         SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
 186                         printf("MXS SPI: Timeout waiting for finish\n");
 187                         return -ETIMEDOUT;
 188                 }
 189         }
 190
 191         return 0;
 192 }
 193
 194 static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 195                         char *data, int length, int write, unsigned long flags)
 196 {
 197         const int xfer_max_sz = 0xff00;
 198         const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
 199         struct mxs_ssp_regs *ssp_regs = slave->regs;
 200         struct mxs_dma_desc *dp;
 201         uint32_t ctrl0;
 202         uint32_t cache_data_count;
 203         const uint32_t dstart = (uint32_t)data;
 204         int dmach;
 205         int tl;
 206         int ret = 0;
 207
 208 #if defined(CONFIG_MX23)
 209         const int mxs_spi_pio_words = 1;
 210 #elif defined(CONFIG_MX28)
 211         const int mxs_spi_pio_words = 4;
 212 #endif
 213
 214         ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
 215
 216         memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
 217
 218         ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
 219         ctrl0 |= SSP_CTRL0_DATA_XFER;
 220
 221         if (flags & SPI_XFER_BEGIN)
 222                 ctrl0 |= SSP_CTRL0_LOCK_CS;
 223         if (!write)
 224                 ctrl0 |= SSP_CTRL0_READ;
 225
 226         if (length % ARCH_DMA_MINALIGN)
 227                 cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
 228         else
 229                 cache_data_count = length;
 230
 231         /* Flush data to DRAM so DMA can pick them up */
 232         if (write)
 233                 flush_dcache_range(dstart, dstart + cache_data_count);
 234
 235         /* Invalidate the area, so no writeback into the RAM races with DMA */
 236         invalidate_dcache_range(dstart, dstart + cache_data_count);
 237
 238         dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
 239
 240         dp = desc;
 241         while (length) {
 242                 dp->address = (dma_addr_t)dp;
 243                 dp->cmd.address = (dma_addr_t)data;
 244
 245                 /*
 246                  * This is correct, even though it does indeed look insane.
 247                  * I hereby have to, wholeheartedly, thank Freescale Inc.,
 248                  * for always inventing insane hardware and keeping me busy
 249                  * and employed ;-)
 250                  */
 251                 if (write)
 252                         dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
 253                 else
 254                         dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
 255
 256                 /*
 257                  * The DMA controller can transfer large chunks (64kB) at
 258                  * time by setting the transfer length to 0. Setting tl to
 259                  * 0x10000 will overflow below and make .data contain 0.
 260                  * Otherwise, 0xff00 is the transfer maximum.
 261                  */
 262                 if (length >= 0x10000)
 263                         tl = 0x10000;
 264                 else
 265                         tl = min(length, xfer_max_sz);
 266
 267                 dp->cmd.data |=
 268                         ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
 269                         (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
 270                         MXS_DMA_DESC_HALT_ON_TERMINATE |
 271                         MXS_DMA_DESC_TERMINATE_FLUSH;
 272
 273                 data += tl;
 274                 length -= tl;
 275
 276                 if (!length) {
 277                         dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
 278
 279                         if (flags & SPI_XFER_END) {
 280                                 ctrl0 &= ~SSP_CTRL0_LOCK_CS;
 281                                 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
 282                         }
 283                 }
 284
 285                 /*
 286                  * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
 287                  * case of MX28, write only CTRL0 in case of MX23 due
 288                  * to the difference in register layout. It is utterly
 289                  * essential that the XFER_SIZE register is written on
 290                  * a per-descriptor basis with the same size as is the
 291                  * descriptor!
 292                  */
 293                 dp->cmd.pio_words[0] = ctrl0;
 294 #ifdef CONFIG_MX28
 295                 dp->cmd.pio_words[1] = 0;
 296                 dp->cmd.pio_words[2] = 0;
 297                 dp->cmd.pio_words[3] = tl;
 298 #endif
 299
 300                 mxs_dma_desc_append(dmach, dp);
 301
 302                 dp++;
 303         }
 304
 305         if (mxs_dma_go(dmach))
 306                 ret = -EINVAL;
 307
 308         /* The data arrived into DRAM, invalidate cache over them */
 309         if (!write)
 310                 invalidate_dcache_range(dstart, dstart + cache_data_count);
 311
 312         return ret;
 313 }
 314
 315 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 316                 const void *dout, void *din, unsigned long flags)
 317 {
 318         struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
 319         struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
 320         int len = bitlen / 8;
 321         char dummy;
 322         int write = 0;
 323         char *data = NULL;
 324         int dma = 1;
 325
 326         if (bitlen == 0) {
 327                 if (flags & SPI_XFER_END) {
 328                         din = (void *)&dummy;
 329                         len = 1;
 330                 } else
 331                         return 0;
 332         }
 333
 334         /* Half-duplex only */
 335         if (din && dout)
 336                 return -EINVAL;
 337         /* No data */
 338         if (!din && !dout)
 339                 return 0;
 340
 341         if (dout) {
 342                 data = (char *)dout;
 343                 write = 1;
 344         } else if (din) {
 345                 data = (char *)din;
 346                 write = 0;
 347         }
 348
 349         /*
 350          * Check for alignment, if the buffer is aligned, do DMA transfer,
 351          * PIO otherwise. This is a temporary workaround until proper bounce
 352          * buffer is in place.
 353          */
 354         if (dma) {
 355                 if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
 356                         dma = 0;
 357                 if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
 358                         dma = 0;
 359         }
 360
 361         if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
 362                 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
 363                 return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
 364         } else {
 365                 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
 366                 return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
 367         }
 368 }