drivers/spi/rk_spi.c

   1 /*
   2  * spi driver for rockchip
   3  *
   4  * (C) Copyright 2015 Google, Inc
   5  *
   6  * (C) Copyright 2008-2013 Rockchip Electronics
   7  * Peter, Software Engineering, <superpeter.cai@gmail.com>.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <clk.h>
  14 #include <dm.h>
  15 #include <dt-structs.h>
  16 #include <errno.h>
  17 #include <spi.h>
  18 #include <linux/errno.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/periph.h>
  22 #include <dm/pinctrl.h>
  23 #include "rk_spi.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 /* Change to 1 to output registers at the start of each transaction */
  28 #define DEBUG_RK_SPI    0
  29
  30 struct rockchip_spi_platdata {
  31 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  32         struct dtd_rockchip_rk3288_spi of_plat;
  33 #endif
  34         s32 frequency;          /* Default clock frequency, -1 for none */
  35         fdt_addr_t base;
  36         uint deactivate_delay_us;       /* Delay to wait after deactivate */
  37         uint activate_delay_us;         /* Delay to wait after activate */
  38 };
  39
  40 struct rockchip_spi_priv {
  41         struct rockchip_spi *regs;
  42         struct clk clk;
  43         unsigned int max_freq;
  44         unsigned int mode;
  45         ulong last_transaction_us;      /* Time of last transaction end */
  46         u8 bits_per_word;               /* max 16 bits per word */
  47         u8 n_bytes;
  48         unsigned int speed_hz;
  49         unsigned int last_speed_hz;
  50         unsigned int tmode;
  51         uint input_rate;
  52 };
  53
  54 #define SPI_FIFO_DEPTH          32
  55
  56 static void rkspi_dump_regs(struct rockchip_spi *regs)
  57 {
  58         debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
  59         debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
  60         debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
  61         debug("ser: \t\t0x%08x\n", readl(&regs->ser));
  62         debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
  63         debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
  64         debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
  65         debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
  66         debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
  67         debug("sr: \t\t0x%08x\n", readl(&regs->sr));
  68         debug("imr: \t\t0x%08x\n", readl(&regs->imr));
  69         debug("isr: \t\t0x%08x\n", readl(&regs->isr));
  70         debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
  71         debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
  72         debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
  73 }
  74
  75 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
  76 {
  77         writel(enable ? 1 : 0, &regs->enr);
  78 }
  79
  80 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
  81 {
  82         /*
  83          * We should try not to exceed the speed requested by the caller:
  84          * when selecting a divider, we need to make sure we round up.
  85          */
  86         uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
  87
  88         /* The baudrate register (BAUDR) is defined as a 32bit register where
  89          * the upper 16bit are reserved and having 'Fsclk_out' in the lower
  90          * 16bits with 'Fsclk_out' defined as follows:
  91          *
  92          *   Fsclk_out = Fspi_clk/ SCKDV
  93          *   Where SCKDV is any even value between 2 and 65534.
  94          */
  95         if (clk_div > 0xfffe) {
  96                 clk_div = 0xfffe;
  97                 debug("%s: can't divide down to %d hz (actual will be %d hz)\n",
  98                       __func__, speed, priv->input_rate / clk_div);
  99         }
 100
 101         /* Round up to the next even 16bit number */
 102         clk_div = (clk_div + 1) & 0xfffe;
 103
 104         debug("spi speed %u, div %u\n", speed, clk_div);
 105
 106         clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
 107         priv->last_speed_hz = speed;
 108 }
 109
 110 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
 111 {
 112         unsigned long start;
 113
 114         start = get_timer(0);
 115         while (readl(&regs->sr) & SR_BUSY) {
 116                 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
 117                         debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
 118                         return -ETIMEDOUT;
 119                 }
 120         }
 121
 122         return 0;
 123 }
 124
 125 static void spi_cs_activate(struct udevice *dev, uint cs)
 126 {
 127         struct udevice *bus = dev->parent;
 128         struct rockchip_spi_platdata *plat = bus->platdata;
 129         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 130         struct rockchip_spi *regs = priv->regs;
 131
 132         /* If it's too soon to do another transaction, wait */
 133         if (plat->deactivate_delay_us && priv->last_transaction_us) {
 134                 ulong delay_us;         /* The delay completed so far */
 135                 delay_us = timer_get_us() - priv->last_transaction_us;
 136                 if (delay_us < plat->deactivate_delay_us)
 137                         udelay(plat->deactivate_delay_us - delay_us);
 138         }
 139
 140         debug("activate cs%u\n", cs);
 141         writel(1 << cs, &regs->ser);
 142         if (plat->activate_delay_us)
 143                 udelay(plat->activate_delay_us);
 144 }
 145
 146 static void spi_cs_deactivate(struct udevice *dev, uint cs)
 147 {
 148         struct udevice *bus = dev->parent;
 149         struct rockchip_spi_platdata *plat = bus->platdata;
 150         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 151         struct rockchip_spi *regs = priv->regs;
 152
 153         debug("deactivate cs%u\n", cs);
 154         writel(0, &regs->ser);
 155
 156         /* Remember time of this transaction so we can honour the bus delay */
 157         if (plat->deactivate_delay_us)
 158                 priv->last_transaction_us = timer_get_us();
 159 }
 160
 161 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 162 static int conv_of_platdata(struct udevice *dev)
 163 {
 164         struct rockchip_spi_platdata *plat = dev->platdata;
 165         struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
 166         struct rockchip_spi_priv *priv = dev_get_priv(dev);
 167         int ret;
 168
 169         plat->base = dtplat->reg[0];
 170         plat->frequency = 20000000;
 171         ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
 172         if (ret < 0)
 173                 return ret;
 174         dev->req_seq = 0;
 175
 176         return 0;
 177 }
 178 #endif
 179
 180 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
 181 {
 182 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 183         struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
 184         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 185         int ret;
 186
 187         plat->base = devfdt_get_addr(bus);
 188
 189         ret = clk_get_by_index(bus, 0, &priv->clk);
 190         if (ret < 0) {
 191                 debug("%s: Could not get clock for %s: %d\n", __func__,
 192                       bus->name, ret);
 193                 return ret;
 194         }
 195
 196         plat->frequency =
 197                 dev_read_u32_default(bus, "spi-max-frequency", 50000000);
 198         plat->deactivate_delay_us =
 199                 dev_read_u32_default(bus, "spi-deactivate-delay", 0);
 200         plat->activate_delay_us =
 201                 dev_read_u32_default(bus, "spi-activate-delay", 0);
 202
 203         debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
 204               __func__, (uint)plat->base, plat->frequency,
 205               plat->deactivate_delay_us);
 206 #endif
 207
 208         return 0;
 209 }
 210
 211 static int rockchip_spi_calc_modclk(ulong max_freq)
 212 {
 213         unsigned div;
 214         const unsigned long gpll_hz = 594000000UL;
 215
 216         /*
 217          * We need to find an input clock that provides at least twice
 218          * the maximum frequency and can be generated from the assumed
 219          * speed of GPLL (594MHz) using an integer divider.
 220          *
 221          * To give us more achievable bitrates at higher speeds (these
 222          * are generated by dividing by an even 16-bit integer from
 223          * this frequency), we try to have an input frequency of at
 224          * least 4x our max_freq.
 225          */
 226
 227         div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
 228         return gpll_hz / div;
 229 }
 230
 231 static int rockchip_spi_probe(struct udevice *bus)
 232 {
 233         struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
 234         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 235         int ret;
 236
 237         debug("%s: probe\n", __func__);
 238 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 239         ret = conv_of_platdata(bus);
 240         if (ret)
 241                 return ret;
 242 #endif
 243         priv->regs = (struct rockchip_spi *)plat->base;
 244
 245         priv->last_transaction_us = timer_get_us();
 246         priv->max_freq = plat->frequency;
 247
 248         /* Clamp the value from the DTS against any hardware limits */
 249         if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
 250                 priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
 251
 252         /* Find a module-input clock that fits with the max_freq setting */
 253         ret = clk_set_rate(&priv->clk,
 254                            rockchip_spi_calc_modclk(priv->max_freq));
 255         if (ret < 0) {
 256                 debug("%s: Failed to set clock: %d\n", __func__, ret);
 257                 return ret;
 258         }
 259         priv->input_rate = ret;
 260         debug("%s: rate = %u\n", __func__, priv->input_rate);
 261         priv->bits_per_word = 8;
 262         priv->tmode = TMOD_TR; /* Tx & Rx */
 263
 264         return 0;
 265 }
 266
 267 static int rockchip_spi_claim_bus(struct udevice *dev)
 268 {
 269         struct udevice *bus = dev->parent;
 270         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 271         struct rockchip_spi *regs = priv->regs;
 272         u8 spi_dfs, spi_tf;
 273         uint ctrlr0;
 274
 275         /* Disable the SPI hardware */
 276         rkspi_enable_chip(regs, 0);
 277
 278         switch (priv->bits_per_word) {
 279         case 8:
 280                 priv->n_bytes = 1;
 281                 spi_dfs = DFS_8BIT;
 282                 spi_tf = HALF_WORD_OFF;
 283                 break;
 284         case 16:
 285                 priv->n_bytes = 2;
 286                 spi_dfs = DFS_16BIT;
 287                 spi_tf = HALF_WORD_ON;
 288                 break;
 289         default:
 290                 debug("%s: unsupported bits: %dbits\n", __func__,
 291                       priv->bits_per_word);
 292                 return -EPROTONOSUPPORT;
 293         }
 294
 295         if (priv->speed_hz != priv->last_speed_hz)
 296                 rkspi_set_clk(priv, priv->speed_hz);
 297
 298         /* Operation Mode */
 299         ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
 300
 301         /* Data Frame Size */
 302         ctrlr0 |= spi_dfs << DFS_SHIFT;
 303
 304         /* set SPI mode 0..3 */
 305         if (priv->mode & SPI_CPOL)
 306                 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
 307         if (priv->mode & SPI_CPHA)
 308                 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
 309
 310         /* Chip Select Mode */
 311         ctrlr0 |= CSM_KEEP << CSM_SHIFT;
 312
 313         /* SSN to Sclk_out delay */
 314         ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
 315
 316         /* Serial Endian Mode */
 317         ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
 318
 319         /* First Bit Mode */
 320         ctrlr0 |= FBM_MSB << FBM_SHIFT;
 321
 322         /* Byte and Halfword Transform */
 323         ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
 324
 325         /* Rxd Sample Delay */
 326         ctrlr0 |= 0 << RXDSD_SHIFT;
 327
 328         /* Frame Format */
 329         ctrlr0 |= FRF_SPI << FRF_SHIFT;
 330
 331         /* Tx and Rx mode */
 332         ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
 333
 334         writel(ctrlr0, &regs->ctrlr0);
 335
 336         return 0;
 337 }
 338
 339 static int rockchip_spi_release_bus(struct udevice *dev)
 340 {
 341         struct udevice *bus = dev->parent;
 342         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 343
 344         rkspi_enable_chip(priv->regs, false);
 345
 346         return 0;
 347 }
 348
 349 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
 350                            const void *dout, void *din, unsigned long flags)
 351 {
 352         struct udevice *bus = dev->parent;
 353         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 354         struct rockchip_spi *regs = priv->regs;
 355         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 356         int len = bitlen >> 3;
 357         const u8 *out = dout;
 358         u8 *in = din;
 359         int toread, towrite;
 360         int ret;
 361
 362         debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
 363               len, flags);
 364         if (DEBUG_RK_SPI)
 365                 rkspi_dump_regs(regs);
 366
 367         /* Assert CS before transfer */
 368         if (flags & SPI_XFER_BEGIN)
 369                 spi_cs_activate(dev, slave_plat->cs);
 370
 371         while (len > 0) {
 372                 int todo = min(len, 0xffff);
 373
 374                 rkspi_enable_chip(regs, false);
 375                 writel(todo - 1, &regs->ctrlr1);
 376                 rkspi_enable_chip(regs, true);
 377
 378                 toread = todo;
 379                 towrite = todo;
 380                 while (toread || towrite) {
 381                         u32 status = readl(&regs->sr);
 382
 383                         if (towrite && !(status & SR_TF_FULL)) {
 384                                 writel(out ? *out++ : 0, regs->txdr);
 385                                 towrite--;
 386                         }
 387                         if (toread && !(status & SR_RF_EMPT)) {
 388                                 u32 byte = readl(regs->rxdr);
 389
 390                                 if (in)
 391                                         *in++ = byte;
 392                                 toread--;
 393                         }
 394                 }
 395                 ret = rkspi_wait_till_not_busy(regs);
 396                 if (ret)
 397                         break;
 398                 len -= todo;
 399         }
 400
 401         /* Deassert CS after transfer */
 402         if (flags & SPI_XFER_END)
 403                 spi_cs_deactivate(dev, slave_plat->cs);
 404
 405         rkspi_enable_chip(regs, false);
 406
 407         return ret;
 408 }
 409
 410 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
 411 {
 412         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 413
 414         /* Clamp to the maximum frequency specified in the DTS */
 415         if (speed > priv->max_freq)
 416                 speed = priv->max_freq;
 417
 418         priv->speed_hz = speed;
 419
 420         return 0;
 421 }
 422
 423 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
 424 {
 425         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 426
 427         priv->mode = mode;
 428
 429         return 0;
 430 }
 431
 432 static const struct dm_spi_ops rockchip_spi_ops = {
 433         .claim_bus      = rockchip_spi_claim_bus,
 434         .release_bus    = rockchip_spi_release_bus,
 435         .xfer           = rockchip_spi_xfer,
 436         .set_speed      = rockchip_spi_set_speed,
 437         .set_mode       = rockchip_spi_set_mode,
 438         /*
 439          * cs_info is not needed, since we require all chip selects to be
 440          * in the device tree explicitly
 441          */
 442 };
 443
 444 static const struct udevice_id rockchip_spi_ids[] = {
 445         { .compatible = "rockchip,rk3288-spi" },
 446         { .compatible = "rockchip,rk3399-spi" },
 447         { }
 448 };
 449
 450 U_BOOT_DRIVER(rockchip_spi) = {
 451 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 452         .name   = "rockchip_rk3288_spi",
 453 #else
 454         .name   = "rockchip_spi",
 455 #endif
 456         .id     = UCLASS_SPI,
 457         .of_match = rockchip_spi_ids,
 458         .ops    = &rockchip_spi_ops,
 459         .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
 460         .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
 461         .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
 462         .probe  = rockchip_spi_probe,
 463 };