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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / drivers / usb / usb_ohci.h
1 /*
2 * URB OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * usb-ohci.h
8 */
9
10 /* functions for doing board or CPU specific setup/cleanup */
11 extern int usb_board_init(void);
12 extern int usb_board_stop(void);
13 extern int usb_board_init_fail(void);
14
15 extern int usb_cpu_init(void);
16 extern int usb_cpu_stop(void);
17 extern int usb_cpu_init_fail(void);
18
19
20 static int cc_to_error[16] = {
21
22 /* mapping of the OHCI CC status to error codes */
23 /* No Error */ 0,
24 /* CRC Error */ USB_ST_CRC_ERR,
25 /* Bit Stuff */ USB_ST_BIT_ERR,
26 /* Data Togg */ USB_ST_CRC_ERR,
27 /* Stall */ USB_ST_STALLED,
28 /* DevNotResp */ -1,
29 /* PIDCheck */ USB_ST_BIT_ERR,
30 /* UnExpPID */ USB_ST_BIT_ERR,
31 /* DataOver */ USB_ST_BUF_ERR,
32 /* DataUnder */ USB_ST_BUF_ERR,
33 /* reservd */ -1,
34 /* reservd */ -1,
35 /* BufferOver */ USB_ST_BUF_ERR,
36 /* BuffUnder */ USB_ST_BUF_ERR,
37 /* Not Access */ -1,
38 /* Not Access */ -1
39 };
40
41 /* ED States */
42
43 #define ED_NEW 0x00
44 #define ED_UNLINK 0x01
45 #define ED_OPER 0x02
46 #define ED_DEL 0x04
47 #define ED_URB_DEL 0x08
48
49 /* usb_ohci_ed */
50 struct ed {
51 __u32 hwINFO;
52 __u32 hwTailP;
53 __u32 hwHeadP;
54 __u32 hwNextED;
55
56 struct ed *ed_prev;
57 __u8 int_period;
58 __u8 int_branch;
59 __u8 int_load;
60 __u8 int_interval;
61 __u8 state;
62 __u8 type;
63 __u16 last_iso;
64 struct ed *ed_rm_list;
65
66 struct usb_device *usb_dev;
67 void *purb;
68 __u32 unused[2];
69 } __attribute((aligned(16)));
70 typedef struct ed ed_t;
71
72
73 /* TD info field */
74 #define TD_CC 0xf0000000
75 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
76 #define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
77 #define TD_EC 0x0C000000
78 #define TD_T 0x03000000
79 #define TD_T_DATA0 0x02000000
80 #define TD_T_DATA1 0x03000000
81 #define TD_T_TOGGLE 0x00000000
82 #define TD_R 0x00040000
83 #define TD_DI 0x00E00000
84 #define TD_DI_SET(X) (((X) & 0x07)<< 21)
85 #define TD_DP 0x00180000
86 #define TD_DP_SETUP 0x00000000
87 #define TD_DP_IN 0x00100000
88 #define TD_DP_OUT 0x00080000
89
90 #define TD_ISO 0x00010000
91 #define TD_DEL 0x00020000
92
93 /* CC Codes */
94 #define TD_CC_NOERROR 0x00
95 #define TD_CC_CRC 0x01
96 #define TD_CC_BITSTUFFING 0x02
97 #define TD_CC_DATATOGGLEM 0x03
98 #define TD_CC_STALL 0x04
99 #define TD_DEVNOTRESP 0x05
100 #define TD_PIDCHECKFAIL 0x06
101 #define TD_UNEXPECTEDPID 0x07
102 #define TD_DATAOVERRUN 0x08
103 #define TD_DATAUNDERRUN 0x09
104 #define TD_BUFFEROVERRUN 0x0C
105 #define TD_BUFFERUNDERRUN 0x0D
106 #define TD_NOTACCESSED 0x0F
107
108
109 #define MAXPSW 1
110
111 struct td {
112 __u32 hwINFO;
113 __u32 hwCBP; /* Current Buffer Pointer */
114 __u32 hwNextTD; /* Next TD Pointer */
115 __u32 hwBE; /* Memory Buffer End Pointer */
116
117 /* #ifndef CONFIG_MPC5200 /\* this seems wrong *\/ */
118 __u16 hwPSW[MAXPSW];
119 /* #endif */
120 __u8 unused;
121 __u8 index;
122 struct ed *ed;
123 struct td *next_dl_td;
124 struct usb_device *usb_dev;
125 int transfer_len;
126 __u32 data;
127
128 __u32 unused2[2];
129 } __attribute((aligned(32)));
130 typedef struct td td_t;
131
132 #define OHCI_ED_SKIP (1 << 14)
133
134 /*
135 * The HCCA (Host Controller Communications Area) is a 256 byte
136 * structure defined in the OHCI spec. that the host controller is
137 * told the base address of. It must be 256-byte aligned.
138 */
139
140 #define NUM_INTS 32 /* part of the OHCI standard */
141 struct ohci_hcca {
142 __u32 int_table[NUM_INTS]; /* Interrupt ED table */
143 #if defined(CONFIG_MPC5200)
144 __u16 pad1; /* set to 0 on each frame_no change */
145 __u16 frame_no; /* current frame number */
146 #else
147 __u16 frame_no; /* current frame number */
148 __u16 pad1; /* set to 0 on each frame_no change */
149 #endif
150 __u32 done_head; /* info returned for an interrupt */
151 u8 reserved_for_hc[116];
152 } __attribute((aligned(256)));
153
154
155 /*
156 * Maximum number of root hub ports.
157 */
158 #ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
159 # error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!"
160 #endif
161
162 /*
163 * This is the structure of the OHCI controller's memory mapped I/O
164 * region. This is Memory Mapped I/O. You must use the readl() and
165 * writel() macros defined in asm/io.h to access these!!
166 */
167 struct ohci_regs {
168 /* control and status registers */
169 __u32 revision;
170 __u32 control;
171 __u32 cmdstatus;
172 __u32 intrstatus;
173 __u32 intrenable;
174 __u32 intrdisable;
175 /* memory pointers */
176 __u32 hcca;
177 __u32 ed_periodcurrent;
178 __u32 ed_controlhead;
179 __u32 ed_controlcurrent;
180 __u32 ed_bulkhead;
181 __u32 ed_bulkcurrent;
182 __u32 donehead;
183 /* frame counters */
184 __u32 fminterval;
185 __u32 fmremaining;
186 __u32 fmnumber;
187 __u32 periodicstart;
188 __u32 lsthresh;
189 /* Root hub ports */
190 struct ohci_roothub_regs {
191 __u32 a;
192 __u32 b;
193 __u32 status;
194 __u32 portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS];
195 } roothub;
196 } __attribute((aligned(32)));
197
198 /* Some EHCI controls */
199 #define EHCI_USBCMD_OFF 0x20
200 #define EHCI_USBCMD_HCRESET (1 << 1)
201
202 /* OHCI CONTROL AND STATUS REGISTER MASKS */
203
204 /*
205 * HcControl (control) register masks
206 */
207 #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
208 #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
209 #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
210 #define OHCI_CTRL_CLE (1 << 4) /* control list enable */
211 #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
212 #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
213 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
214 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
215 #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
216
217 /* pre-shifted values for HCFS */
218 # define OHCI_USB_RESET (0 << 6)
219 # define OHCI_USB_RESUME (1 << 6)
220 # define OHCI_USB_OPER (2 << 6)
221 # define OHCI_USB_SUSPEND (3 << 6)
222
223 /*
224 * HcCommandStatus (cmdstatus) register masks
225 */
226 #define OHCI_HCR (1 << 0) /* host controller reset */
227 #define OHCI_CLF (1 << 1) /* control list filled */
228 #define OHCI_BLF (1 << 2) /* bulk list filled */
229 #define OHCI_OCR (1 << 3) /* ownership change request */
230 #define OHCI_SOC (3 << 16) /* scheduling overrun count */
231
232 /*
233 * masks used with interrupt registers:
234 * HcInterruptStatus (intrstatus)
235 * HcInterruptEnable (intrenable)
236 * HcInterruptDisable (intrdisable)
237 */
238 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
239 #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
240 #define OHCI_INTR_SF (1 << 2) /* start frame */
241 #define OHCI_INTR_RD (1 << 3) /* resume detect */
242 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
243 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
244 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
245 #define OHCI_INTR_OC (1 << 30) /* ownership change */
246 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
247
248
249 /* Virtual Root HUB */
250 struct virt_root_hub {
251 int devnum; /* Address of Root Hub endpoint */
252 void *dev; /* was urb */
253 void *int_addr;
254 int send;
255 int interval;
256 };
257
258 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
259
260 /* destination of request */
261 #define RH_INTERFACE 0x01
262 #define RH_ENDPOINT 0x02
263 #define RH_OTHER 0x03
264
265 #define RH_CLASS 0x20
266 #define RH_VENDOR 0x40
267
268 /* Requests: bRequest << 8 | bmRequestType */
269 #define RH_GET_STATUS 0x0080
270 #define RH_CLEAR_FEATURE 0x0100
271 #define RH_SET_FEATURE 0x0300
272 #define RH_SET_ADDRESS 0x0500
273 #define RH_GET_DESCRIPTOR 0x0680
274 #define RH_SET_DESCRIPTOR 0x0700
275 #define RH_GET_CONFIGURATION 0x0880
276 #define RH_SET_CONFIGURATION 0x0900
277 #define RH_GET_STATE 0x0280
278 #define RH_GET_INTERFACE 0x0A80
279 #define RH_SET_INTERFACE 0x0B00
280 #define RH_SYNC_FRAME 0x0C80
281 /* Our Vendor Specific Request */
282 #define RH_SET_EP 0x2000
283
284
285 /* Hub port features */
286 #define RH_PORT_CONNECTION 0x00
287 #define RH_PORT_ENABLE 0x01
288 #define RH_PORT_SUSPEND 0x02
289 #define RH_PORT_OVER_CURRENT 0x03
290 #define RH_PORT_RESET 0x04
291 #define RH_PORT_POWER 0x08
292 #define RH_PORT_LOW_SPEED 0x09
293
294 #define RH_C_PORT_CONNECTION 0x10
295 #define RH_C_PORT_ENABLE 0x11
296 #define RH_C_PORT_SUSPEND 0x12
297 #define RH_C_PORT_OVER_CURRENT 0x13
298 #define RH_C_PORT_RESET 0x14
299
300 /* Hub features */
301 #define RH_C_HUB_LOCAL_POWER 0x00
302 #define RH_C_HUB_OVER_CURRENT 0x01
303
304 #define RH_DEVICE_REMOTE_WAKEUP 0x00
305 #define RH_ENDPOINT_STALL 0x01
306
307 #define RH_ACK 0x01
308 #define RH_REQ_ERR -1
309 #define RH_NACK 0x00
310
311
312 /* OHCI ROOT HUB REGISTER MASKS */
313
314 /* roothub.portstatus [i] bits */
315 #define RH_PS_CCS 0x00000001 /* current connect status */
316 #define RH_PS_PES 0x00000002 /* port enable status*/
317 #define RH_PS_PSS 0x00000004 /* port suspend status */
318 #define RH_PS_POCI 0x00000008 /* port over current indicator */
319 #define RH_PS_PRS 0x00000010 /* port reset status */
320 #define RH_PS_PPS 0x00000100 /* port power status */
321 #define RH_PS_LSDA 0x00000200 /* low speed device attached */
322 #define RH_PS_CSC 0x00010000 /* connect status change */
323 #define RH_PS_PESC 0x00020000 /* port enable status change */
324 #define RH_PS_PSSC 0x00040000 /* port suspend status change */
325 #define RH_PS_OCIC 0x00080000 /* over current indicator change */
326 #define RH_PS_PRSC 0x00100000 /* port reset status change */
327
328 /* roothub.status bits */
329 #define RH_HS_LPS 0x00000001 /* local power status */
330 #define RH_HS_OCI 0x00000002 /* over current indicator */
331 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
332 #define RH_HS_LPSC 0x00010000 /* local power status change */
333 #define RH_HS_OCIC 0x00020000 /* over current indicator change */
334 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
335
336 /* roothub.b masks */
337 #define RH_B_DR 0x0000ffff /* device removable flags */
338 #define RH_B_PPCM 0xffff0000 /* port power control mask */
339
340 /* roothub.a masks */
341 #define RH_A_NDP (0xff << 0) /* number of downstream ports */
342 #define RH_A_PSM (1 << 8) /* power switching mode */
343 #define RH_A_NPS (1 << 9) /* no power switching */
344 #define RH_A_DT (1 << 10) /* device type (mbz) */
345 #define RH_A_OCPM (1 << 11) /* over current protection mode */
346 #define RH_A_NOCP (1 << 12) /* no over current protection */
347 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
348
349 /* urb */
350 #define N_URB_TD 48
351 typedef struct
352 {
353 ed_t *ed;
354 __u16 length; /* number of tds associated with this request */
355 __u16 td_cnt; /* number of tds already serviced */
356 struct usb_device *dev;
357 int state;
358 unsigned long pipe;
359 void *transfer_buffer;
360 int transfer_buffer_length;
361 int interval;
362 int actual_length;
363 int finished;
364 td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
365 } urb_priv_t;
366 #define URB_DEL 1
367
368 /*
369 * This is the full ohci controller description
370 *
371 * Note how the "proper" USB information is just
372 * a subset of what the full implementation needs. (Linus)
373 */
374
375
376 typedef struct ohci {
377 struct ohci_hcca *hcca; /* hcca */
378 /*dma_addr_t hcca_dma;*/
379
380 int irq;
381 int disabled; /* e.g. got a UE, we're hung */
382 int sleeping;
383 unsigned long flags; /* for HC bugs */
384
385 struct ohci_regs *regs; /* OHCI controller's memory */
386
387 int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
388 ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
389 ed_t *ed_bulktail; /* last endpoint of bulk list */
390 ed_t *ed_controltail; /* last endpoint of control list */
391 int intrstatus;
392 __u32 hc_control; /* copy of the hc control reg */
393 struct usb_device *dev[32];
394 struct virt_root_hub rh;
395
396 const char *slot_name;
397 } ohci_t;
398
399 #define NUM_EDS 8 /* num of preallocated endpoint descriptors */
400
401 struct ohci_device {
402 ed_t ed[NUM_EDS];
403 int ed_cnt;
404 };
405
406 /* hcd */
407 /* endpoint */
408 static int ep_link(ohci_t * ohci, ed_t * ed);
409 static int ep_unlink(ohci_t * ohci, ed_t * ed);
410 static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe,
411 int interval, int load);
412
413 /*-------------------------------------------------------------------------*/
414
415 /* we need more TDs than EDs */
416 #define NUM_TD 64
417
418 /* +1 so we can align the storage */
419 td_t gtd[NUM_TD+1];
420 /* pointers to aligned storage */
421 td_t *ptd;
422
423 /* TDs ... */
424 static inline struct td *
425 td_alloc (struct usb_device *usb_dev)
426 {
427 int i;
428 struct td *td;
429
430 td = NULL;
431 for (i = 0; i < NUM_TD; i++)
432 {
433 if (ptd[i].usb_dev == NULL)
434 {
435 td = &ptd[i];
436 td->usb_dev = usb_dev;
437 break;
438 }
439 }
440
441 return td;
442 }
443
444 static inline void
445 ed_free (struct ed *ed)
446 {
447 ed->usb_dev = NULL;
448 }