]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/video/rockchip/rk_vop.c
aa6ca8c859566a97d090c4a105389db0d533def9
2 * Copyright (c) 2015 Google, Inc
3 * Copyright 2014 Rockchip Inc.
5 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/hardware.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/cru_rk3288.h>
21 #include <asm/arch/grf_rk3288.h>
22 #include <asm/arch/edp_rk3288.h>
23 #include <asm/arch/vop_rk3288.h>
24 #include <dm/device-internal.h>
25 #include <dm/uclass-internal.h>
26 #include <dt-bindings/clock/rk3288-cru.h>
27 #include <power/regulator.h>
29 DECLARE_GLOBAL_DATA_PTR
;
32 struct rk3288_vop
*regs
;
33 struct rk3288_grf
*grf
;
36 void rkvop_enable(struct rk3288_vop
*regs
, ulong fbbase
,
37 int fb_bits_per_pixel
, const struct display_timing
*edid
)
41 u32 hactive
= edid
->hactive
.typ
;
42 u32 vactive
= edid
->vactive
.typ
;
44 writel(V_ACT_WIDTH(hactive
- 1) | V_ACT_HEIGHT(vactive
- 1),
45 ®s
->win0_act_info
);
47 writel(V_DSP_XST(edid
->hsync_len
.typ
+ edid
->hback_porch
.typ
) |
48 V_DSP_YST(edid
->vsync_len
.typ
+ edid
->vback_porch
.typ
),
51 writel(V_DSP_WIDTH(hactive
- 1) |
52 V_DSP_HEIGHT(vactive
- 1),
53 ®s
->win0_dsp_info
);
55 clrsetbits_le32(®s
->win0_color_key
, M_WIN0_KEY_EN
| M_WIN0_KEY_COLOR
,
56 V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
58 switch (fb_bits_per_pixel
) {
61 writel(V_RGB565_VIRWIDTH(hactive
), ®s
->win0_vir
);
65 writel(V_RGB888_VIRWIDTH(hactive
), ®s
->win0_vir
);
70 writel(V_ARGB888_VIRWIDTH(hactive
), ®s
->win0_vir
);
75 lb_mode
= LB_RGB_3840X2
;
76 else if (hactive
> 1920)
77 lb_mode
= LB_RGB_2560X4
;
78 else if (hactive
> 1280)
79 lb_mode
= LB_RGB_1920X5
;
81 lb_mode
= LB_RGB_1280X8
;
83 clrsetbits_le32(®s
->win0_ctrl0
,
84 M_WIN0_LB_MODE
| M_WIN0_DATA_FMT
| M_WIN0_EN
,
85 V_WIN0_LB_MODE(lb_mode
) | V_WIN0_DATA_FMT(rgb_mode
) |
88 writel(fbbase
, ®s
->win0_yrgb_mst
);
89 writel(0x01, ®s
->reg_cfg_done
); /* enable reg config */
92 void rkvop_mode_set(struct rk3288_vop
*regs
,
93 const struct display_timing
*edid
, enum vop_modes mode
)
95 u32 hactive
= edid
->hactive
.typ
;
96 u32 vactive
= edid
->vactive
.typ
;
97 u32 hsync_len
= edid
->hsync_len
.typ
;
98 u32 hback_porch
= edid
->hback_porch
.typ
;
99 u32 vsync_len
= edid
->vsync_len
.typ
;
100 u32 vback_porch
= edid
->vback_porch
.typ
;
101 u32 hfront_porch
= edid
->hfront_porch
.typ
;
102 u32 vfront_porch
= edid
->vfront_porch
.typ
;
108 clrsetbits_le32(®s
->sys_ctrl
, M_ALL_OUT_EN
,
113 clrsetbits_le32(®s
->sys_ctrl
, M_ALL_OUT_EN
,
117 clrsetbits_le32(®s
->sys_ctrl
, M_ALL_OUT_EN
,
121 clrsetbits_le32(®s
->sys_ctrl
, M_ALL_OUT_EN
,
126 if (mode
== VOP_MODE_HDMI
|| mode
== VOP_MODE_EDP
)
133 flags
= V_DSP_OUT_MODE(mode_flags
) |
134 V_DSP_HSYNC_POL(!!(edid
->flags
& DISPLAY_FLAGS_HSYNC_HIGH
)) |
135 V_DSP_VSYNC_POL(!!(edid
->flags
& DISPLAY_FLAGS_VSYNC_HIGH
));
137 clrsetbits_le32(®s
->dsp_ctrl0
,
138 M_DSP_OUT_MODE
| M_DSP_VSYNC_POL
| M_DSP_HSYNC_POL
,
141 writel(V_HSYNC(hsync_len
) |
142 V_HORPRD(hsync_len
+ hback_porch
+ hactive
+ hfront_porch
),
143 ®s
->dsp_htotal_hs_end
);
145 writel(V_HEAP(hsync_len
+ hback_porch
+ hactive
) |
146 V_HASP(hsync_len
+ hback_porch
),
147 ®s
->dsp_hact_st_end
);
149 writel(V_VSYNC(vsync_len
) |
150 V_VERPRD(vsync_len
+ vback_porch
+ vactive
+ vfront_porch
),
151 ®s
->dsp_vtotal_vs_end
);
153 writel(V_VAEP(vsync_len
+ vback_porch
+ vactive
)|
154 V_VASP(vsync_len
+ vback_porch
),
155 ®s
->dsp_vact_st_end
);
157 writel(V_HEAP(hsync_len
+ hback_porch
+ hactive
) |
158 V_HASP(hsync_len
+ hback_porch
),
159 ®s
->post_dsp_hact_info
);
161 writel(V_VAEP(vsync_len
+ vback_porch
+ vactive
)|
162 V_VASP(vsync_len
+ vback_porch
),
163 ®s
->post_dsp_vact_info
);
165 writel(0x01, ®s
->reg_cfg_done
); /* enable reg config */
169 * rk_display_init() - Try to enable the given display device
171 * This function performs many steps:
172 * - Finds the display device being referenced by @ep_node
173 * - Puts the VOP's ID into its uclass platform data
174 * - Probes the device to set it up
175 * - Reads the EDID timing information
176 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
177 * - Enables the display (the display device handles this and will do different
178 * things depending on the display type)
179 * - Tells the uclass about the display resolution so that the console will
182 * @dev: VOP device that we want to connect to the display
183 * @fbbase: Frame buffer address
184 * @ep_node: Device tree node to process - this is the offset of an endpoint
185 * node within the VOP's 'port' list.
186 * @return 0 if OK, -ve if something went wrong
188 int rk_display_init(struct udevice
*dev
, ulong fbbase
, int ep_node
)
190 struct video_priv
*uc_priv
= dev_get_uclass_priv(dev
);
191 const void *blob
= gd
->fdt_blob
;
192 struct rk_vop_priv
*priv
= dev_get_priv(dev
);
193 int vop_id
, remote_vop_id
;
194 struct rk3288_vop
*regs
= priv
->regs
;
195 struct display_timing timing
;
196 struct udevice
*disp
;
197 int ret
, remote
, i
, offset
;
198 struct display_plat
*disp_uc_plat
;
200 enum video_log2_bpp l2bpp
;
202 vop_id
= fdtdec_get_int(blob
, ep_node
, "reg", -1);
203 debug("vop_id=%d\n", vop_id
);
204 remote
= fdtdec_lookup_phandle(blob
, ep_node
, "remote-endpoint");
207 remote_vop_id
= fdtdec_get_int(blob
, remote
, "reg", -1);
208 debug("remote vop_id=%d\n", remote_vop_id
);
210 for (i
= 0, offset
= remote
; i
< 3 && offset
> 0; i
++)
211 offset
= fdt_parent_offset(blob
, offset
);
213 debug("%s: Invalid remote-endpoint position\n", dev
->name
);
217 ret
= uclass_find_device_by_of_offset(UCLASS_DISPLAY
, offset
, &disp
);
219 debug("%s: device '%s' display not found (ret=%d)\n", __func__
,
224 disp_uc_plat
= dev_get_uclass_platdata(disp
);
225 debug("Found device '%s', disp_uc_priv=%p\n", disp
->name
, disp_uc_plat
);
226 if (display_in_use(disp
)) {
227 debug(" - device in use\n");
231 disp_uc_plat
->source_id
= remote_vop_id
;
232 disp_uc_plat
->src_dev
= dev
;
234 ret
= device_probe(disp
);
236 debug("%s: device '%s' display won't probe (ret=%d)\n",
237 __func__
, dev
->name
, ret
);
241 ret
= display_read_timing(disp
, &timing
);
243 debug("%s: Failed to read timings\n", __func__
);
247 ret
= clk_get_by_index(dev
, 1, &clk
);
249 ret
= clk_set_rate(&clk
, timing
.pixelclock
.typ
);
250 if (IS_ERR_VALUE(ret
)) {
251 debug("%s: Failed to set pixel clock: ret=%d\n", __func__
, ret
);
255 /* Set bitwidth for vop display according to vop mode */
268 rkvop_mode_set(regs
, &timing
, vop_id
);
270 rkvop_enable(regs
, fbbase
, 1 << l2bpp
, &timing
);
272 ret
= display_enable(disp
, 1 << l2bpp
, &timing
);
276 uc_priv
->xsize
= timing
.hactive
.typ
;
277 uc_priv
->ysize
= timing
.vactive
.typ
;
278 uc_priv
->bpix
= l2bpp
;
279 debug("fb=%lx, size=%d %d\n", fbbase
, uc_priv
->xsize
, uc_priv
->ysize
);
284 static int rk_vop_probe(struct udevice
*dev
)
286 struct video_uc_platdata
*plat
= dev_get_uclass_platdata(dev
);
287 const void *blob
= gd
->fdt_blob
;
288 struct rk_vop_priv
*priv
= dev_get_priv(dev
);
292 /* Before relocation we don't need to do anything */
293 if (!(gd
->flags
& GD_FLG_RELOC
))
296 priv
->grf
= syscon_get_first_range(ROCKCHIP_SYSCON_GRF
);
297 priv
->regs
= (struct rk3288_vop
*)dev_get_addr(dev
);
299 /* lcdc(vop) iodomain select 1.8V */
300 rk_setreg(&priv
->grf
->io_vsel
, 1 << 0);
303 * Try some common regulators. We should really get these from the
304 * device tree somehow.
306 ret
= regulator_autoset_by_name("vcc18_lcd", ®
);
308 debug("%s: Cannot autoset regulator vcc18_lcd\n", __func__
);
309 ret
= regulator_autoset_by_name("VCC18_LCD", ®
);
311 debug("%s: Cannot autoset regulator VCC18_LCD\n", __func__
);
312 ret
= regulator_autoset_by_name("vdd10_lcd_pwren_h", ®
);
314 debug("%s: Cannot autoset regulator vdd10_lcd_pwren_h\n",
317 ret
= regulator_autoset_by_name("vdd10_lcd", ®
);
319 debug("%s: Cannot autoset regulator vdd10_lcd\n",
322 ret
= regulator_autoset_by_name("VDD10_LCD", ®
);
324 debug("%s: Cannot autoset regulator VDD10_LCD\n",
327 ret
= regulator_autoset_by_name("vcc33_lcd", ®
);
329 debug("%s: Cannot autoset regulator vcc33_lcd\n", __func__
);
332 * Try all the ports until we find one that works. In practice this
333 * tries EDP first if available, then HDMI.
335 * Note that rockchip_vop_set_clk() always uses NPLL as the source
336 * clock so it is currently not possible to use more than one display
337 * device simultaneously.
339 port
= fdt_subnode_offset(blob
, dev_of_offset(dev
), "port");
342 for (node
= fdt_first_subnode(blob
, port
);
344 node
= fdt_next_subnode(blob
, node
)) {
345 ret
= rk_display_init(dev
, plat
->base
, node
);
347 debug("Device failed: ret=%d\n", ret
);
351 video_set_flush_dcache(dev
, 1);
356 static int rk_vop_bind(struct udevice
*dev
)
358 struct video_uc_platdata
*plat
= dev_get_uclass_platdata(dev
);
360 plat
->size
= 1920 * 1200 * 4;
365 static const struct video_ops rk_vop_ops
= {
368 static const struct udevice_id rk_vop_ids
[] = {
369 { .compatible
= "rockchip,rk3399-vop-big" },
370 { .compatible
= "rockchip,rk3399-vop-lit" },
371 { .compatible
= "rockchip,rk3288-vop" },
375 U_BOOT_DRIVER(rk_vop
) = {
378 .of_match
= rk_vop_ids
,
381 .probe
= rk_vop_probe
,
382 .priv_auto_alloc_size
= sizeof(struct rk_vop_priv
),