include/configs/B2.h

   1 /*
   2  * (C) Copyright 2004
   3  * DAVE Srl
   4  *
   5  * http://www.dave-tech.it
   6  * http://www.wawnet.biz
   7  * mailto:info@wawnet.biz
   8  *
   9  * Configuation settings for the B2 board.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * If we are developing, we might want to start armboot from ram
  35  * so we MUST NOT initialize critical regs like mem-timing ...
  36  */
  37 #define CONFIG_INIT_CRITICAL
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43 #define CONFIG_ARM7                     1       /* This is a ARM7 CPU   */
  44 #define CONFIG_B2                       1       /* on an B2 Board      */
  45 #define CONFIG_ARM_THUMB        1       /* this is an ARM7TDMI */
  46 #undef  CONFIG_ARM7_REVD                /* disable ARM720 REV.D Workarounds */
  47
  48 #define CONFIG_S3C44B0_CLOCK_SPEED      75 /* we have a 75Mhz S3C44B0*/
  49
  50
  51 #undef CONFIG_USE_IRQ                   /* don't need them anymore */
  52
  53
  54 /*
  55  * Size of malloc() pool
  56  */
  57 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
  58 #define CFG_ENV_SIZE            1024            /* 1024 bytes may be used for env vars*/
  59 #define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 128*1024 )
  60 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
  61
  62 /*
  63  * Hardware drivers
  64  */
  65 #define CONFIG_DRIVER_LAN91C96
  66 #define CONFIG_LAN91C96_BASE            0x04000300 /* base address         */
  67 #define CONFIG_SMC_USE_32_BIT
  68 #undef  CONFIG_SHOW_ACTIVITY
  69 #define CONFIG_NET_RETRY_COUNT          10         /* # of retries          */
  70
  71 /*
  72  * select serial console configuration
  73  */
  74 #define CONFIG_SERIAL1          1       /* we use Serial line 1 */
  75
  76 /* allow to overwrite serial and ethaddr */
  77 #define CONFIG_ENV_OVERWRITE
  78
  79 #define CONFIG_BAUDRATE         115200
  80
  81 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
  82
  83 #define CONFIG_COMMANDS         ( CONFIG_CMD_DFL | \
  84                                                                 CFG_CMD_DATE | \
  85                                                                 CFG_CMD_ELF     | \
  86                                                                 CFG_CMD_EEPROM  | \
  87                                                                 CFG_CMD_I2C     )
  88
  89 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  90 #include <cmd_confdefs.h>
  91
  92 #define CONFIG_BOOTDELAY        5
  93 #define CONFIG_ETHADDR  00:50:c2:1e:af:fb
  94 #define CONFIG_BOOTARGS  "setenv bootargs root=/dev/ram ip=192.168.0.70:::::eth0:off \
  95                                                          ether=25,0,0,0,eth0 ethaddr=00:50:c2:1e:af:fb"
  96 #define CONFIG_NETMASK  255.255.0.0
  97 #define CONFIG_IPADDR   192.168.0.70
  98 #define CONFIG_SERVERIP 192.168.0.23
  99 #define CONFIG_BOOTFILE "B2-rootfs/usr/B2-zImage.u-boot"
 100 #define CONFIG_BOOTCOMMAND      "bootm 20000 f0000"
 101
 102 /*
 103  * Miscellaneous configurable options
 104  */
 105 #define CFG_LONGHELP                            /* undef to save memory         */
 106 #define CFG_PROMPT              "=>  "  /* Monitor Command Prompt       */
 107 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 108 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 109 #define CFG_MAXARGS             16              /* max number of command args   */
 110 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 111
 112 #define CFG_MEMTEST_START       0x0C400000      /* memtest works on     */
 113 #define CFG_MEMTEST_END         0x0C800000      /* 4 ... 8 MB in DRAM   */
 114
 115 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 116
 117 #define CFG_LOAD_ADDR           0x0c700000      /* default load address */
 118
 119 #define CFG_HZ                          1000            /* 1 kHz */
 120
 121                                                 /* valid baudrates */
 122 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 123
 124 /*-----------------------------------------------------------------------
 125  * Stack sizes
 126  *
 127  * The stack sizes are set up in start.S using the settings below
 128  */
 129 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 130 #ifdef CONFIG_USE_IRQ
 131 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 132 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 133 #endif
 134
 135 /*-----------------------------------------------------------------------
 136  * Physical Memory Map
 137  */
 138 #define CONFIG_NR_DRAM_BANKS    1          /* we have 1 banks of DRAM */
 139 #define PHYS_SDRAM_1            0xc0000000 /* SDRAM Bank #1 */
 140 #define PHYS_SDRAM_1_SIZE       0x01000000 /* 16 MB */
 141
 142 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 143 #define PHYS_FLASH_SIZE         0x00400000 /* 4 MB */
 144
 145 #define CFG_FLASH_BASE          PHYS_FLASH_1
 146
 147 /*-----------------------------------------------------------------------
 148  * FLASH and environment organization
 149  */
 150 /*-----------------------------------------------------------------------
 151  * FLASH organization
 152  */
 153 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 154 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 155
 156 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 157 #define CFG_FLASH_WRITE_TOUT    1000    /* Timeout for Flash Write (in ms)      */
 158
 159 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 160 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 161 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 162 /*
 163  * The following defines are added for buggy IOP480 byte interface.
 164  * All other boards should use the standard values (CPCI405 etc.)
 165  */
 166 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 167 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 168 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 169
 170 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 171
 172 /*-----------------------------------------------------------------------
 173  * Environment Variable setup
 174  */
 175 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 176 #define CFG_ENV_OFFSET          0x0     /* environment starts at the beginning of the EEPROM */
 177
 178 /*-----------------------------------------------------------------------
 179  * I2C EEPROM (STM24C02W6) for environment
 180  */
 181 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 182 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 183 #define CFG_I2C_SLAVE           0xFE
 184
 185 #define CFG_I2C_EEPROM_ADDR     0xA8    /* EEPROM STM24C02W6            */
 186 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 187 /* mask of address bits that overflow into the "EEPROM chip address"    */
 188 /*#define CFG_I2C_EEPROM_ADDR_OVERFLOW  0x07*/
 189 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 190                                         /* 16 byte page write mode using*/
 191                                         /* last 4 bits of the address   */
 192 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 193 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 194
 195 /* Flash banks JFFS2 should use */
 196 /*
 197 #define CFG_JFFS2_FIRST_BANK    0
 198 #define CFG_JFFS2_FIRST_SECTOR  2
 199 #define CFG_JFFS2_NUM_BANKS     1
 200 */
 201
 202 /*
 203         Linux TAGs (see lib_arm/armlinux.c)
 204 */
 205 #define CONFIG_CMDLINE_TAG
 206 #undef CONFIG_SETUP_MEMORY_TAGS
 207 #define CONFIG_INITRD_TAG
 208
 209 #endif  /* __CONFIG_H */