include/configs/M52277EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF52277 EVB board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M52277EVB_H
  15 #define _M52277EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M52277EVB        /* M52277EVB board */
  22
  23 #define CONFIG_MCFUART
  24 #define CONFIG_SYS_UART_PORT            (0)
  25
  26 #undef CONFIG_WATCHDOG
  27
  28 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  29
  30 /*
  31  * BOOTP options
  32  */
  33 #define CONFIG_BOOTP_BOOTFILESIZE
  34 #define CONFIG_BOOTP_BOOTPATH
  35 #define CONFIG_BOOTP_GATEWAY
  36 #define CONFIG_BOOTP_HOSTNAME
  37
  38 #define CONFIG_HOSTNAME                 M52277EVB
  39 #define CONFIG_SYS_UBOOT_END            0x3FFFF
  40 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
  41 #ifdef CONFIG_SYS_STMICRO_BOOT
  42 /* ST Micro serial flash */
  43 #define CONFIG_EXTRA_ENV_SETTINGS               \
  44         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  45         "loadaddr=0x40010000\0"                 \
  46         "uboot=u-boot.bin\0"                    \
  47         "load=loadb ${loadaddr} ${baudrate};"   \
  48         "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"   \
  49         "upd=run load; run prog\0"              \
  50         "prog=sf probe 0:2 10000 1;"            \
  51         "sf erase 0 30000;"                     \
  52         "sf write ${loadaddr} 0 30000;"         \
  53         "save\0"                                \
  54         ""
  55 #endif
  56 #ifdef CONFIG_SYS_SPANSION_BOOT
  57 #define CONFIG_EXTRA_ENV_SETTINGS               \
  58         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  59         "loadaddr=0x40010000\0"                 \
  60         "uboot=u-boot.bin\0"                    \
  61         "load=loadb ${loadaddr} ${baudrate}\0"  \
  62         "upd=run load; run prog\0"              \
  63         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
  64         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
  65         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
  66         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
  67         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
  68         " ${filesize}; save\0"                  \
  69         "updsbf=run loadsbf; run progsbf\0"     \
  70         "loadsbf=loadb ${loadaddr} ${baudrate};"        \
  71         "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"   \
  72         "progsbf=sf probe 0:2 10000 1;"         \
  73         "sf erase 0 30000;"                     \
  74         "sf write ${loadaddr} 0 30000;"         \
  75         ""
  76 #endif
  77
  78 /* LCD */
  79 #ifdef CONFIG_CMD_BMP
  80 #define CONFIG_SPLASH_SCREEN
  81 #define CONFIG_LCD_LOGO
  82 #define CONFIG_SHARP_LQ035Q7DH06
  83 #endif
  84
  85 /* USB */
  86 #ifdef CONFIG_CMD_USB
  87 #define CONFIG_SYS_USB_EHCI_REGS_BASE   0xFC0B0000
  88 #define CONFIG_SYS_USB_EHCI_CPU_INIT
  89 #endif
  90
  91 /* Realtime clock */
  92 #define CONFIG_MCFRTC
  93 #undef RTC_DEBUG
  94 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
  95
  96 /* Timer */
  97 #define CONFIG_MCFTMR
  98 #undef CONFIG_MCFPIT
  99
 100 /* I2c */
 101 #define CONFIG_SYS_I2C
 102 #define CONFIG_SYS_I2C_FSL
 103 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 104 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 105 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 106 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 107
 108 /* DSPI and Serial Flash */
 109 #define CONFIG_CF_SPI
 110 #define CONFIG_CF_DSPI
 111 #define CONFIG_HARD_SPI
 112 #define CONFIG_SYS_SBFHDR_SIZE          0x7
 113 #ifdef CONFIG_CMD_SPI
 114 #       define CONFIG_SYS_DSPI_CS2
 115
 116 #       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
 117                                          DSPI_CTAR_PCSSCK_1CLK | \
 118                                          DSPI_CTAR_PASC(0) | \
 119                                          DSPI_CTAR_PDT(0) | \
 120                                          DSPI_CTAR_CSSCK(0) | \
 121                                          DSPI_CTAR_ASC(0) | \
 122                                          DSPI_CTAR_DT(1))
 123 #endif
 124
 125 /* Input, PCI, Flexbus, and VCO */
 126 #define CONFIG_EXTRA_CLOCK
 127
 128 #define CONFIG_SYS_INPUT_CLKSRC 16000000
 129
 130 #define CONFIG_PRAM             2048    /* 2048 KB */
 131
 132 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 133
 134 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 135 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 136
 137 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_SDRAM_BASE + 0x10000)
 138
 139 #define CONFIG_SYS_MBAR         0xFC000000
 140
 141 /*
 142  * Low Level Configuration Settings
 143  * (address mappings, register initial values, etc.)
 144  * You should know what you are doing if you make changes here.
 145  */
 146
 147 /*
 148  * Definitions for initial stack pointer and data area (in DPRAM)
 149  */
 150 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 151 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
 152 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 153 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 154 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 155 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 156
 157 /*
 158  * Start addresses for the final memory configuration
 159  * (Set up by the startup code)
 160  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 161  */
 162 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 163 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
 164 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 165 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 166 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 167 #define CONFIG_SYS_SDRAM_EMOD           0x81810000
 168 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 169 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0x00
 170
 171 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 172 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 173
 174 #ifdef CONFIG_CF_SBF
 175 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 176 #else
 177 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 178 #endif
 179 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 180 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 181 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 182
 183 /* Initial Memory map for Linux */
 184 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 185 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 186
 187 /*
 188  * Configuration for environment
 189  * Environment is not embedded in u-boot. First time runing may have env
 190  * crc error warning if there is no correct environment on the flash.
 191  */
 192 #ifdef CONFIG_CF_SBF
 193 #       define CONFIG_ENV_SPI_CS        2
 194 #endif
 195 #define CONFIG_ENV_OVERWRITE            1
 196
 197 /*-----------------------------------------------------------------------
 198  * FLASH organization
 199  */
 200 #ifdef CONFIG_SYS_STMICRO_BOOT
 201 #       define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_CS0_BASE
 202 #       define CONFIG_SYS_FLASH0_BASE   CONFIG_SYS_CS0_BASE
 203 #       define CONFIG_ENV_OFFSET        0x30000
 204 #       define CONFIG_ENV_SIZE          0x1000
 205 #       define CONFIG_ENV_SECT_SIZE     0x10000
 206 #endif
 207 #ifdef CONFIG_SYS_SPANSION_BOOT
 208 #       define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_CS0_BASE
 209 #       define CONFIG_SYS_FLASH0_BASE   CONFIG_SYS_CS0_BASE
 210 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 211 #       define CONFIG_ENV_SIZE          0x1000
 212 #       define CONFIG_ENV_SECT_SIZE     0x8000
 213 #endif
 214
 215 #define CONFIG_SYS_FLASH_CFI
 216 #ifdef CONFIG_SYS_FLASH_CFI
 217 #       define CONFIG_FLASH_CFI_DRIVER  1
 218 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 219 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 220 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 221 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 222 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 223 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 224 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 225 #       define CONFIG_SYS_FLASH_CHECKSUM
 226 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE }
 227 #endif
 228
 229 #define LDS_BOARD_TEXT \
 230         arch/m68k/cpu/mcf5227x/built-in.o   (.text*) \
 231         arch/m68k/lib/built-in.o            (.text*)
 232
 233 /*
 234  * This is setting for JFFS2 support in u-boot.
 235  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 236  */
 237 #ifdef CONFIG_CMD_JFFS2
 238 #       define CONFIG_JFFS2_DEV         "nor0"
 239 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x40000)
 240 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
 241 #endif
 242
 243 /*-----------------------------------------------------------------------
 244  * Cache Configuration
 245  */
 246 #define CONFIG_SYS_CACHELINE_SIZE       16
 247
 248 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 249                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 250 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 251                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 252 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 253 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 254                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 255                                          CF_ACR_EN | CF_ACR_SM_ALL)
 256 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 257                                          CF_CACR_DISD | CF_CACR_INVI | \
 258                                          CF_CACR_CEIB | CF_CACR_DCM | \
 259                                          CF_CACR_EUSP)
 260
 261 /*-----------------------------------------------------------------------
 262  * Memory bank definitions
 263  */
 264 /*
 265  * CS0 - NOR Flash
 266  * CS1 - Available
 267  * CS2 - Available
 268  * CS3 - Available
 269  * CS4 - Available
 270  * CS5 - Available
 271  */
 272
 273 #ifdef CONFIG_CF_SBF
 274 #define CONFIG_SYS_CS0_BASE             0x04000000
 275 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 276 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 277 #else
 278 #define CONFIG_SYS_CS0_BASE             0x00000000
 279 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 280 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 281 #endif
 282
 283 #endif                          /* _M52277EVB_H */