include/configs/M54418TWR.h

   1 /*
   2  * Configuation settings for the Freescale MCF54418 TWR board.
   3  *
   4  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54418TWR_H
  15 #define _M54418TWR_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M54418TWR        /* M54418TWR board */
  22
  23 #define CONFIG_MCFUART
  24 #define CONFIG_SYS_UART_PORT            (0)
  25 #define CONFIG_BAUDRATE         115200
  26 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600 , 19200 , 38400 , 57600, 115200 }
  27
  28 #undef CONFIG_WATCHDOG
  29
  30 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  31
  32 /*
  33  * BOOTP options
  34  */
  35 #define CONFIG_BOOTP_BOOTFILESIZE
  36 #define CONFIG_BOOTP_BOOTPATH
  37 #define CONFIG_BOOTP_GATEWAY
  38 #define CONFIG_BOOTP_HOSTNAME
  39
  40 /* Command line configuration */
  41 #define CONFIG_CMD_CACHE
  42 #undef CONFIG_CMD_DATE
  43 #undef CONFIG_CMD_JFFS2
  44 #undef CONFIG_CMD_UBI
  45 #define CONFIG_CMD_MII
  46 #undef CONFIG_CMD_NAND
  47 #define CONFIG_CMD_REGINFO
  48
  49 /*
  50  * NAND FLASH
  51  */
  52 #ifdef CONFIG_CMD_NAND
  53 #define CONFIG_JFFS2_NAND
  54 #define CONFIG_NAND_FSL_NFC
  55 #define CONFIG_SYS_NAND_BASE            0xFC0FC000
  56 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  57 #define NAND_MAX_CHIPS                  CONFIG_SYS_MAX_NAND_DEVICE
  58 #define CONFIG_SYS_NAND_SELECT_DEVICE
  59 #endif
  60
  61 /* Network configuration */
  62 #define CONFIG_MCFFEC
  63 #ifdef CONFIG_MCFFEC
  64 #define CONFIG_MII                      1
  65 #define CONFIG_MII_INIT         1
  66 #define CONFIG_SYS_DISCOVER_PHY
  67 #define CONFIG_SYS_RX_ETH_BUFFER        2
  68 #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
  69 #define CONFIG_SYS_TX_ETH_BUFFER        2
  70 #define CONFIG_HAS_ETH1
  71
  72 #define CONFIG_SYS_FEC0_PINMUX          0
  73 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  74 #define CONFIG_SYS_FEC1_PINMUX          0
  75 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
  76 #define MCFFEC_TOUT_LOOP                50000
  77 #define CONFIG_SYS_FEC0_PHYADDR 0
  78 #define CONFIG_SYS_FEC1_PHYADDR 1
  79
  80 #define CONFIG_BOOTDELAY                2       /* autoboot after 5 seconds */
  81
  82 #ifdef  CONFIG_SYS_NAND_BOOT
  83 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \
  84                                 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
  85                                 "-(jffs2) console=ttyS0,115200"
  86 #else
  87 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot="     \
  88                                 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \
  89                                 __stringify(CONFIG_IPADDR) "  ip="      \
  90                                 __stringify(CONFIG_IPADDR) ":"  \
  91                                 __stringify(CONFIG_SERVERIP)":" \
  92                                 __stringify(CONFIG_GATEWAYIP)": "       \
  93                                 __stringify(CONFIG_NETMASK)             \
  94                                 "::eth0:off:rw console=ttyS0,115200"
  95 #endif
  96
  97 #define CONFIG_ETHPRIME "FEC0"
  98 #define CONFIG_IPADDR           192.168.1.2
  99 #define CONFIG_NETMASK          255.255.255.0
 100 #define CONFIG_SERVERIP 192.168.1.1
 101 #define CONFIG_GATEWAYIP        192.168.1.1
 102
 103 #define CONFIG_SYS_FEC_BUF_USE_SRAM
 104 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
 105 #ifndef CONFIG_SYS_DISCOVER_PHY
 106 #define FECDUPLEX       FULL
 107 #define FECSPEED        _100BASET
 108 #define LINKSTATUS      1
 109 #else
 110 #define LINKSTATUS      0
 111 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 112 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 113 #endif
 114 #endif                  /* CONFIG_SYS_DISCOVER_PHY */
 115 #endif
 116
 117 #define CONFIG_HOSTNAME         M54418TWR
 118
 119 #if defined(CONFIG_CF_SBF)
 120 /* ST Micro serial flash */
 121 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
 122 #define CONFIG_EXTRA_ENV_SETTINGS               \
 123         "netdev=eth0\0"                         \
 124         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 125         "loadaddr=0x40010000\0"                 \
 126         "sbfhdr=sbfhdr.bin\0"                   \
 127         "uboot=u-boot.bin\0"                    \
 128         "load=tftp ${loadaddr} ${sbfhdr};"      \
 129         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
 130         "upd=run load; run prog\0"              \
 131         "prog=sf probe 0:1 1000000 3;"          \
 132         "sf erase 0 40000;"                     \
 133         "sf write ${loadaddr} 0 40000;"         \
 134         "save\0"                                \
 135         ""
 136 #elif defined(CONFIG_SYS_NAND_BOOT)
 137 #define CONFIG_EXTRA_ENV_SETTINGS               \
 138         "netdev=eth0\0"                         \
 139         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 140         "loadaddr=0x40010000\0"                 \
 141         "u-boot=u-boot.bin\0"                   \
 142         "load=tftp ${loadaddr} ${u-boot};\0"    \
 143         "upd=run load; run prog\0"              \
 144         "prog=nand device 0;"                   \
 145         "nand erase 0 40000;"                   \
 146         "nb_update ${loadaddr} ${filesize};"    \
 147         "save\0"                                \
 148         ""
 149 #else
 150 #define CONFIG_SYS_UBOOT_END    0x3FFFF
 151 #define CONFIG_EXTRA_ENV_SETTINGS               \
 152         "netdev=eth0\0"                         \
 153         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 154         "loadaddr=40010000\0"                   \
 155         "u-boot=u-boot.bin\0"                   \
 156         "load=tftp ${loadaddr) ${u-boot}\0"     \
 157         "upd=run load; run prog\0"              \
 158         "prog=prot off mram" " ;"       \
 159         "cp.b ${loadaddr} 0 ${filesize};"       \
 160         "save\0"                                \
 161         ""
 162 #endif
 163
 164 /* Realtime clock */
 165 #undef CONFIG_MCFRTC
 166 #define CONFIG_RTC_MCFRRTC
 167 #define CONFIG_SYS_MCFRRTC_BASE         0xFC0A8000
 168
 169 /* Timer */
 170 #define CONFIG_MCFTMR
 171 #undef CONFIG_MCFPIT
 172
 173 /* I2c */
 174 #undef CONFIG_SYS_FSL_I2C
 175 #undef CONFIG_HARD_I2C          /* I2C with hardware support */
 176 #undef  CONFIG_SYS_I2C_SOFT     /* I2C bit-banged */
 177 /* I2C speed and slave address  */
 178 #define CONFIG_SYS_I2C_SPEED            80000
 179 #define CONFIG_SYS_I2C_SLAVE            0x7F
 180 #define CONFIG_SYS_I2C_OFFSET           0x58000
 181 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 182
 183 /* DSPI and Serial Flash */
 184 #define CONFIG_CF_SPI
 185 #define CONFIG_CF_DSPI
 186 #define CONFIG_SERIAL_FLASH
 187 #define CONFIG_HARD_SPI
 188 #define CONFIG_SYS_SBFHDR_SIZE          0x7
 189 #ifdef CONFIG_CMD_SPI
 190
 191 #       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
 192                                          DSPI_CTAR_PCSSCK_1CLK | \
 193                                          DSPI_CTAR_PASC(0) | \
 194                                          DSPI_CTAR_PDT(0) | \
 195                                          DSPI_CTAR_CSSCK(0) | \
 196                                          DSPI_CTAR_ASC(0) | \
 197                                          DSPI_CTAR_DT(1))
 198 #       define CONFIG_SYS_DSPI_CTAR1    (CONFIG_SYS_DSPI_CTAR0)
 199 #       define CONFIG_SYS_DSPI_CTAR2    (CONFIG_SYS_DSPI_CTAR0)
 200 #endif
 201
 202 /* Input, PCI, Flexbus, and VCO */
 203 #define CONFIG_EXTRA_CLOCK
 204
 205 #define CONFIG_PRAM                     2048    /* 2048 KB */
 206
 207 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 208
 209 #if defined(CONFIG_CMD_KGDB)
 210 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 211 #else
 212 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 213 #endif
 214 /* Print Buffer Size */
 215 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 216                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 217 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 218 /* Boot Argument Buffer Size    */
 219 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 220
 221 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 222
 223 #define CONFIG_SYS_MBAR         0xFC000000
 224
 225 /*
 226  * Low Level Configuration Settings
 227  * (address mappings, register initial values, etc.)
 228  * You should know what you are doing if you make changes here.
 229  */
 230
 231 /*-----------------------------------------------------------------------
 232  * Definitions for initial stack pointer and data area (in DPRAM)
 233  */
 234 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 235 /* End of used area in internal SRAM */
 236 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
 237 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 238 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - \
 239                                         GENERATED_GBL_DATA_SIZE) - 32)
 240 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 241 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 242
 243 /*-----------------------------------------------------------------------
 244  * Start addresses for the final memory configuration
 245  * (Set up by the startup code)
 246  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 247  */
 248 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 249 #define CONFIG_SYS_SDRAM_SIZE           128     /* SDRAM size in MB */
 250
 251 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE + 0x400)
 252 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 253 #define CONFIG_SYS_DRAM_TEST
 254
 255 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
 256 #define CONFIG_SERIAL_BOOT
 257 #endif
 258
 259 #if defined(CONFIG_SERIAL_BOOT)
 260 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
 261 #else
 262 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 263 #endif
 264
 265 #define CONFIG_SYS_BOOTPARAMS_LEN       (64 * 1024)
 266 /* Reserve 256 kB for Monitor */
 267 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)
 268 /* Reserve 256 kB for malloc() */
 269 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 270
 271 /*
 272  * For booting Linux, the board info and command line data
 273  * have to be in the first 8 MB of memory, since this is
 274  * the maximum mapped by the Linux kernel during initialization ??
 275  */
 276 /* Initial Memory map for Linux */
 277 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
 278                                 (CONFIG_SYS_SDRAM_SIZE << 20))
 279
 280 /* Configuration for environment
 281  * Environment is embedded in u-boot in the second sector of the flash
 282  */
 283 #if !defined(CONFIG_SERIAL_BOOT)  /*MRAM boot*/
 284 #define CONFIG_SYS_NO_FLASH
 285 #define CONFIG_ENV_IS_IN_MRAM   1
 286 #define CONFIG_ENV_ADDR         (0x40000 - 0x1000) /*MRAM size 40000*/
 287 #define CONFIG_ENV_SIZE         0x1000
 288 #endif
 289
 290 #if defined(CONFIG_CF_SBF)
 291 #define CONFIG_SYS_NO_FLASH
 292 #define CONFIG_ENV_IS_IN_SPI_FLASH      1
 293 #define CONFIG_ENV_SPI_CS               1
 294 #define CONFIG_ENV_OFFSET               0x40000
 295 #define CONFIG_ENV_SIZE         0x2000
 296 #define CONFIG_ENV_SECT_SIZE            0x10000
 297 #endif
 298 #if defined(CONFIG_SYS_NAND_BOOT)
 299 #define CONFIG_SYS_NO_FLASH
 300 #define CONFIG_ENV_IS_NOWHERE
 301 #define CONFIG_ENV_OFFSET       0x80000
 302 #define CONFIG_ENV_SIZE 0x20000
 303 #define CONFIG_ENV_SECT_SIZE    0x20000
 304 #endif
 305 #undef CONFIG_ENV_OVERWRITE
 306
 307 /* FLASH organization */
 308 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 309
 310 #undef CONFIG_SYS_FLASH_CFI
 311 #ifdef CONFIG_SYS_FLASH_CFI
 312
 313 #define CONFIG_FLASH_CFI_DRIVER 1
 314 /* Max size that the board might have */
 315 #define CONFIG_SYS_FLASH_SIZE           0x1000000
 316 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 317 /* max number of memory banks */
 318 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 319 /* max number of sectors on one chip */
 320 #define CONFIG_SYS_MAX_FLASH_SECT       270
 321 /* "Real" (hardware) sectors protection */
 322 #define CONFIG_SYS_FLASH_PROTECTION
 323 #define CONFIG_SYS_FLASH_CHECKSUM
 324 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_CS0_BASE }
 325 #else
 326 /* max number of sectors on one chip */
 327 #define CONFIG_SYS_MAX_FLASH_SECT       270
 328 /* max number of sectors on one chip */
 329 #define CONFIG_SYS_MAX_FLASH_BANKS      0
 330 #endif
 331
 332 /*
 333  * This is setting for JFFS2 support in u-boot.
 334  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 335  */
 336 #ifdef CONFIG_CMD_JFFS2
 337 #define CONFIG_JFFS2_DEV                "nand0"
 338 #define CONFIG_JFFS2_PART_OFFSET        (0x800000)
 339 #define CONFIG_CMD_MTDPARTS
 340 #define CONFIG_MTD_DEVICE
 341 #define MTDIDS_DEFAULT          "nand0=m54418twr.nand"
 342
 343 #define MTDPARTS_DEFAULT        "mtdparts=m54418twr.nand:1m(data),"     \
 344                                                 "7m(kernel),"           \
 345                                                 "-(rootfs)"
 346
 347 #endif
 348
 349 #ifdef CONFIG_CMD_UBI
 350 #define CONFIG_CMD_MTDPARTS
 351 #define CONFIG_MTD_DEVICE       /* needed for mtdparts command */
 352 #define CONFIG_MTD_PARTITIONS   /* mtdparts and UBI support */
 353 #define CONFIG_RBTREE
 354 #define MTDIDS_DEFAULT          "nand0=NAND"
 355 #define MTDPARTS_DEFAULT        "mtdparts=NAND:1m(u-boot),"     \
 356                                         "-(ubi)"
 357 #endif
 358 /* Cache Configuration */
 359 #define CONFIG_SYS_CACHELINE_SIZE       16
 360 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 361                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 362 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 363                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 364 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 365 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 366 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 367                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 368                                          CF_ACR_EN | CF_ACR_SM_ALL)
 369 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 370                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 371 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 372                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 373                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 374
 375 #define CACR_STATUS     (CONFIG_SYS_INIT_RAM_ADDR + \
 376                         CONFIG_SYS_INIT_RAM_SIZE - 12)
 377
 378 /*-----------------------------------------------------------------------
 379  * Memory bank definitions
 380  */
 381 /*
 382  * CS0 - NOR Flash 16MB
 383  * CS1 - Available
 384  * CS2 - Available
 385  * CS3 - Available
 386  * CS4 - Available
 387  * CS5 - Available
 388  */
 389
 390  /* Flash */
 391 #define CONFIG_SYS_CS0_BASE             0x00000000
 392 #define CONFIG_SYS_CS0_MASK             0x000F0101
 393 #define CONFIG_SYS_CS0_CTRL             0x00001D60
 394
 395 #endif                          /* _M54418TWR_H */